diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/quick/se | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/quick/se')
26 files changed, 13754 insertions, 13769 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index eedb7e6a0..f228f639d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 34993500 # Number of ticks simulated -final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000038 # Number of seconds simulated +sim_ticks 37928000 # Number of ticks simulated +final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25302 # Simulator instruction rate (inst/s) -host_op_rate 25300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138325772 # Simulator tick rate (ticks/s) -host_mem_usage 279800 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 174102 # Simulator instruction rate (inst/s) +host_op_rate 174036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1031016392 # Simulator tick rate (ticks/s) +host_mem_usage 293404 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 665723634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309085973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 665723634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309085973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34895000 # Total gap between requests +system.physmem.totGap 37822500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 365.511111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 232.220198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.209697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22 24.44% 24.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 24 26.67% 51.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3849750 # Total ticks spent queuing -system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.714286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.680361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.730884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19 22.62% 22.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 23.81% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.57% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.38% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 7.14% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 10.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation +system.physmem.totQLat 3251500 # Total ticks spent queuing +system.physmem.totMemAccLat 13245250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.62 # Data bus utilization in percentage -system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.03 # Data bus utilization in percentage +system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 435 # Number of row buffer hits during reads +system.physmem.readRowHits 437 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65469.04 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 70961.54 # Average gap between requests +system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ) -system.physmem_0.averagePower 827.438306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) +system.physmem_0.averagePower 825.080242 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ) -system.physmem_1.averagePower 815.785757 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states +system.physmem_1.actBackEnergy 20293425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1041750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25416240 # Total energy per rank (pJ) +system.physmem_1.averagePower 809.305525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1595750 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1972 # Number of BP lookups -system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1968 # Number of BP lookups +system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups system.cpu.branchPred.BTBHits 385 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 2254 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2268 # DTB accesses -system.cpu.itb.fetch_hits 2642 # ITB hits +system.cpu.itb.fetch_hits 2639 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2659 # ITB accesses +system.cpu.itb.fetch_accesses 2656 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,80 +293,80 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 69987 # number of cpu cycles simulated +system.cpu.numCycles 75856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.935469 # CPI: cycles per instruction -system.cpu.ipc 0.091446 # IPC: instructions per cycle -system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.852500 # CPI: cycles per instruction +system.cpu.ipc 0.084370 # IPC: instructions per cycle +system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked +system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.036694 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025400 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1233 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1973 # number of overall hits -system.cpu.dcache.overall_hits::total 1973 # number of overall hits +system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits +system.cpu.dcache.overall_hits::total 1975 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses -system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7703250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8670250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16373500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1335 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 124 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses +system.cpu.dcache.overall_misses::total 226 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2200 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2200 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.103182 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.103182 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75522.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69362 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,12 +377,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 51 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70123.287671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076783 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076783 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5649 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits -system.cpu.icache.overall_hits::total 2277 # number of overall hits +system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5643 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits +system.cpu.icache.overall_hits::total 2274 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28333250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28333250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28333250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28333250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28333250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77625.342466 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77625.342466 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77625.342466 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77625.342466 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27622250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27622250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27622250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75677.397260 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75677.397260 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.387081 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.091079 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.671740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.765541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.621541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007122 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -534,17 +534,17 @@ system.cpu.l2cache.demand_misses::total 533 # nu system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24623500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7033500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5044000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24623500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12077500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24623500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12077500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 34712000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27246250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12756000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40002250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27246250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12756000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40002250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) @@ -567,17 +567,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67646.978022 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73265.625000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69095.890411 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74852.335165 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77768.229167 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75460.869565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75051.125704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75051.125704 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,17 +597,17 @@ system.cpu.l2cache.demand_mshr_misses::total 533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20056500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5835000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9973000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20056500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9973000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6259250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28945500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10637500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33323750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10637500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33323750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55100.274725 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60781.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -654,10 +654,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 629250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 286000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 460 # Transaction distribution system.membus.trans_dist::ReadResp 460 # Transaction distribution @@ -678,9 +678,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.2 # Layer utilization (%) +system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 7064bc28f..edf4ba710 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20537500 # Number of ticks simulated -final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22074000 # Number of ticks simulated +final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92569 # Simulator instruction rate (inst/s) -host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 298254404 # Simulator tick rate (ticks/s) -host_mem_usage 293992 # Number of bytes of host memory used +host_inst_rate 94896 # Simulator instruction rate (inst/s) +host_op_rate 94876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 328609283 # Simulator tick rate (ticks/s) +host_mem_usage 293652 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975386488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 542227632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1517614121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975386488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975386488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975386488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 542227632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1517614121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 487 # Number of read requests accepted +system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 907492978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 501585576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1409078554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 907492978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 907492978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 907492978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 501585576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1409078554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31168 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31168 # Total read bytes from the system interface side +system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::6 1 # Pe system.physmem.perBankRdBursts::7 3 # Per bank write bursts system.physmem.perBankRdBursts::8 0 # Per bank write bursts system.physmem.perBankRdBursts::9 1 # Per bank write bursts -system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 25 # Per bank write bursts system.physmem.perBankRdBursts::12 14 # Per bank write bursts system.physmem.perBankRdBursts::13 120 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20412000 # Total gap between requests +system.physmem.totGap 21941500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 487 # Read request sizes (log2) +system.physmem.readPktSize::6 486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,100 +186,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.853659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 204.819475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.253502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28 34.15% 34.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 20.73% 54.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 10.98% 65.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 9.76% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.88% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.22% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation -system.physmem.totQLat 4742750 # Total ticks spent queuing -system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.818416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.662840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation +system.physmem.totQLat 4363750 # Total ticks spent queuing +system.physmem.totMemAccLat 13476250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8978.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27728.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1409.08 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1409.08 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.86 # Data bus utilization in percentage -system.physmem.busUtilRead 11.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.01 # Data bus utilization in percentage +system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 390 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41913.76 # Average gap between requests -system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 45147.12 # Average gap between requests +system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) -system.physmem_0.averagePower 881.195525 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) +system.physmem_0.averagePower 873.750829 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 118250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) -system.physmem_1.averagePower 864.696352 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states +system.physmem_1.actBackEnergy 10123200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 619500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13518075 # Total energy per rank (pJ) +system.physmem_1.averagePower 853.818096 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 963500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14362750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2806 # Number of BP lookups -system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2808 # Number of BP lookups +system.cpu.branchPred.condPredicted 1660 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 686 # Number of BTB hits +system.cpu.branchPred.BTBHits 676 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.007576 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 398 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2085 # DTB read hits -system.cpu.dtb.read_misses 55 # DTB read misses +system.cpu.dtb.read_hits 2105 # DTB read hits +system.cpu.dtb.read_misses 56 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2140 # DTB read accesses -system.cpu.dtb.write_hits 1069 # DTB write hits +system.cpu.dtb.read_accesses 2161 # DTB read accesses +system.cpu.dtb.write_hits 1074 # DTB write hits system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1099 # DTB write accesses -system.cpu.dtb.data_hits 3154 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1104 # DTB write accesses +system.cpu.dtb.data_hits 3179 # DTB hits +system.cpu.dtb.data_misses 86 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3239 # DTB accesses -system.cpu.itb.fetch_hits 2196 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3265 # DTB accesses +system.cpu.itb.fetch_hits 2195 # ITB hits +system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2234 # ITB accesses +system.cpu.itb.fetch_accesses 2229 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,237 +292,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41076 # number of cpu cycles simulated +system.cpu.numCycles 44149 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8744 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16221 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2806 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1081 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4165 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 8603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1074 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4302 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 801 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2196 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.137917 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 735 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2195 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 341 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.147127 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.556854 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11405 80.01% 80.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.03% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.51% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 201 1.41% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 243 1.70% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 210 1.47% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 240 1.68% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 179 1.26% 91.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1273 8.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11330 79.87% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 287 2.02% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 214 1.51% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 242 1.71% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 209 1.47% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 241 1.70% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 178 1.25% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1280 9.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068312 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394902 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8821 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2387 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2410 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 194 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 14185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.063603 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.368570 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8626 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2413 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 199 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 229 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14785 # Number of instructions handled by decode +system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14877 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8987 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1032 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 429 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 8799 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1077 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 424 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2422 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 942 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 42 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 850 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17814 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17805 # Number of integer rename lookups +system.cpu.rename.UnblockCycles 1020 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14259 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 32 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 922 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10782 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17904 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17895 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6153 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6212 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 504 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1309 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.skidInsts 534 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12936 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10718 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6142 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3483 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10742 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6197 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3553 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14255 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.751877 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.757279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.490412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10249 71.90% 71.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1278 8.97% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 900 6.31% 87.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 686 4.81% 91.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 522 3.66% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 330 2.31% 97.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 1.49% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.36% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10181 71.77% 71.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1265 8.92% 80.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 910 6.42% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 677 4.77% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 530 3.74% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 330 2.33% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 213 1.50% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 54 0.38% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 25 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14255 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14185 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 30 20.69% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 73 50.34% 71.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 42 28.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 19.86% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 74 50.68% 70.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 43 29.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7258 67.72% 67.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2331 21.75% 89.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1124 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7248 67.47% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2358 21.95% 89.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10718 # Type of FU issued -system.cpu.iq.rate 0.260931 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013529 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19060 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9783 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10742 # Type of FU issued +system.cpu.iq.rate 0.243312 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013592 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35814 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19169 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9787 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10850 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10875 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1477 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 444 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1002 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12999 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1309 # Number of dispatched store instructions +system.cpu.iew.iewBlockCycles 1035 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13050 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 470 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10224 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2143 # Number of load instructions executed +system.cpu.iew.branchMispredicts 472 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10248 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2164 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3244 # number of memory reference insts executed -system.cpu.iew.exec_branches 1603 # Number of branches executed -system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.248904 # Inst execution rate -system.cpu.iew.wb_sent 9953 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9793 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5300 # num instructions producing a value -system.cpu.iew.wb_consumers 7279 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3270 # number of memory reference insts executed +system.cpu.iew.exec_branches 1599 # Number of branches executed +system.cpu.iew.exec_stores 1106 # Number of stores executed +system.cpu.iew.exec_rate 0.232123 # Inst execution rate +system.cpu.iew.wb_sent 9960 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9797 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5308 # num instructions producing a value +system.cpu.iew.wb_consumers 7306 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.238412 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.728122 # average fanout of values written-back +system.cpu.iew.wb_rate 0.221908 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.726526 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6609 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6660 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.404730 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10600 81.22% 81.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1162 8.90% 90.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 501 3.84% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.62% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 133 1.02% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 75 0.57% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 89 0.68% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 89 0.68% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 191 1.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10525 81.07% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1166 8.98% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 505 3.89% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 137 1.06% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 75 0.58% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12983 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,187 +568,187 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction -system.cpu.commit.bw_lim_events 191 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25507 # The number of ROB reads -system.cpu.rob.rob_writes 27214 # The number of ROB writes -system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25491 # The number of ROB reads +system.cpu.rob.rob_writes 27316 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.446328 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads -system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12992 # number of integer regfile reads -system.cpu.int_regfile_writes 7455 # number of integer regfile writes +system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144329 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144329 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13019 # number of integer regfile reads +system.cpu.int_regfile_writes 7461 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.596270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2347 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.566474 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits -system.cpu.dcache.overall_hits::total 2314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 107.596270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5893 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5893 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2347 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2347 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2347 # number of overall hits +system.cpu.dcache.overall_hits::total 2347 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 157 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses +system.cpu.dcache.overall_misses::total 513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12056250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12056250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24043225 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24043225 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36099475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36099475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36099475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36099475 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078697 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078697 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.179371 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.179371 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.179371 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.179371 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70369.346979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70369.346979 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2245 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.078947 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 340 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 340 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8557250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8557250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5645250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5645250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14202500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14202500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050627 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.060490 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.060490 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.400693 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1716 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.471338 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.464968 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.374396 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077331 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077331 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.400693 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077344 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077344 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4706 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4706 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1718 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1718 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1718 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1718 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1718 # number of overall hits -system.cpu.icache.overall_hits::total 1718 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses -system.cpu.icache.overall_misses::total 478 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31723500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31723500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31723500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31723500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31723500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31723500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2196 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2196 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2196 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2196 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2196 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2196 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217668 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217668 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217668 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217668 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217668 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217668 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66367.154812 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66367.154812 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66367.154812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66367.154812 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4704 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4704 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1716 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1716 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1716 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1716 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1716 # number of overall hits +system.cpu.icache.overall_hits::total 1716 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses +system.cpu.icache.overall_misses::total 479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34067500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34067500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34067500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2195 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2195 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218223 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.218223 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.218223 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.218223 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.218223 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.218223 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71122.129436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71122.129436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71122.129436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71122.129436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,54 +757,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22315500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22315500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142987 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142987 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71068.471338 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71068.471338 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24276250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24276250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24276250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24276250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24276250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24276250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143052 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143052 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143052 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77312.898089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77312.898089 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77312.898089 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77312.898089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77312.898089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77312.898089 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.773509 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.195035 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.460945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60.312564 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.471795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60.723240 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006676 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4391 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4391 # Number of data accesses +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001853 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006689 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4382 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4382 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -813,60 +812,60 @@ system.cpu.l2cache.demand_hits::total 1 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses -system.cpu.l2cache.overall_misses::total 487 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21990500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7915750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29906250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5408750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5408750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21990500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13324500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35315000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21990500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13324500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35315000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses +system.cpu.l2cache.overall_misses::total 486 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8448250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 32399000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5570250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5570250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37969250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14018500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37969250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70257.188498 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77605.392157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.253012 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75121.527778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75121.527778 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72515.400411 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72515.400411 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76519.968051 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83646.039604 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.454106 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77364.583333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77364.583333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76519.968051 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81031.791908 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78126.028807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76519.968051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81031.791908 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78126.028807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -876,100 +875,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18043000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6661250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24704250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4522750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4522750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11184000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29227000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11184000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29227000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20032750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7188250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 27221000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11862500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31895250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20032750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11862500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31895250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57645.367412 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65306.372549 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59528.313253 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62815.972222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62815.972222 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64002.396166 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71170.792079 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65751.207729 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64920.138889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64920.138889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 535750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 285500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadReq 414 # Transaction distribution +system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::samples 486 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 487 # Request fanout histogram -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.2 # Layer utilization (%) +system.membus.snoop_fanout::total 486 # Request fanout histogram +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2581250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index dcfebc3a2..95d6f5391 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32544000 # Number of ticks simulated -final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32544500 # Number of ticks simulated +final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 485157 # Simulator instruction rate (inst/s) -host_op_rate 484642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2465828156 # Simulator tick rate (ticks/s) -host_mem_usage 286540 # Number of bytes of host memory used +host_inst_rate 643051 # Simulator instruction rate (inst/s) +host_op_rate 642147 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3266208350 # Simulator tick rate (ticks/s) +host_mem_usage 291356 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 373 # Transaction distribution -system.membus.trans_dist::ReadResp 373 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 446 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 446 # Request fanout histogram -system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.3 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65088 # number of cpu cycles simulated +system.cpu.numCycles 65089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65088 # Number of busy cycles +system.cpu.num_busy_cycles 65089 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -144,15 +121,119 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits +system.cpu.dcache.overall_hits::total 1880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.dcache.overall_misses::total 168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -171,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -189,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -209,33 +290,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy @@ -262,17 +343,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) @@ -295,17 +376,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -325,17 +406,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses @@ -347,122 +428,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits -system.cpu.dcache.overall_hits::total 1880 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses -system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -491,5 +468,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 373 # Transaction distribution +system.membus.trans_dist::ReadResp 373 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 446 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 446 # Request fanout histogram +system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 6a0f7583b..a634edee1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18733500 # Number of ticks simulated -final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20287000 # Number of ticks simulated +final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33056 # Simulator instruction rate (inst/s) -host_op_rate 33048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 239448729 # Simulator tick rate (ticks/s) -host_mem_usage 278492 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 136939 # Simulator instruction rate (inst/s) +host_op_rate 136838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1073215892 # Simulator tick rate (ticks/s) +host_mem_usage 292092 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 761843756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 290388876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 761843756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 290388876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 703504707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 268152019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 971656726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 703504707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 703504707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 703504707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 268152019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 971656726 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18651500 # Total gap between requests +system.physmem.totGap 20198000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 421.209302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.192017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.893842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 23.26% 23.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 18.60% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 6.98% 48.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 6.98% 55.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 13.95% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 9.30% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation -system.physmem.totQLat 1952250 # Total ticks spent queuing -system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 427.707317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 281.056415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.596590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation +system.physmem.totQLat 1763250 # Total ticks spent queuing +system.physmem.totMemAccLat 7538250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5724.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24474.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 971.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 971.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.22 # Data bus utilization in percentage -system.physmem.busUtilRead 8.22 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.59 # Data bus utilization in percentage +system.physmem.busUtilRead 7.59 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 257 # Number of row buffer hits during reads +system.physmem.readRowHits 258 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 60556.82 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined +system.physmem.avgGap 65577.92 # Average gap between requests +system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ) -system.physmem_0.averagePower 806.306964 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states +system.physmem_0.actBackEnergy 10555830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12721485 # Total energy per rank (pJ) +system.physmem_0.averagePower 803.504500 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 765250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14968250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ) -system.physmem_1.averagePower 848.926575 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states +system.physmem_1.actBackEnergy 10492560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 300000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13287405 # Total energy per rank (pJ) +system.physmem_1.averagePower 838.851326 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 458000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14875250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 793 # Number of BP lookups +system.cpu.branchPred.lookups 791 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups system.cpu.branchPred.BTBHits 58 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.320285 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 136 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 816 # DT system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 829 # DTB accesses -system.cpu.itb.fetch_hits 974 # ITB hits +system.cpu.itb.fetch_hits 969 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 987 # ITB accesses +system.cpu.itb.fetch_accesses 982 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,29 +293,29 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 37467 # number of cpu cycles simulated +system.cpu.numCycles 40574 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 596 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 595 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.494004 # CPI: cycles per instruction -system.cpu.ipc 0.068994 # IPC: instructions per cycle -system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked -system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.695938 # CPI: cycles per instruction +system.cpu.ipc 0.063711 # IPC: instructions per cycle +system.cpu.tickCycles 5396 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35178 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.478730 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011836 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.342007 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses @@ -335,14 +335,14 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4644500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3502000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8146500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4962000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4962000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3282500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3282500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8244500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8244500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8244500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8244500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -359,14 +359,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76139.344262 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81441.860465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81344.262295 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81344.262295 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76337.209302 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76337.209302 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79274.038462 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79274.038462 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6389750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4628250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4628250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2009000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2009000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6637250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6637250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6637250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6637250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79797.413793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79797.413793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74407.407407 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74407.407407 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 117.949271 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 746 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.345291 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.949271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057592 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057592 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2171 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2171 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 751 # number of overall hits -system.cpu.icache.overall_hits::total 751 # number of overall hits +system.cpu.icache.tags.tag_accesses 2161 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2161 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 746 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 746 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 746 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 746 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 746 # number of overall hits +system.cpu.icache.overall_hits::total 746 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 974 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 974 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 974 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69163.677130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69163.677130 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17117250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17117250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17117250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17117250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17117250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17117250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 969 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 969 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 969 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230134 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230134 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230134 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230134 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230134 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230134 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76758.968610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76758.968610 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76758.968610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76758.968610 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14884500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16684250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16684250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16684250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16684250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16684250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16684250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230134 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.230134 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.230134 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74817.264574 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74817.264574 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 146.534478 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 145.900805 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.615214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.919264 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003620 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.086871 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.813934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003604 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000849 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004453 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses @@ -528,17 +528,17 @@ system.cpu.l2cache.demand_misses::total 308 # nu system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14661500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4251500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2052250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14661500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6303750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14661500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6303750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16461250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4569250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21030500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1982000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1982000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16461250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6551250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23012500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16461250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6551250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23012500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 223 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 58 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) @@ -561,17 +561,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65746.636771 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73301.724138 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73817.264574 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78780.172414 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74841.637011 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.407407 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.407407 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74715.909091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74715.909091 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,17 +591,17 @@ system.cpu.l2cache.demand_mshr_misses::total 308 system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11864500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3534000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5252250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11864500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5252250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13669750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3841250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17511000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1642000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1642000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13669750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5483250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19153000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13669750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5483250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19153000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -613,17 +613,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53204.035874 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60931.034483 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61299.327354 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66228.448276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62316.725979 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60814.814815 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60814.814815 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution @@ -649,9 +649,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 383750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 143250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution @@ -672,9 +672,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 308 # Request fanout histogram -system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 15.3 # Layer utilization (%) +system.membus.reqLayer0.occupancy 360000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 1638500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 49b58755c..165a7d5f5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11765500 # Number of ticks simulated -final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12774000 # Number of ticks simulated +final_tick 12774000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73154 # Simulator instruction rate (inst/s) -host_op_rate 73124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 360297045 # Simulator tick rate (ticks/s) -host_mem_usage 293708 # Number of bytes of host memory used +host_inst_rate 77109 # Simulator instruction rate (inst/s) +host_op_rate 77075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412290611 # Simulator tick rate (ticks/s) +host_mem_usage 293132 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1017211338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462368790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1479580128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1017211338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1017211338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1017211338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462368790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1479580128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 936903084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425865038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1362768123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 936903084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 936903084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 936903084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425865038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1362768123 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11676000 # Total gap between requests +system.physmem.totGap 12677500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.076923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 220.895953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 363.044972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7 17.95% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 7.69% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 7.69% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.13% 71.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 7.69% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 2.56% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation -system.physmem.totQLat 1802000 # Total ticks spent queuing -system.physmem.totMemAccLat 6902000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation +system.physmem.totQLat 1960500 # Total ticks spent queuing +system.physmem.totMemAccLat 7060500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6625.00 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7207.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25375.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25957.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1362.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1362.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.56 # Data bus utilization in percentage -system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.65 # Data bus utilization in percentage +system.physmem.busUtilRead 10.65 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 223 # Number of row buffer hits during reads +system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42926.47 # Average gap between requests -system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined +system.physmem.avgGap 46608.46 # Average gap between requests +system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 631800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6746115 # Total energy per rank (pJ) -system.physmem_0.averagePower 838.417275 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206000 # Time in different power states +system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) +system.physmem_0.averagePower 832.600901 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7778000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 158760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 86625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 850200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5222340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 7073235 # Total energy per rank (pJ) -system.physmem_1.averagePower 879.072239 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 397500 # Time in different power states +system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 6961470 # Total energy per rank (pJ) +system.physmem_1.averagePower 865.181917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 428500 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7402500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1090 # Number of BP lookups -system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 734 # Number of BTB lookups -system.cpu.branchPred.BTBHits 202 # Number of BTB hits +system.cpu.branchPred.lookups 1106 # Number of BP lookups +system.cpu.branchPred.condPredicted 562 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 735 # Number of BTB lookups +system.cpu.branchPred.BTBHits 214 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 29.115646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 201 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 689 # DTB read hits -system.cpu.dtb.read_misses 23 # DTB read misses +system.cpu.dtb.read_hits 705 # DTB read hits +system.cpu.dtb.read_misses 25 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 712 # DTB read accesses -system.cpu.dtb.write_hits 352 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses +system.cpu.dtb.read_accesses 730 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 370 # DTB write accesses -system.cpu.dtb.data_hits 1041 # DTB hits -system.cpu.dtb.data_misses 41 # DTB misses +system.cpu.dtb.write_accesses 386 # DTB write accesses +system.cpu.dtb.data_hits 1072 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1082 # DTB accesses -system.cpu.itb.fetch_hits 938 # ITB hits +system.cpu.dtb.data_accesses 1116 # DTB accesses +system.cpu.itb.fetch_hits 947 # ITB hits system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 964 # ITB accesses +system.cpu.itb.fetch_accesses 973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23532 # number of cpu cycles simulated +system.cpu.numCycles 25549 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4442 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6549 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1090 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 401 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4412 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 415 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1107 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 938 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 155 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.330561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.910863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.331734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6093 84.50% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 49 0.68% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 123 1.71% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 84 1.16% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 131 1.82% 89.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 58 0.80% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.93% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 62 0.86% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 544 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6194 84.42% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 50 0.68% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 126 1.72% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 86 1.17% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 137 1.87% 89.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 59 0.80% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 69 0.94% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 62 0.85% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 554 7.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.046320 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.278302 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5244 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 757 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 975 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 55 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 180 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 156 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.043289 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.261576 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5200 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 911 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 995 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 54 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 159 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5674 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 180 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5327 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 452 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 942 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 30 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5438 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 5779 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 271 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5279 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 611 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 960 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5531 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6138 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6131 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3966 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6270 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2145 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2198 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 115 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 883 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4685 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4768 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3891 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2057 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3966 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1238 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.539592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.280898 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7337 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.540548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.288327 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5712 79.21% 79.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 492 6.82% 86.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 353 4.90% 90.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 253 3.51% 94.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 197 2.73% 97.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.68% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 52 0.72% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19 0.26% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5813 79.23% 79.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 503 6.86% 86.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 359 4.89% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 255 3.48% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 198 2.70% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 113 1.54% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 62 0.85% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.29% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7337 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 18.97% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 37.93% 56.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 25 43.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2776 71.34% 71.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 739 18.99% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 375 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2817 71.03% 71.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 757 19.09% 90.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 391 9.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3891 # Type of FU issued -system.cpu.iq.rate 0.165349 # Inst issue rate -system.cpu.iq.fu_busy_cnt 51 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013107 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6745 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3580 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3966 # Type of FU issued +system.cpu.iq.rate 0.155231 # Inst issue rate +system.cpu.iq.fu_busy_cnt 58 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014624 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15337 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6922 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3670 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3935 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4017 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 468 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 480 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 180 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 393 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5027 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 538 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5114 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 883 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 22 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 169 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 191 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3755 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 713 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 136 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 188 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3845 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 731 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 121 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 336 # number of nop insts executed -system.cpu.iew.exec_refs 1083 # number of memory reference insts executed -system.cpu.iew.exec_branches 638 # Number of branches executed -system.cpu.iew.exec_stores 370 # Number of stores executed -system.cpu.iew.exec_rate 0.159570 # Inst execution rate -system.cpu.iew.wb_sent 3650 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3586 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1711 # num instructions producing a value -system.cpu.iew.wb_consumers 2190 # num instructions consuming a value +system.cpu.iew.exec_nop 340 # number of nop insts executed +system.cpu.iew.exec_refs 1117 # number of memory reference insts executed +system.cpu.iew.exec_branches 655 # Number of branches executed +system.cpu.iew.exec_stores 386 # Number of stores executed +system.cpu.iew.exec_rate 0.150495 # Inst execution rate +system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3676 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1745 # num instructions producing a value +system.cpu.iew.wb_consumers 2262 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152388 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.781279 # average fanout of values written-back +system.cpu.iew.wb_rate 0.143880 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.771441 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2437 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 157 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6757 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381234 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.252230 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 154 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.374800 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238011 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5909 87.45% 87.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193 2.86% 90.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 297 4.40% 94.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 108 1.60% 96.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.07% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.78% 98.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.49% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22 0.33% 98.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70 1.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6022 87.62% 87.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192 2.79% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 299 4.35% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 111 1.62% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.05% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 55 0.80% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.48% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.29% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6757 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6873 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,102 +568,102 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 70 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11453 # The number of ROB reads -system.cpu.rob.rob_writes 10498 # The number of ROB writes -system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16321 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11659 # The number of ROB reads +system.cpu.rob.rob_writes 10686 # The number of ROB writes +system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18212 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.858400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.858400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.101436 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.101436 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4543 # number of integer regfile reads -system.cpu.int_regfile_writes 2774 # number of integer regfile writes +system.cpu.cpi 10.703393 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.703393 # CPI: Total CPI of All Threads +system.cpu.ipc 0.093428 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.093428 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4655 # number of integer regfile reads +system.cpu.int_regfile_writes 2832 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 46.039302 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 46.039302 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011240 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011240 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits -system.cpu.dcache.overall_hits::total 729 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses -system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1969 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1969 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 218 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 218 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits +system.cpu.dcache.overall_hits::total 743 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses +system.cpu.dcache.overall_misses::total 199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8172750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8172750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5678000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5678000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13850750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13850750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13850750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13850750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 942 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 942 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 942 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 942 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.189815 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.189815 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.258503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.258503 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.211253 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.211253 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.211253 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.211253 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66445.121951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66445.121951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74710.526316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74710.526316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69601.758794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69601.758794 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -672,87 +672,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1841500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1841500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6635000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6635000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090234 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090234 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78581.967213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78581.967213 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 91.893913 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 694 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.663102 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.711230 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 92.065177 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044954 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044954 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.893913 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2063 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2063 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 685 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 685 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 685 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 685 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 685 # number of overall hits -system.cpu.icache.overall_hits::total 685 # number of overall hits +system.cpu.icache.tags.tag_accesses 2081 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2081 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 694 # number of overall hits +system.cpu.icache.overall_hits::total 694 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17329249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17329249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17329249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17329249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17329249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17329249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 938 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 938 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 938 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 938 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.269723 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.269723 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.269723 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.269723 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.269723 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.269723 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68495.055336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68495.055336 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68495.055336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68495.055336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68495.055336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68495.055336 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18914999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18914999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18914999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18914999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18914999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18914999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 947 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 947 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 947 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 947 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.267159 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.267159 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.267159 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.267159 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.267159 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.267159 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74762.841897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74762.841897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74762.841897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74762.841897 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -768,39 +768,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187 system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12893999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12893999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12893999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12893999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12893999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12893999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.199360 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.199360 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.199360 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68951.866310 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68951.866310 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68951.866310 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68951.866310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68951.866310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68951.866310 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14404999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14404999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14404999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14404999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14404999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14404999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.197466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.197466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.197466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77032.080214 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77032.080214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 121.503793 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.236486 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.265551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29.238242 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002816 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000892 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.076745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29.159741 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003700 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses @@ -815,17 +815,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12706250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4451500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17157750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1694250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1694250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12706250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6145750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12706250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6145750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14216750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4732500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18949250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1816000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14216750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6548500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20765250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14216750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6548500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20765250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -848,17 +848,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76025.401070 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77581.967213 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76408.266129 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76342.830882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76342.830882 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -878,17 +878,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10348750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3702000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1400750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1400750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5102750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15451500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5102750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15451500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11881250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15850750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11881250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5489500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17370750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11881250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5489500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17370750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -900,17 +900,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63536.096257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65073.770492 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63914.314516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution @@ -935,10 +935,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 318750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 139500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 248 # Transaction distribution system.membus.trans_dist::ReadResp 248 # Transaction distribution @@ -959,9 +959,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.membus.reqLayer0.occupancy 341000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1440250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 6695f502c..364bc6f05 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16524000 # Number of ticks simulated -final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16524500 # Number of ticks simulated +final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428144 # Simulator instruction rate (inst/s) -host_op_rate 427151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2733498759 # Simulator tick rate (ticks/s) -host_mem_usage 286260 # Number of bytes of host memory used +host_inst_rate 396950 # Simulator instruction rate (inst/s) +host_op_rate 396157 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2535599202 # Simulator tick rate (ticks/s) +host_mem_usage 290048 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 218 # Transaction distribution -system.membus.trans_dist::ReadResp 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 245 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245 # Request fanout histogram -system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 13.3 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33048 # number of cpu cycles simulated +system.cpu.numCycles 33049 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33048 # Number of busy cycles +system.cpu.num_busy_cycles 33049 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -144,15 +121,119 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 47.433873 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 47.433873 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits +system.cpu.dcache.overall_hits::total 627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses +system.cpu.dcache.overall_misses::total 82 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4387000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4387000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 80.042941 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 80.042941 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039083 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039083 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id @@ -171,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -189,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -209,34 +290,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8721000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 8721000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8721000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 8721000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8721000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 8721000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 107.153052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.161341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.991711 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id @@ -256,17 +337,17 @@ system.cpu.l2cache.demand_misses::total 245 # nu system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8558000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11445500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses) @@ -289,17 +370,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,17 +400,17 @@ system.cpu.l2cache.demand_mshr_misses::total 245 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6601500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8829000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3321000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3321000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9922500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -341,122 +422,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits -system.cpu.dcache.overall_hits::total 627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution @@ -485,5 +462,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 218 # Transaction distribution +system.membus.trans_dist::ReadResp 218 # Transaction distribution +system.membus.trans_dist::ReadExReq 27 # Transaction distribution +system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 245 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 245 # Request fanout histogram +system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 452f74fef..a4c548b0e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27981000 # Number of ticks simulated -final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 30427500 # Number of ticks simulated +final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40383 # Simulator instruction rate (inst/s) -host_op_rate 47269 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 245344554 # Simulator tick rate (ticks/s) -host_mem_usage 297404 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 90683 # Simulator instruction rate (inst/s) +host_op_rate 106136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 599001910 # Simulator tick rate (ticks/s) +host_mem_usage 308040 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27895500 # Total gap between requests +system.physmem.totGap 30336000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,75 +187,76 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2478000 # Total ticks spent queuing -system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2605000 # Total ticks spent queuing +system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.52 # Data bus utilization in percentage -system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.92 # Data bus utilization in percentage +system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 350 # Number of row buffer hits during reads +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 66260.10 # Average gap between requests -system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 72057.01 # Average gap between requests +system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) -system.physmem_0.averagePower 856.107753 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ) +system.physmem_0.averagePower 848.018629 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) -system.physmem_1.averagePower 786.272135 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states +system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) +system.physmem_1.averagePower 782.664197 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1926 # Number of BP lookups +system.cpu.branchPred.lookups 1927 # Number of BP lookups system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups system.cpu.branchPred.BTBHits 326 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -376,44 +377,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 55962 # number of cpu cycles simulated +system.cpu.numCycles 60855 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4604 # Number of instructions committed system.cpu.committedOps 5390 # Number of ops (including micro ops) committed system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 12.155083 # CPI: cycles per instruction -system.cpu.ipc 0.082270 # IPC: instructions per cycle -system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked -system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.217854 # CPI: cycles per instruction +system.cpu.ipc 0.075655 # IPC: instructions per cycle +system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits -system.cpu.dcache.overall_hits::total 1900 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits +system.cpu.dcache.overall_hits::total 1899 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -422,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4804 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits -system.cpu.icache.overall_hits::total 1919 # number of overall hits +system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4806 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits +system.cpu.icache.overall_hits::total 1920 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,39 +573,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses @@ -628,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20459750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5689250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2814500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20459750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8503750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20459750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8503750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) @@ -661,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,17 +698,17 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses @@ -719,17 +720,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution @@ -743,25 +744,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 378 # Transaction distribution system.membus.trans_dist::ReadResp 378 # Transaction distribution @@ -782,9 +781,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index bac015830..eb7b98cb0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16223000 # Number of ticks simulated -final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 17307500 # Number of ticks simulated +final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54860 # Simulator instruction rate (inst/s) -host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 193800024 # Simulator tick rate (ticks/s) -host_mem_usage 308908 # Number of bytes of host memory used +host_inst_rate 56147 # Simulator instruction rate (inst/s) +host_op_rate 65749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 211593476 # Simulator tick rate (ticks/s) +host_mem_usage 308560 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1020598007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447436083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1468034089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1020598007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1020598007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1020598007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447436083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1468034089 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16156000 # Total gap between requests +system.physmem.totGap 17240500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,76 +187,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 388.063492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.022879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.382701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.40% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.29% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 84.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3126000 # Total ticks spent queuing -system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3336500 # Total ticks spent queuing +system.physmem.totMemAccLat 10780250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8404.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27154.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1468.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1468.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.24 # Data bus utilization in percentage -system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.47 # Data bus utilization in percentage +system.physmem.busUtilRead 11.47 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40695.21 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43426.95 # Average gap between requests +system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2074800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) -system.physmem_0.averagePower 920.354334 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14395920 # Total energy per rank (pJ) +system.physmem_0.averagePower 909.263856 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) -system.physmem_1.averagePower 810.522027 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states +system.physmem_1.actBackEnergy 10358325 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 414750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12772695 # Total energy per rank (pJ) +system.physmem_1.averagePower 806.611620 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 897000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14679500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2638 # Number of BP lookups -system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2634 # Number of BP lookups +system.cpu.branchPred.condPredicted 1633 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 783 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2098 # Number of BTB lookups +system.cpu.branchPred.BTBHits 781 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 37.225929 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 353 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -495,95 +496,95 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32447 # number of cpu cycles simulated +system.cpu.numCycles 34616 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7775 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12462 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2634 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1134 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4935 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1009 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 273 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2063 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 315 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.090163 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.470015 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10832 80.12% 80.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 265 1.96% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 242 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 236 1.75% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 238 1.76% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.14% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.05% 90.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 172 1.27% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1103 8.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2145 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 13520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076092 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360007 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6427 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4469 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2141 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 348 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12076 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups +system.cpu.rename.SquashCycles 348 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6634 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 859 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2057 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1243 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 177 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1054 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11789 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52593 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12687 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6295 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 43 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 434 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2310 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1632 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10336 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8345 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4743 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12819 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.617234 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373407 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10276 76.01% 76.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1181 8.74% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 737 5.45% 90.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 452 3.34% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 368 2.72% 96.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 2.09% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 137 1.01% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 63 0.47% 99.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available @@ -619,113 +620,113 @@ system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5033 60.31% 60.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2011 24.10% 84.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1292 15.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8358 # Type of FU issued -system.cpu.iq.rate 0.257589 # Inst issue rate +system.cpu.iq.FU_type_0::total 8345 # Type of FU issued +system.cpu.iq.rate 0.241073 # Inst issue rate system.cpu.iq.fu_busy_cnt 169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.020252 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30336 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7551 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8471 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 694 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 348 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 819 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2310 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1632 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 251 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 363 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8047 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1910 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 11 # number of nop insts executed -system.cpu.iew.exec_refs 3148 # number of memory reference insts executed -system.cpu.iew.exec_branches 1457 # Number of branches executed -system.cpu.iew.exec_stores 1240 # Number of stores executed -system.cpu.iew.exec_rate 0.248498 # Inst execution rate -system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7601 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3572 # num instructions producing a value -system.cpu.iew.wb_consumers 6998 # num instructions consuming a value +system.cpu.iew.exec_refs 3142 # number of memory reference insts executed +system.cpu.iew.exec_branches 1452 # Number of branches executed +system.cpu.iew.exec_stores 1232 # Number of stores executed +system.cpu.iew.exec_rate 0.232465 # Inst execution rate +system.cpu.iew.wb_sent 7714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7583 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3567 # num instructions producing a value +system.cpu.iew.wb_consumers 6985 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219061 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510666 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5019 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12644 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.425261 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266647 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10588 83.74% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 887 7.02% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 425 3.36% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 213 1.68% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 117 0.93% 96.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 214 1.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.40% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 113 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12644 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -771,122 +772,122 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22692 # The number of ROB reads -system.cpu.rob.rob_writes 21720 # The number of ROB writes -system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22770 # The number of ROB reads +system.cpu.rob.rob_writes 21679 # The number of ROB writes +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7945 # number of integer regfile reads -system.cpu.int_regfile_writes 4420 # number of integer regfile writes -system.cpu.fp_regfile_reads 31 # number of floating regfile reads -system.cpu.cc_regfile_reads 28734 # number of cc regfile reads -system.cpu.cc_regfile_writes 3302 # number of cc regfile writes -system.cpu.misc_regfile_reads 3189 # number of misc regfile reads +system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads +system.cpu.ipc 0.132627 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.132627 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7923 # number of integer regfile reads +system.cpu.int_regfile_writes 4408 # number of integer regfile writes +system.cpu.fp_regfile_reads 32 # number of floating regfile reads +system.cpu.cc_regfile_reads 28677 # number of cc regfile reads +system.cpu.cc_regfile_writes 3298 # number of cc regfile writes +system.cpu.misc_regfile_reads 3185 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.291293 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.917808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.291293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021311 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021311 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 5532 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5532 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1558 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1558 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits +system.cpu.dcache.overall_hits::total 2156 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 198 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 198 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses +system.cpu.dcache.overall_misses::total 513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12309993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12309993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22746000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22746000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35055993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35055993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35055993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35055993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2669 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2669 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2669 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2669 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.192207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62171.681818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62171.681818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72209.523810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72209.523810 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68335.269006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68335.269006 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 93 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,169 +896,169 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10297005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10297005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10297005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10297005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059795 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055077 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055077 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.998434 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1659 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.642857 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.998434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073241 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073241 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4430 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits -system.cpu.icache.overall_hits::total 1666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses -system.cpu.icache.overall_misses::total 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4420 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4420 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1659 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1659 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1659 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1659 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1659 # number of overall hits +system.cpu.icache.overall_hits::total 1659 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 404 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 404 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 404 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 404 # number of overall misses +system.cpu.icache.overall_misses::total 404 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28289500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28289500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28289500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28289500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28289500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28289500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2063 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2063 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2063 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2063 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195831 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195831 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195831 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195831 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195831 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195831 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70023.514851 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70023.514851 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70023.514851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70023.514851 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 361 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 110 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 110 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 110 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 110 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21612000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21612000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21612000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21612000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21612000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21612000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142511 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.142511 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.142511 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73510.204082 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73510.204082 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.994376 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.852442 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.141935 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001408 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005707 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 84 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses system.cpu.l2cache.overall_misses::total 402 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21127500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6646750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27774250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3346500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3346500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21127500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9993250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31120750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21127500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9993250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31120750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) @@ -1069,28 +1070,28 @@ system.cpu.l2cache.demand_accesses::total 441 # n system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.800000 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76548.913043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79127.976190 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77150.694444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77414.800995 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77414.800995 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1105,50 +1106,50 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 79 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17683000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17683000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25835000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17683000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25835000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64068.840580 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67443.037975 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64819.718310 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67238.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67238.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution @@ -1162,7 +1163,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram @@ -1170,21 +1171,17 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 238495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.trans_dist::ReadReq 355 # Transaction distribution system.membus.trans_dist::ReadResp 355 # Transaction distribution @@ -1205,9 +1202,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 499500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 9157ec7b3..9add0d45b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16487000 # Number of ticks simulated -final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17911000 # Number of ticks simulated +final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33036 # Simulator instruction rate (inst/s) -host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118603969 # Simulator tick rate (ticks/s) -host_mem_usage 248576 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 61363 # Simulator instruction rate (inst/s) +host_op_rate 71855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 239307903 # Simulator tick rate (ticks/s) +host_mem_usage 305224 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 26048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408 # Number of read requests accepted +system.physmem.num_reads::total 406 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 968343476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 385908101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 96477025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1450728603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 968343476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 968343476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 968343476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 385908101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 96477025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1450728603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26048 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26048 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,7 +48,7 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 88 # Per bank write bursts system.physmem.perBankRdBursts::1 45 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts -system.physmem.perBankRdBursts::3 45 # Per bank write bursts +system.physmem.perBankRdBursts::3 44 # Per bank write bursts system.physmem.perBankRdBursts::4 18 # Per bank write bursts system.physmem.perBankRdBursts::5 32 # Per bank write bursts system.physmem.perBankRdBursts::6 37 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16473500 # Total gap between requests +system.physmem.totGap 17897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408 # Read request sizes (log2) +system.physmem.readPktSize::6 407 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,13 +94,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3192729 # Total ticks spent queuing -system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 57 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 433.403509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 294.791776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.955773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6 10.53% 10.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 33.33% 43.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 15.79% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 5.26% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.51% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.51% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 7.02% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 5.26% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57 # Bytes accessed per row activation +system.physmem.totQLat 3190492 # Total ticks spent queuing +system.physmem.totMemAccLat 10821742 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7839.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26589.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1454.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1454.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.37 # Data bus utilization in percentage -system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.36 # Data bus utilization in percentage +system.physmem.busUtilRead 11.36 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 342 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40376.23 # Average gap between requests -system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43974.20 # Average gap between requests +system.physmem.pageHitRate 84.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 279720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 152625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2035800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) -system.physmem_0.averagePower 918.403600 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem_0.totalEnergy 14310600 # Total energy per rank (pJ) +system.physmem_0.averagePower 903.874941 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) -system.physmem_1.averagePower 817.101847 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states +system.physmem_1.actBackEnergy 10067625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 668250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12747240 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.131217 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1195750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14254250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2361 # Number of BP lookups -system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 1410 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 473 # Number of BTB hits +system.cpu.branchPred.BTBHits 476 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 54.649828 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 288 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32975 # number of cpu cycles simulated +system.cpu.numCycles 35823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6115 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11289 # Number of instructions fetch has processed system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.predictedBranches 764 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8098 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched +system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3842 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.850771 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.201734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9287 59.94% 59.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2459 15.87% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 519 3.35% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3228 20.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5035 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst +system.cpu.fetch.rateDist::total 15493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065907 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.315133 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5846 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4125 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5024 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 366 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 330 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9854 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1610 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 366 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1543 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 4080 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.UnblockCycles 608 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8873 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 401 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups +system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9263 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40182 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9732 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 3769 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 309 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8340 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7136 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7753 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.460595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.852056 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11312 73.01% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1923 12.41% 85.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1608 10.38% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 603 3.89% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15493 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 427 29.53% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.43% 61.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 550 38.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4484 62.84% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1571 22.02% 84.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1073 15.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7157 # Type of FU issued -system.cpu.iq.rate 0.217043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7136 # Type of FU issued +system.cpu.iq.rate 0.199202 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1446 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.202635 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31353 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11164 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8554 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 9 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 756 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 315 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 366 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 898 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1253 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 291 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1394 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 400 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2417 # number of memory reference insts executed -system.cpu.iew.exec_branches 1277 # Number of branches executed -system.cpu.iew.exec_stores 1017 # Number of stores executed -system.cpu.iew.exec_rate 0.205034 # Inst execution rate -system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6587 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2990 # num instructions producing a value -system.cpu.iew.wb_consumers 5391 # num instructions consuming a value +system.cpu.iew.exec_refs 2409 # number of memory reference insts executed +system.cpu.iew.exec_branches 1271 # Number of branches executed +system.cpu.iew.exec_stores 1015 # Number of stores executed +system.cpu.iew.exec_rate 0.188036 # Inst execution rate +system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2981 # num instructions producing a value +system.cpu.iew.wb_consumers 5387 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183290 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553369 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2567 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.359593 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.005851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12307 82.30% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1380 9.23% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 605 4.05% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 296 1.98% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 166 1.11% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.52% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.31% 99.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 31 0.21% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14953 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,122 +654,122 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22003 # The number of ROB reads -system.cpu.rob.rob_writes 16441 # The number of ROB writes -system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22696 # The number of ROB reads +system.cpu.rob.rob_writes 16433 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6737 # number of integer regfile reads -system.cpu.int_regfile_writes 3765 # number of integer regfile writes +system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128158 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128158 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6713 # number of integer regfile reads +system.cpu.int_regfile_writes 3756 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24010 # number of cc regfile reads -system.cpu.cc_regfile_writes 2910 # number of cc regfile writes -system.cpu.misc_regfile_reads 2599 # number of misc regfile reads +system.cpu.cc_regfile_reads 23929 # number of cc regfile reads +system.cpu.cc_regfile_writes 2892 # number of cc regfile writes +system.cpu.misc_regfile_reads 2595 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.129086 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1902 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.394366 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.129086 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164315 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164315 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4674 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1160 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1160 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits -system.cpu.dcache.overall_hits::total 1876 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits +system.cpu.dcache.overall_hits::total 1882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses -system.cpu.dcache.overall_misses::total 369 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 362 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 362 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 362 # number of overall misses +system.cpu.dcache.overall_misses::total 362 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9785742 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9785742 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17062992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17062992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17062992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17062992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1331 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.128475 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.128475 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.161319 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.161319 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.161319 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.161319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57226.561404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57226.561404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47135.337017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47135.337017 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -778,120 +778,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5294755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5294755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7484255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7484255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7484255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7484255 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076577 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8376505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8376505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8376505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8376505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076634 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063697 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063697 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53402.439024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53402.439024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063725 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063725 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 138.060100 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3485 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.773649 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.043653 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3477 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.786441 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 138.060100 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269649 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.269649 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 254 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.496094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7990 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7990 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3485 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3485 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3485 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3485 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3485 # number of overall hits -system.cpu.icache.overall_hits::total 3485 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses -system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19725741 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19725741 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19725741 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19725741 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19725741 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19725741 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094099 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094099 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094099 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54490.997238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54490.997238 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7642 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 18 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 94 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 136.043653 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.265710 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.265710 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 7977 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7977 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3477 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3477 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3477 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3477 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3477 # number of overall hits +system.cpu.icache.overall_hits::total 3477 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22425741 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22425741 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22425741 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22425741 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22425741 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22425741 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3841 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3841 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3841 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3841 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094767 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094767 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094767 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094767 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094767 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094767 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61609.178571 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61609.178571 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61609.178571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61609.178571 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8359 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 92 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 81.297872 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.858696 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16894743 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16894743 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16894743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16894743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16894743 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16894743 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077203 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077203 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077203 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56884.656566 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56884.656566 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18519493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18519493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18519493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18519493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18519493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18519493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077063 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077063 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077063 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62565.854730 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62565.854730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -900,28 +900,28 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.136661 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.519523 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.115068 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.115385 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.591914 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.333856 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.210892 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008581 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002767 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.367812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 44.986812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.164899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008445 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002746 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000559 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011750 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021301 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7446 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7446 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7429 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7429 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits @@ -933,61 +933,61 @@ system.cpu.l2cache.demand_hits::total 53 # nu system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits system.cpu.l2cache.overall_hits::total 53 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 387 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses +system.cpu.l2cache.demand_misses::total 386 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses -system.cpu.l2cache.overall_misses::total 387 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16599750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5077250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21677000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2079500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16599750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7156750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23756500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16599750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7156750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23756500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 386 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18219750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5781750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24001500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2253750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18219750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8035500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26255250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18219750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8035500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26255250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922559 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922297 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.894737 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.894472 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922559 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.879545 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922559 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.879545 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60583.029197 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61171.686747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 60719.887955 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69316.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69316.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61386.304910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61386.304910 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66739.010989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69659.638554 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67419.943820 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68018.782383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68018.782383 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1005,118 +1005,116 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14211250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4185750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18397000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1810701 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14211250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6019250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15861750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4830750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20692500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1641917 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2002750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2002750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15861750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6833500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22695250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15861750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6833500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24337167 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58315.257353 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61932.692308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59121.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59724.342105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56862.539720 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 591 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 67 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 64 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 378 # Transaction distribution -system.membus.trans_dist::ReadResp 376 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 496749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 377 # Transaction distribution +system.membus.trans_dist::ReadResp 375 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 408 # Request fanout histogram +system.membus.snoop_fanout::samples 407 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 408 # Request fanout histogram -system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 23.0 # Layer utilization (%) +system.membus.snoop_fanout::total 407 # Request fanout histogram +system.membus.reqLayer0.occupancy 509443 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2140258 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 72322cbec..cdd01be72 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 396323 # Simulator instruction rate (inst/s) -host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232084410 # Simulator tick rate (ticks/s) -host_mem_usage 298640 # Number of bytes of host memory used +host_inst_rate 771856 # Simulator instruction rate (inst/s) +host_op_rate 901727 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 450886881 # Simulator tick rate (ticks/s) +host_mem_usage 297796 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -347,18 +347,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index b8c713e42..bd1ca933f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 370272 # Simulator instruction rate (inst/s) -host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216878622 # Simulator tick rate (ticks/s) -host_mem_usage 297624 # Number of bytes of host memory used +host_inst_rate 801222 # Simulator instruction rate (inst/s) +host_op_rate 936270 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 468120222 # Simulator tick rate (ticks/s) +host_mem_usage 297024 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -228,18 +228,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 872a056d2..8573f117d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25815000 # Number of ticks simulated -final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25815500 # Number of ticks simulated +final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376930 # Simulator instruction rate (inst/s) -host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2127142386 # Simulator tick rate (ticks/s) -host_mem_usage 307352 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 263675 # Simulator instruction rate (inst/s) +host_op_rate 307555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1488783160 # Simulator tick rate (ticks/s) +host_mem_usage 306760 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51630 # number of cpu cycles simulated +system.cpu.numCycles 51631 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy @@ -440,17 +440,17 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,17 +503,17 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses @@ -525,17 +525,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -549,19 +549,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) @@ -588,9 +586,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ca0260a61..f65d4ed09 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21163500 # Number of ticks simulated -final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 22762000 # Number of ticks simulated +final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81533 # Simulator instruction rate (inst/s) -host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 345921870 # Simulator tick rate (ticks/s) -host_mem_usage 292088 # Number of bytes of host memory used +host_inst_rate 85129 # Simulator instruction rate (inst/s) +host_op_rate 85110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 388456550 # Simulator tick rate (ticks/s) +host_mem_usage 291584 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21120 # Nu system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 471 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 997944574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 426394500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1424339074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 997944574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 997944574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 997944574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 426394500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1424339074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 927862227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 396450224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1324312451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 927862227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 927862227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 927862227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 396450224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1324312451 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 471 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21083000 # Total gap between requests +system.physmem.totGap 22674500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.095238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.705030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.763121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 34 32.38% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17 16.19% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 9.52% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 0.95% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.90% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.90% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation -system.physmem.totQLat 5392000 # Total ticks spent queuing -system.physmem.totMemAccLat 14223250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.184943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.583818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 26.92% 26.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 35 33.65% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 18 17.31% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.62% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 2.88% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation +system.physmem.totQLat 5218000 # Total ticks spent queuing +system.physmem.totMemAccLat 14049250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11447.98 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11078.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30197.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1424.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29828.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1324.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1424.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1324.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.13 # Data bus utilization in percentage -system.physmem.busUtilRead 11.13 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.35 # Data bus utilization in percentage +system.physmem.busUtilRead 10.35 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44762.21 # Average gap between requests +system.physmem.avgGap 48141.19 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 491400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) -system.physmem_0.averagePower 790.660351 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states +system.physmem_0.actBackEnergy 9465705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1196250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12369120 # Total energy per rank (pJ) +system.physmem_0.averagePower 781.248697 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1950500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13375750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) -system.physmem_1.averagePower 944.255803 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states +system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14812845 # Total energy per rank (pJ) +system.physmem_1.averagePower 935.597347 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 284750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15222250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2146 # Number of BP lookups -system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1636 # Number of BTB lookups -system.cpu.branchPred.BTBHits 528 # Number of BTB hits +system.cpu.branchPred.lookups 2110 # Number of BP lookups +system.cpu.branchPred.condPredicted 1371 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 423 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1629 # Number of BTB lookups +system.cpu.branchPred.BTBHits 525 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.228361 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -279,236 +279,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 42328 # number of cpu cycles simulated +system.cpu.numCycles 45525 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13064 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2146 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 812 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4771 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing -system.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2037 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.207470 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8934 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12895 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2110 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.890662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.186824 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11035 76.76% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1473 10.25% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 0.88% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 160 1.11% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 1.97% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 90 0.63% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 137 0.95% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 121 0.84% 93.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 951 6.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11164 77.11% 77.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1470 10.15% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 124 0.86% 88.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 160 1.11% 89.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 1.95% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 94 0.65% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 128 0.88% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 113 0.78% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 942 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050699 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.308637 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8549 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2515 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2791 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.046348 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.283251 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8487 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2706 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2773 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 391 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12032 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11880 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8711 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 391 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8645 # Number of cycles rename is idle system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 944 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2743 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1081 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11544 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 1002 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2724 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1214 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11398 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 196 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6963 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13345 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 231 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 967 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13412 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13162 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3681 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3597 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 298 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 290 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2474 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1168 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8940 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8280 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3419 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.575960 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.325471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.566653 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.310295 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11054 76.89% 76.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1314 9.14% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 739 5.14% 91.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 413 2.87% 94.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 345 2.40% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 315 2.19% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 104 0.72% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 66 0.46% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11167 77.13% 77.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.08% 86.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 734 5.07% 91.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 423 2.92% 94.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 344 2.38% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 310 2.14% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 102 0.70% 99.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 57 0.39% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 27 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14478 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.06% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 131 66.50% 70.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58 29.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.59% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 129 65.82% 70.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4865 58.76% 58.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2336 28.21% 87.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1072 12.95% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4822 58.78% 58.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2303 28.07% 86.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1072 13.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8280 # Type of FU issued -system.cpu.iq.rate 0.195615 # Inst issue rate -system.cpu.iq.fu_busy_cnt 197 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023792 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31160 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12466 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7466 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8204 # Type of FU issued +system.cpu.iq.rate 0.180209 # Inst issue rate +system.cpu.iq.fu_busy_cnt 196 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12267 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8398 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1342 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 267 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 475 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10593 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 391 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 464 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10483 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2474 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1168 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7957 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2194 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 323 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 348 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 444 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7875 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1553 # number of nop insts executed -system.cpu.iew.exec_refs 3252 # number of memory reference insts executed -system.cpu.iew.exec_branches 1379 # Number of branches executed -system.cpu.iew.exec_stores 1058 # Number of stores executed -system.cpu.iew.exec_rate 0.187984 # Inst execution rate -system.cpu.iew.wb_sent 7571 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7468 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2915 # num instructions producing a value -system.cpu.iew.wb_consumers 4399 # num instructions consuming a value +system.cpu.iew.exec_nop 1532 # number of nop insts executed +system.cpu.iew.exec_refs 3217 # number of memory reference insts executed +system.cpu.iew.exec_branches 1365 # Number of branches executed +system.cpu.iew.exec_stores 1057 # Number of stores executed +system.cpu.iew.exec_rate 0.172982 # Inst execution rate +system.cpu.iew.wb_sent 7509 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7410 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2869 # num instructions producing a value +system.cpu.iew.wb_consumers 4254 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.176432 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.662651 # average fanout of values written-back +system.cpu.iew.wb_rate 0.162768 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674424 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4969 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4860 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 386 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.416333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.231872 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.412758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.228786 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11333 83.91% 83.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 875 6.48% 90.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 515 3.81% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 250 1.85% 96.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.10% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 177 1.31% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.47% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11456 84.09% 84.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 871 6.39% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 510 3.74% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 252 1.85% 96.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.09% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 178 1.31% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.48% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103 0.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13623 # Number of insts commited each cycle system.cpu.commit.committedInsts 5623 # Number of instructions committed system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,102 +554,102 @@ system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5623 # Class of committed instruction -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23983 # The number of ROB reads -system.cpu.rob.rob_writes 22065 # The number of ROB writes -system.cpu.timesIdled 275 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27952 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23990 # The number of ROB reads +system.cpu.rob.rob_writes 21831 # The number of ROB writes +system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.489370 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.489370 # CPI: Total CPI of All Threads -system.cpu.ipc 0.117794 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.117794 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10767 # number of integer regfile reads -system.cpu.int_regfile_writes 5247 # number of integer regfile writes +system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads +system.cpu.ipc 0.109522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.109522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10639 # number of integer regfile reads +system.cpu.int_regfile_writes 5201 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 164 # number of misc regfile reads +system.cpu.misc_regfile_reads 165 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.212769 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2418 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.148936 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.212769 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022269 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 5997 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5997 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1862 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1862 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits +system.cpu.dcache.overall_hits::total 2418 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses +system.cpu.dcache.overall_misses::total 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12038750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12038750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24387249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24387249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36425999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36425999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36425999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36425999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2027 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2027 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.174180 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174180 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174180 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174180 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71423.527451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71423.527451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -658,82 +658,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7833500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7833500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4084749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4084749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11918249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11918249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11918249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11918249 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044894 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044894 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.205778 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.783784 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.735736 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.344728 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.205778 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077249 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077249 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4407 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4407 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1593 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1593 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1593 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1593 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1593 # number of overall hits -system.cpu.icache.overall_hits::total 1593 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 444 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 444 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 444 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 444 # number of overall misses -system.cpu.icache.overall_misses::total 444 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30764750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30764750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30764750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30764750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30764750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30764750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2037 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2037 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2037 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2037 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2037 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2037 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217968 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217968 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217968 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217968 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217968 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217968 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69289.977477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69289.977477 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4385 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4385 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits +system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 449 # number of overall misses +system.cpu.icache.overall_misses::total 449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34003000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34003000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34003000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34003000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34003000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34003000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221619 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.221619 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.221619 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.221619 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.221619 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.221619 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75730.512249 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75730.512249 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75730.512249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75730.512249 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,51 +742,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 111 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 111 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 111 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 111 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24043500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24043500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24043500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24043500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24043500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24043500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163476 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.163476 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.163476 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72202.702703 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72202.702703 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26389500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26389500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164363 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.164363 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.164363 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.292920 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 218.150435 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.335208 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.957712 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004893 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.168468 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.981967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004888 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006662 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006657 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses @@ -807,17 +807,17 @@ system.cpu.l2cache.demand_misses::total 471 # nu system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 471 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30897000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3981500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3981500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11198000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11198000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34878500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26025000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7738500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 33763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4034000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4034000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26025000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11772500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37797500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26025000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11772500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37797500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) @@ -840,17 +840,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993671 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71759.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79302.197802 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73389.548694 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79630 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74052.016985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74052.016985 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80680 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80680 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,17 +870,17 @@ system.cpu.l2cache.demand_mshr_misses::total 471 system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19517000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6096000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25613000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3359000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3359000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19517000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9455000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28972000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19517000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9455000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28972000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21894000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6598000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28492000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3411000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3411000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21894000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10009000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21894000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10009000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31903000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses @@ -892,17 +892,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59142.424242 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66989.010989 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60838.479810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67180 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67180 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68220 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68220 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution @@ -927,11 +927,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 569000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 233500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 421 # Transaction distribution system.membus.trans_dist::ReadResp 421 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution @@ -951,9 +951,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 598000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2506000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 84d2a731d..4f23a8939 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30902000 # Number of ticks simulated -final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30902500 # Number of ticks simulated +final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104539 # Simulator instruction rate (inst/s) -host_op_rate 104503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 574021463 # Simulator tick rate (ticks/s) -host_mem_usage 276192 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 544856 # Simulator instruction rate (inst/s) +host_op_rate 544118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2985748792 # Simulator tick rate (ticks/s) +host_mem_usage 288768 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 380 # Transaction distribution -system.membus.trans_dist::ReadResp 380 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 430 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430 # Request fanout histogram -system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.5 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -72,7 +49,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 61804 # number of cpu cycles simulated +system.cpu.numCycles 61805 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -91,7 +68,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61804 # Number of busy cycles +system.cpu.num_busy_cycles 61805 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -130,15 +107,119 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits +system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses +system.cpu.dcache.overall_misses::total 137 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -157,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses system.cpu.icache.overall_misses::total 295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16141000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16141000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16141000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16141000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16141000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses @@ -175,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54715.254237 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54715.254237 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -195,33 +276,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 295 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15551000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15551000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.724070 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.264551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.459518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy @@ -248,17 +329,17 @@ system.cpu.l2cache.demand_misses::total 430 # nu system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15236000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7124000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22360000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15236000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7124000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22360000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses) @@ -281,17 +362,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,17 +392,17 @@ system.cpu.l2cache.demand_mshr_misses::total 430 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses @@ -333,122 +414,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.158665 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.158665 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021035 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021035 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses -system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -477,5 +454,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 442500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 380 # Transaction distribution +system.membus.trans_dist::ReadResp 380 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 430 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 430 # Request fanout histogram +system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index e81ca8aaa..c9ca56107 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18857500 # Number of ticks simulated -final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20101000 # Number of ticks simulated +final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101158 # Simulator instruction rate (inst/s) -host_op_rate 101133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329193143 # Simulator tick rate (ticks/s) -host_mem_usage 288984 # Number of bytes of host memory used +host_inst_rate 103196 # Simulator instruction rate (inst/s) +host_op_rate 103171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 357968408 # Simulator tick rate (ticks/s) +host_mem_usage 289136 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1092084971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 321576041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1413661012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1092084971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1092084971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1092084971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 321576041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1413661012 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18724000 # Total gap between requests +system.physmem.totGap 19960500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 3635500 # Total ticks spent queuing -system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.606609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.258819 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.28% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 5.13% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 3861750 # Total ticks spent queuing +system.physmem.totMemAccLat 12186750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8697.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27447.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1413.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1413.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.77 # Data bus utilization in percentage -system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.04 # Data bus utilization in percentage +system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 356 # Number of row buffer hits during reads +system.physmem.readRowHits 357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42171.17 # Average gap between requests -system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 476280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 259875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2644200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 44956.08 # Average gap between requests +system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15222495 # Total energy per rank (pJ) -system.physmem_0.averagePower 961.471341 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15068130 # Total energy per rank (pJ) +system.physmem_0.averagePower 951.571203 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15316250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8055810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2433000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11899695 # Total energy per rank (pJ) -system.physmem_1.averagePower 751.599242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4725250 # Time in different power states +system.physmem_1.actBackEnergy 7470990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2946000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11827875 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.063003 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6720750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 11341250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10486250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2332 # Number of BP lookups -system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2330 # Number of BP lookups +system.cpu.branchPred.condPredicted 1881 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups -system.cpu.branchPred.BTBHits 661 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1929 # Number of BTB lookups +system.cpu.branchPred.BTBHits 660 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.214619 # BTB Hit Percentage system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -279,237 +279,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 37716 # number of cpu cycles simulated +system.cpu.numCycles 40203 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 865 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 7819 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13492 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2330 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.061192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.469867 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10352 81.42% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.49% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 216 1.70% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 152 1.20% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 247 1.94% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 139 1.09% 88.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.99% 90.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 114 0.90% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1052 8.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 12714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.057956 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.335597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7212 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3139 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1951 # Number of cycles decode is running system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst +system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7370 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 627 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11201 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1508 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9631 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18130 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18104 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4633 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 361 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4184 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.716140 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.547958 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9591 75.44% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 944 7.42% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 633 4.98% 87.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 463 3.64% 91.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 426 3.35% 94.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 301 2.37% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 1.89% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 71 0.56% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12714 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 4.37% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 122 48.41% 52.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 119 47.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5535 60.79% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1910 20.98% 81.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1658 18.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.rate 0.241489 # Inst issue rate -system.cpu.iq.fu_busy_cnt 251 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9105 # Type of FU issued +system.cpu.iq.rate 0.226476 # Inst issue rate +system.cpu.iq.fu_busy_cnt 252 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14543 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 870 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 62 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8701 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3329 # number of memory reference insts executed -system.cpu.iew.exec_branches 1361 # Number of branches executed +system.cpu.iew.exec_refs 3330 # number of memory reference insts executed +system.cpu.iew.exec_branches 1363 # Number of branches executed system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.230724 # Inst execution rate -system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8300 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4483 # num instructions producing a value -system.cpu.iew.wb_consumers 7102 # num instructions consuming a value +system.cpu.iew.exec_rate 0.216427 # Inst execution rate +system.cpu.iew.wb_sent 8428 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4465 # num instructions producing a value +system.cpu.iew.wb_consumers 7078 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back +system.cpu.iew.wb_rate 0.206403 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.630828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11592 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.499655 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.370216 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12003 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.482546 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.346027 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9439 81.43% 81.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 839 7.24% 88.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 524 4.52% 93.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9841 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 848 7.06% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 522 4.35% 93.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 225 1.87% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.40% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 120 1.00% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.92% 98.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 59 0.49% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 110 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11592 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12003 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,61 +555,61 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21860 # The number of ROB reads -system.cpu.rob.rob_writes 21470 # The number of ROB writes -system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22278 # The number of ROB reads +system.cpu.rob.rob_writes 21482 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads -system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13744 # number of integer regfile reads -system.cpu.int_regfile_writes 7176 # number of integer regfile writes +system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13740 # number of integer regfile reads +system.cpu.int_regfile_writes 7173 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.843132 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.313725 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.843132 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015587 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits -system.cpu.dcache.overall_hits::total 2261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses -system.cpu.dcache.overall_misses::total 452 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 1556 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1556 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 720 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 720 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits +system.cpu.dcache.overall_hits::total 2276 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 326 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 326 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8814500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8814500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30924496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30924496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39738996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39738996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39738996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39738996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -618,38 +618,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2713 # system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066587 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.066587 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.311663 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.311663 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.161076 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.161076 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.161076 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.161076 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 90935.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 90935.917620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.833333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 335 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 335 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -658,14 +658,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4529750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4529750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4417498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4417498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8947248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8947248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8947248 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -674,119 +674,119 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 169.362964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.362964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082697 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082697 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4007 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits -system.cpu.icache.overall_hits::total 1391 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses -system.cpu.icache.overall_misses::total 438 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4005 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits +system.cpu.icache.overall_hits::total 1389 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 439 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 439 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 439 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses +system.cpu.icache.overall_misses::total 439 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31975250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31975250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31975250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31975250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31975250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31975250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1828 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1828 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1828 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.240153 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.240153 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72836.560364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72836.560364 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 97.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 89 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 89 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 89 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 89 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26127750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26127750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26127750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26127750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26127750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26127750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.954316 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000972 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.205981 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.748335 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006102 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses @@ -810,17 +810,17 @@ system.cpu.l2cache.demand_misses::total 445 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 445 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23649250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4137750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27787000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3745250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3745250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23649250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31532250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23649250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31532250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25715250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4463750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30179000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4367500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4367500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25715250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8831250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34546500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25715250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8831250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34546500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) @@ -843,17 +843,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984513 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -873,17 +873,17 @@ system.cpu.l2cache.demand_mshr_misses::total 445 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21441250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25233500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3785500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3785500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21441250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7577750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29019000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21441250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7577750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29019000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses @@ -895,17 +895,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution @@ -930,11 +930,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 589250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 165750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -954,9 +954,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 555000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2341000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 52edf7aee..f6a7e842c 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27800000 # Number of ticks simulated -final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27800500 # Number of ticks simulated +final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 583909 # Simulator instruction rate (inst/s) -host_op_rate 583078 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3038583452 # Simulator tick rate (ticks/s) -host_mem_usage 285748 # Number of bytes of host memory used +host_inst_rate 510787 # Simulator instruction rate (inst/s) +host_op_rate 510102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2658808340 # Simulator tick rate (ticks/s) +host_mem_usage 289420 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,40 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 308 # Transaction distribution -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 389 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 389 # Request fanout histogram -system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.6 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55600 # number of cpu cycles simulated +system.cpu.numCycles 55601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles +system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -112,15 +89,119 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits +system.cpu.dcache.overall_hits::total 1253 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses +system.cpu.dcache.overall_misses::total 135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -139,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -157,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,33 +258,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy @@ -233,17 +314,17 @@ system.cpu.l2cache.demand_misses::total 389 # nu system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) @@ -266,17 +347,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -296,17 +377,17 @@ system.cpu.l2cache.demand_mshr_misses::total 389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses @@ -318,122 +399,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -462,5 +439,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 385500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 308 # Transaction distribution +system.membus.trans_dist::ReadResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 389 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 389 # Request fanout histogram +system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 3b4d7b677..8ea066b3b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19678000 # Number of ticks simulated -final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 21143500 # Number of ticks simulated +final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46918 # Simulator instruction rate (inst/s) -host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171550123 # Simulator tick rate (ticks/s) -host_mem_usage 309548 # Number of bytes of host memory used +host_inst_rate 49814 # Simulator instruction rate (inst/s) +host_op_rate 90238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195722405 # Simulator tick rate (ticks/s) +host_mem_usage 309420 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 832407123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 426797834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1259204957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 832407123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 832407123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 832407123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 426797834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1259204957 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19629500 # Total gap between requests +system.physmem.totGap 21095000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,308 +186,310 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 4347000 # Total ticks spent queuing -system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.440000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.807528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.488436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35 35.00% 35.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 31 31.00% 66.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 6.00% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.00% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.00% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.00% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100 # Bytes accessed per row activation +system.physmem.totQLat 5105750 # Total ticks spent queuing +system.physmem.totMemAccLat 12924500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12244.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30994.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1262.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1262.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.60 # Data bus utilization in percentage -system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.86 # Data bus utilization in percentage +system.physmem.busUtilRead 9.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 309 # Number of row buffer hits during reads +system.physmem.readRowHits 307 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47073.14 # Average gap between requests -system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 50587.53 # Average gap between requests +system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 936000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) -system.physmem_0.averagePower 837.810088 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13058475 # Total energy per rank (pJ) +system.physmem_0.averagePower 824.789199 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 438480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 239250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1513200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) -system.physmem_1.averagePower 889.816201 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states +system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14021205 # Total energy per rank (pJ) +system.physmem_1.averagePower 885.596400 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 102500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15223750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 3423 # Number of BP lookups -system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 864 # Number of BTB hits +system.cpu.branchPred.lookups 3414 # Number of BP lookups +system.cpu.branchPred.condPredicted 3414 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2533 # Number of BTB lookups +system.cpu.branchPred.BTBHits 863 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.070272 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39357 # number of cpu cycles simulated +system.cpu.numCycles 42288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1203 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 12291 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15496 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3414 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1201 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1161 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 2168 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.270406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.764504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2164 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 23838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.164108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669642 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17618 80.47% 80.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 236 1.08% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 0.79% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 259 1.18% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 208 0.95% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19573 82.11% 82.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 236 0.99% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 173 0.73% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.08% 84.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 208 0.87% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 228 0.96% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 337 1.41% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 205 0.86% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2621 11.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2194 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 719 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3480 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3970 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24219 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 23838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080732 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.366440 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12043 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7408 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3332 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 600 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25703 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 600 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 12311 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2293 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 795 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3474 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4365 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24179 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 3820 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27591 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 59364 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 33558 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 4214 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 27545 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 59275 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 33508 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16528 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16482 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1503 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2441 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1612 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21419 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17897 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11052 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16525 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11007 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21893 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.817476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.773238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 23838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750147 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.712551 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16772 76.61% 76.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1137 5.19% 81.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 886 4.05% 85.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 636 2.91% 88.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 833 3.80% 92.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 590 2.69% 95.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 599 2.74% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 316 1.44% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124 0.57% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18713 78.50% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1142 4.79% 83.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 888 3.73% 87.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 640 2.68% 89.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 832 3.49% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 584 2.45% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 601 2.52% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 314 1.32% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124 0.52% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 23838 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 173 77.58% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 31 13.90% 91.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 8.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14382 80.36% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14368 80.35% 80.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2121 11.86% 92.29% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17897 # Type of FU issued -system.cpu.iq.rate 0.454735 # Inst issue rate -system.cpu.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17882 # Type of FU issued +system.cpu.iq.rate 0.422862 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 59896 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32462 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18114 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18098 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 228 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1388 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1385 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 677 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 676 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 601 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1862 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21468 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 600 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1925 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 68 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21444 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2441 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1612 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 694 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16910 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1967 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 972 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3251 # number of memory reference insts executed -system.cpu.iew.exec_branches 1662 # Number of branches executed +system.cpu.iew.exec_refs 3249 # number of memory reference insts executed +system.cpu.iew.exec_branches 1660 # Number of branches executed system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.430063 # Inst execution rate -system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16374 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11006 # num instructions producing a value -system.cpu.iew.wb_consumers 17135 # num instructions consuming a value +system.cpu.iew.exec_rate 0.399877 # Inst execution rate +system.cpu.iew.wb_sent 16617 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16357 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10994 # num instructions producing a value +system.cpu.iew.wb_consumers 17115 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back +system.cpu.iew.wb_rate 0.386800 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642361 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11696 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 19924 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.394281 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 587 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 21874 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.445598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.336765 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16684 83.74% 83.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 365 1.83% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 142 0.71% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.57% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.37% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18628 85.16% 85.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1010 4.62% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 544 2.49% 92.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 738 3.37% 95.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 369 1.69% 97.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.64% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.52% 98.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.33% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 259 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 19924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 21874 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,102 +535,102 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 41131 # The number of ROB reads -system.cpu.rob.rob_writes 44929 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 43058 # The number of ROB reads +system.cpu.rob.rob_writes 44876 # The number of ROB writes +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18450 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21341 # number of integer regfile reads -system.cpu.int_regfile_writes 13120 # number of integer regfile writes +system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127223 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127223 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21328 # number of integer regfile reads +system.cpu.int_regfile_writes 13105 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8069 # number of cc regfile reads +system.cpu.cc_regfile_reads 8064 # number of cc regfile reads system.cpu.cc_regfile_writes 5036 # number of cc regfile writes -system.cpu.misc_regfile_reads 7491 # number of misc regfile reads +system.cpu.misc_regfile_reads 7485 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 82.313704 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.971631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.313704 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020096 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5351 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5351 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1536 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits +system.cpu.dcache.overall_hits::total 2393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 134 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 212 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 212 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 212 # number of overall misses +system.cpu.dcache.overall_misses::total 212 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11119000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11119000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6761250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6761250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17880250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17880250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17880250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17880250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1670 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2605 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2605 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2605 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2605 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080240 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080240 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081382 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081382 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081382 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081382 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82977.611940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 82977.611940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86682.692308 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 86682.692308 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84340.801887 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84340.801887 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 70 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 70 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 70 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses @@ -637,82 +639,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6612750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6612750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12308250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12308250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12308250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12308250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038323 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038323 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88992.187500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88992.187500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84778.846154 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84778.846154 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 131.513084 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1796 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.507246 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 131.513084 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064215 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064215 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4612 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits -system.cpu.icache.overall_hits::total 1800 # number of overall hits +system.cpu.icache.tags.tag_accesses 4604 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4604 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1796 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1796 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1796 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1796 # number of overall hits +system.cpu.icache.overall_hits::total 1796 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28645750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28645750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28645750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28645750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28645750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28645750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2164 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170055 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.170055 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.170055 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.170055 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.170055 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.170055 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77841.711957 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77841.711957 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77841.711957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77841.711957 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -733,39 +735,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 276 system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21933250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21933250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21933250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21933250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21933250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21933250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.127542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.127542 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79468.297101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79468.297101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.168393 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.574096 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.594298 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000964 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004980 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses @@ -786,17 +788,17 @@ system.cpu.l2cache.demand_misses::total 417 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21646250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27278750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6534750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6534750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21646250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12167250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33813500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21646250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12167250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33813500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) @@ -819,17 +821,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997608 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78713.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88007.812500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80468.289086 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83778.846154 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83778.846154 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81087.529976 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81087.529976 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -849,17 +851,17 @@ system.cpu.l2cache.demand_mshr_misses::total 417 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18201750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23038750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18201750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10392250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28594000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18201750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10392250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28594000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses @@ -871,17 +873,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66188.181818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75578.125000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67960.914454 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71221.153846 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71221.153846 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -908,11 +910,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 3 # system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 471250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 339 # Transaction distribution system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution @@ -934,9 +936,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2222500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b43d6cab2..2ef89d07d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28358000 # Number of ticks simulated -final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 28358500 # Number of ticks simulated +final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 307468 # Simulator instruction rate (inst/s) -host_op_rate 556583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618053178 # Simulator tick rate (ticks/s) -host_mem_usage 302528 # Number of bytes of host memory used +host_inst_rate 312703 # Simulator instruction rate (inst/s) +host_op_rate 566020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1645401799 # Simulator tick rate (ticks/s) +host_mem_usage 307640 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,43 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 282 # Transaction distribution -system.membus.trans_dist::ReadResp 282 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 361 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 361 # Request fanout histogram -system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56716 # number of cpu cycles simulated +system.cpu.numCycles 56717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -78,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -117,15 +92,119 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits +system.cpu.dcache.overall_hits::total 1854 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.dcache.overall_misses::total 134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.544338 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -144,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -162,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12156500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12156500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12156500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12156500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12156500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12156500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.474338 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -235,17 +314,17 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14805500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) @@ -268,17 +347,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,17 +377,17 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses @@ -320,122 +399,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits -system.cpu.dcache.overall_hits::total 1854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -466,5 +441,30 @@ system.cpu.toL2Bus.respLayer0.occupancy 342000 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 282 # Transaction distribution +system.membus.trans_dist::ReadResp 282 # Transaction distribution +system.membus.trans_dist::ReadExReq 79 # Transaction distribution +system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 361 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 361 # Request fanout histogram +system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 752a25834..3794759d9 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23754500 # Number of ticks simulated -final_tick 23754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 25499500 # Number of ticks simulated +final_tick 25499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70868 # Simulator instruction rate (inst/s) -host_op_rate 70863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132078042 # Simulator tick rate (ticks/s) -host_mem_usage 294344 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 83845 # Simulator instruction rate (inst/s) +host_op_rate 83838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167736694 # Simulator tick rate (ticks/s) +host_mem_usage 294000 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22336 # Number of bytes read from this memory -system.physmem.bytes_read::total 62400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40064 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 626 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 349 # Number of read requests responded to by this memory -system.physmem.num_reads::total 975 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1686585700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 940284999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2626870698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1686585700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1686585700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1686585700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 940284999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2626870698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 975 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22144 # Number of bytes read from this memory +system.physmem.bytes_read::total 62848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40704 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 346 # Number of read requests responded to by this memory +system.physmem.num_reads::total 982 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1596266593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 868409184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2464675778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1596266593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1596266593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1596266593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 868409184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2464675778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 982 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 982 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 83 # Per bank write bursts -system.physmem.perBankRdBursts::1 151 # Per bank write bursts -system.physmem.perBankRdBursts::2 78 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 152 # Per bank write bursts +system.physmem.perBankRdBursts::2 79 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts system.physmem.perBankRdBursts::4 88 # Per bank write bursts system.physmem.perBankRdBursts::5 49 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 49 # Per bank write bursts -system.physmem.perBankRdBursts::8 41 # Per bank write bursts -system.physmem.perBankRdBursts::9 38 # Per bank write bursts +system.physmem.perBankRdBursts::6 33 # Per bank write bursts +system.physmem.perBankRdBursts::7 50 # Per bank write bursts +system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::9 39 # Per bank write bursts system.physmem.perBankRdBursts::10 30 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 122 # Per bank write bursts -system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::13 120 # Per bank write bursts +system.physmem.perBankRdBursts::14 69 # Per bank write bursts system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23342000 # Total gap between requests +system.physmem.totGap 25359500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 975 # Read request sizes (log2) +system.physmem.readPktSize::6 982 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.431280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.087836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.004628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 56 26.54% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25 11.85% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 14 6.64% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15 7.11% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9 4.27% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 1.90% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 2.84% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13 6.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation -system.physmem.totQLat 12504500 # Total ticks spent queuing -system.physmem.totMemAccLat 30785750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12825.13 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.836364 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.810990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.156672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 81 36.82% 36.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62 28.18% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 22 10.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14 6.36% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 4.55% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 3.18% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.73% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.73% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 5.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 220 # Bytes accessed per row activation +system.physmem.totQLat 12877000 # Total ticks spent queuing +system.physmem.totMemAccLat 31289500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13113.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31575.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2626.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31863.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2464.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2626.87 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2464.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 20.52 # Data bus utilization in percentage -system.physmem.busUtilRead 20.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 19.26 # Data bus utilization in percentage +system.physmem.busUtilRead 19.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 763 # Number of row buffer hits during reads +system.physmem.readRowHits 752 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23940.51 # Average gap between requests -system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4578600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 25824.34 # Average gap between requests +system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 929880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 507375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4547400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16058610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 84750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 23638155 # Total energy per rank (pJ) -system.physmem_0.averagePower 1000.821593 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 44000 # Time in different power states +system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 23657895 # Total energy per rank (pJ) +system.physmem_0.averagePower 1001.657370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 688500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22808500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 695520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 379500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3018600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15908130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21744180 # Total energy per rank (pJ) -system.physmem_1.averagePower 920.632125 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 278750 # Time in different power states +system.physmem_1.actBackEnergy 15503715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 591000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21359100 # Total energy per rank (pJ) +system.physmem_1.averagePower 903.085461 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 888000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22573750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21996000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 7608 # Number of BP lookups -system.cpu.branchPred.condPredicted 4258 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5646 # Number of BTB lookups -system.cpu.branchPred.BTBHits 865 # Number of BTB hits +system.cpu.branchPred.lookups 7477 # Number of BP lookups +system.cpu.branchPred.condPredicted 4177 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1616 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5400 # Number of BTB lookups +system.cpu.branchPred.BTBHits 850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 15.320581 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1051 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 15.740741 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1012 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 5192 # DTB read hits -system.cpu.dtb.read_misses 102 # DTB read misses +system.cpu.dtb.read_hits 4911 # DTB read hits +system.cpu.dtb.read_misses 100 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 5294 # DTB read accesses -system.cpu.dtb.write_hits 2108 # DTB write hits -system.cpu.dtb.write_misses 66 # DTB write misses +system.cpu.dtb.read_accesses 5011 # DTB read accesses +system.cpu.dtb.write_hits 2106 # DTB write hits +system.cpu.dtb.write_misses 69 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2174 # DTB write accesses -system.cpu.dtb.data_hits 7300 # DTB hits -system.cpu.dtb.data_misses 168 # DTB misses +system.cpu.dtb.write_accesses 2175 # DTB write accesses +system.cpu.dtb.data_hits 7017 # DTB hits +system.cpu.dtb.data_misses 169 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 7468 # DTB accesses -system.cpu.itb.fetch_hits 5663 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 7186 # DTB accesses +system.cpu.itb.fetch_hits 5467 # ITB hits +system.cpu.itb.fetch_misses 60 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5720 # ITB accesses +system.cpu.itb.fetch_accesses 5527 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 47510 # number of cpu cycles simulated +system.cpu.numCycles 51000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1451 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 41889 # Number of instructions fetch has processed -system.cpu.fetch.Branches 7608 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1916 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 1416 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 41297 # Number of instructions fetch has processed +system.cpu.fetch.Branches 7477 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1862 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10878 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1697 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5663 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 846 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.466188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.843743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 471 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5467 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 803 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.490920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.868697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21551 75.43% 75.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 541 1.89% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 402 1.41% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 607 2.12% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 545 1.91% 82.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 439 1.54% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 542 1.90% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 448 1.57% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3495 12.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20832 75.21% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 522 1.88% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 376 1.36% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 569 2.05% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 524 1.89% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 456 1.65% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 499 1.80% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 422 1.52% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3499 12.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160135 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.881688 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37575 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12018 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 625 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1245 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 719 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33794 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 947 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1245 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38261 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5449 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1170 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5378 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5409 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 31549 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 73 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 407 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 458 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4425 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 23766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 39316 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 39298 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 27699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.146608 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.809745 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36892 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11130 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5276 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 643 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1210 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 704 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 509 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33151 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1210 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37566 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5376 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5257 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4377 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30969 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 361 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 477 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3380 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 23374 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 38597 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 38579 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14626 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 56 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2199 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3120 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1520 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 14234 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 57 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2267 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2994 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1466 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2933 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1394 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1410 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28021 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 23357 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14239 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8472 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28570 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.817536 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.542788 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 27629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 22900 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13893 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8231 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 27699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.826745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.538980 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19963 69.87% 69.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2657 9.30% 79.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1959 6.86% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1384 4.84% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1325 4.64% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 682 2.39% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 348 1.22% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 184 0.64% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 68 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19213 69.36% 69.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2603 9.40% 78.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1960 7.08% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1418 5.12% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1237 4.47% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 696 2.51% 97.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 372 1.34% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 137 0.49% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 63 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28570 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 22 6.04% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 263 72.25% 78.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79 21.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 27 8.23% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 211 64.33% 72.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 90 27.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7749 65.04% 65.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2973 24.95% 90.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1188 9.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7493 65.81% 65.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2715 23.85% 89.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1173 10.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11915 # Type of FU issued +system.cpu.iq.FU_type_0::total 11386 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7559 66.06% 66.08% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.09% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2735 23.90% 90.01% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1143 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7630 66.27% 66.28% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.29% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2714 23.57% 89.88% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1165 10.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11442 # Type of FU issued -system.cpu.iq.FU_type::total 23357 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.491623 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 183 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 181 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 364 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007835 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007749 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015584 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 42325 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11514 # Type of FU issued +system.cpu.iq.FU_type::total 22900 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.449020 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 168 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 328 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.006987 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007336 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.014323 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73887 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 41585 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20089 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 23695 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 23202 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1937 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 655 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1811 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 601 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 426 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 281 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 75 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1750 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 529 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1765 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 545 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 346 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1245 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2860 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 601 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 28216 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6053 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2914 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 571 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1210 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3002 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 780 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27815 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2876 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 747 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 148 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1270 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1418 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 21922 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2766 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2537 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 5303 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1435 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 21491 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2518 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2502 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 5020 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 71 # number of nop insts executed -system.cpu.iew.exec_nop::1 73 # number of nop insts executed -system.cpu.iew.exec_nop::total 144 # number of nop insts executed -system.cpu.iew.exec_refs::0 3883 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3616 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 7499 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1763 # Number of branches executed -system.cpu.iew.exec_branches::1 1733 # Number of branches executed -system.cpu.iew.exec_branches::total 3496 # Number of branches executed -system.cpu.iew.exec_stores::0 1117 # Number of stores executed -system.cpu.iew.exec_stores::1 1079 # Number of stores executed -system.cpu.iew.exec_stores::total 2196 # Number of stores executed -system.cpu.iew.exec_rate 0.461419 # Inst execution rate -system.cpu.iew.wb_sent::0 10477 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 10192 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 20669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 10260 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 10004 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 20264 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5390 # num instructions producing a value -system.cpu.iew.wb_producers::1 5243 # num instructions producing a value -system.cpu.iew.wb_producers::total 10633 # num instructions producing a value -system.cpu.iew.wb_consumers::0 7128 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6992 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 14120 # num instructions consuming a value +system.cpu.iew.exec_nop::0 69 # number of nop insts executed +system.cpu.iew.exec_nop::1 67 # number of nop insts executed +system.cpu.iew.exec_nop::total 136 # number of nop insts executed +system.cpu.iew.exec_refs::0 3616 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3607 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7223 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1734 # Number of branches executed +system.cpu.iew.exec_branches::1 1745 # Number of branches executed +system.cpu.iew.exec_branches::total 3479 # Number of branches executed +system.cpu.iew.exec_stores::0 1098 # Number of stores executed +system.cpu.iew.exec_stores::1 1105 # Number of stores executed +system.cpu.iew.exec_stores::total 2203 # Number of stores executed +system.cpu.iew.exec_rate 0.421392 # Inst execution rate +system.cpu.iew.wb_sent::0 10180 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 10330 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 20510 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9974 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 10135 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 20109 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5251 # num instructions producing a value +system.cpu.iew.wb_producers::1 5302 # num instructions producing a value +system.cpu.iew.wb_producers::total 10553 # num instructions producing a value +system.cpu.iew.wb_consumers::0 7044 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 7008 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 14052 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.215955 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.210566 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.426521 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.756173 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.749857 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.753045 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.195569 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.198725 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.394294 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.745457 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.756564 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.750996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 15441 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 15019 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1167 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28457 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.449028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.318063 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1130 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.343029 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23389 82.19% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2450 8.61% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1057 3.71% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 365 1.28% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 316 1.11% 96.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 193 0.68% 97.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 226 0.79% 98.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 154 0.54% 98.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 307 1.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22639 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2318 8.39% 90.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1067 3.86% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 382 1.38% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 325 1.18% 96.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 202 0.73% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 208 0.75% 98.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 146 0.53% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 325 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28457 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 27612 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12778 # Number of instructions committed @@ -707,28 +707,28 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6389 # Class of committed instruction system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 307 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 325 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133653 # The number of ROB reads -system.cpu.rob.rob_writes 59305 # The number of ROB writes -system.cpu.timesIdled 412 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 130940 # The number of ROB reads +system.cpu.rob.rob_writes 58397 # The number of ROB writes +system.cpu.timesIdled 389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23301 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.456058 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.456058 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.728029 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.134119 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.134119 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.268238 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 27427 # number of integer regfile reads -system.cpu.int_regfile_writes 15512 # number of integer regfile writes +system.cpu.cpi::0 8.003766 # CPI: Cycles Per Instruction +system.cpu.cpi::1 8.003766 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.001883 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.124941 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.124941 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.249882 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 26966 # number of integer regfile reads +system.cpu.int_regfile_writes 15368 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -736,289 +736,289 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.485703 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 5082 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.561605 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 213.719872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 5036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 346 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.554913 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.485703 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.085205 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 12575 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 12575 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 4060 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 4060 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 5082 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 5082 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 5082 # number of overall hits -system.cpu.dcache.overall_hits::total 5082 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses -system.cpu.dcache.overall_misses::total 1031 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22902750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22902750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 50997162 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 50997162 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 73899912 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 73899912 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 73899912 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 73899912 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 4383 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 213.719872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.084473 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 12454 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 12454 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 4006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 4006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1030 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 5036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 5036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 5036 # number of overall hits +system.cpu.dcache.overall_hits::total 5036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses +system.cpu.dcache.overall_misses::total 1018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26557000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26557000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48843926 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48843926 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75400926 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75400926 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75400926 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75400926 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4324 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4324 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 6113 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 6113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 6113 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 6113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073694 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.073694 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.168657 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.168657 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.168657 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.168657 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70906.346749 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70906.346749 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72029.889831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72029.889831 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71677.897187 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71677.897187 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5816 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 6054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 6054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 6054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 6054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073543 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073543 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83512.578616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83512.578616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69777.037143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69777.037143 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74067.707269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74067.707269 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5713 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.835616 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.946154 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 682 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 349 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 349 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16652250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16652250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28536240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536240 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28536240 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046543 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046543 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057091 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057091 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81628.676471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81628.676471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81958.551724 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81958.551724 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 556 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 556 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 672 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18304750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18304750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11840493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11840493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30145243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30145243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30145243 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30145243 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046716 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046716 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057152 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057152 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90617.574257 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90617.574257 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82225.645833 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82225.645833 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements::0 7 # number of replacements +system.cpu.icache.tags.replacements::0 8 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements -system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 320.653868 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4726 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.525478 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements::total 8 # number of replacements +system.cpu.icache.tags.tagsinuse 322.759154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4537 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.111285 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 320.653868 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.156569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.156569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11936 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11936 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4726 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4726 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4726 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4726 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4726 # number of overall hits -system.cpu.icache.overall_hits::total 4726 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928 # number of overall misses -system.cpu.icache.overall_misses::total 928 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64563245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64563245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64563245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64563245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64563245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64563245 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5654 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5654 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5654 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5654 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.164132 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.164132 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.164132 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.164132 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.164132 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.164132 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69572.462284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69572.462284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69572.462284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69572.462284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69572.462284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69572.462284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4138 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 322.759154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.157597 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.157597 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 630 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 243 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.307617 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11558 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11558 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4537 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4537 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4537 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4537 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4537 # number of overall hits +system.cpu.icache.overall_hits::total 4537 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 923 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 923 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 923 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 923 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 923 # number of overall misses +system.cpu.icache.overall_misses::total 923 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70921745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70921745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70921745 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70921745 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70921745 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70921745 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5460 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5460 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5460 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5460 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169048 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.169048 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.169048 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.169048 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.169048 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.169048 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76838.293608 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76838.293608 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76838.293608 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76838.293608 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76838.293608 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76838.293608 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3978 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 87 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.855422 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.724138 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 300 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 300 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 300 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 300 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46837996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46837996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46837996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46837996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46837996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46837996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.111072 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.111072 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.111072 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74582.796178 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74582.796178 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74582.796178 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74582.796178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74582.796178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74582.796178 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 285 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 285 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 285 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 285 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 285 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51664496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51664496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51664496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51664496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51664496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51664496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116850 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116850 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116850 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80978.833856 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80978.833856 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80978.833856 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80978.833856 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80978.833856 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80978.833856 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 443.003584 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 444.038251 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 830 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 838 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002387 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 321.314753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 121.688831 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009806 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013519 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 830 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 495 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 323.497640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 120.540612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 838 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 537 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025574 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 8854 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 8854 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 626 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 830 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 626 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 349 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 626 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 349 # number of overall misses -system.cpu.l2cache.overall_misses::total 975 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46183500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16439250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 62622750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11732750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11732750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46183500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28172000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 74355500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46183500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28172000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 74355500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 628 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 832 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 628 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 349 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 349 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 636 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 838 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 144 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 144 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 636 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 346 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 982 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 636 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 346 # number of overall misses +system.cpu.l2cache.overall_misses::total 982 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 51000750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 18093750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 69094500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11692500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11692500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 51000750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 29786250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 80787000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 51000750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 29786250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 80787000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 840 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 144 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 144 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 984 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996865 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997619 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996865 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997967 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996865 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73775.559105 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80584.558824 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75449.096386 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80915.517241 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80915.517241 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73775.559105 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80722.063037 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76262.051282 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73775.559105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80722.063037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76262.051282 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997967 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80189.858491 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89573.019802 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82451.670644 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81197.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81197.916667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80189.858491 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86087.427746 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82267.820774 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80189.858491 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86087.427746 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82267.820774 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1027,101 +1027,101 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38371500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13925750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52297250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38371500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23885000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 62256500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38371500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23885000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 62256500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 636 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 636 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 982 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 636 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 982 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43045250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15573250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58618500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9895500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9895500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43045250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25468750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 68514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43045250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25468750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 68514000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997619 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997967 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61296.325879 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68263.480392 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63008.734940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68684.482759 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68684.482759 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61296.325879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68438.395415 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63852.820513 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61296.325879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68438.395415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63852.820513 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997967 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67681.210692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77095.297030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69950.477327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68718.750000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68718.750000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67681.210692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73609.104046 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69769.857434 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67681.210692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73609.104046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69769.857434 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 144 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 144 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 62976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 984 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 977 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 984 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1032000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 556000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 984 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 492000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1076750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 574250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 830 # Transaction distribution -system.membus.trans_dist::ReadResp 830 # Transaction distribution -system.membus.trans_dist::ReadExReq 145 # Transaction distribution -system.membus.trans_dist::ReadExResp 145 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 838 # Transaction distribution +system.membus.trans_dist::ReadResp 838 # Transaction distribution +system.membus.trans_dist::ReadExReq 144 # Transaction distribution +system.membus.trans_dist::ReadExResp 144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62848 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 975 # Request fanout histogram +system.membus.snoop_fanout::samples 982 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 982 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 975 # Request fanout histogram -system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9051500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 38.1 # Layer utilization (%) +system.membus.snoop_fanout::total 982 # Request fanout histogram +system.membus.reqLayer0.occupancy 1219500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 5224000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index b851aeb29..fe03e9faf 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25944000 # Number of ticks simulated -final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27482500 # Number of ticks simulated +final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95549 # Simulator instruction rate (inst/s) -host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171686089 # Simulator tick rate (ticks/s) -host_mem_usage 292480 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 86365 # Simulator instruction rate (inst/s) +host_op_rate 86358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 164391633 # Simulator tick rate (ticks/s) +host_mem_usage 291648 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22016 # Nu system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory system.physmem.num_reads::total 492 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 848596978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 365094049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1213691027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 848596978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 848596978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 848596978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 365094049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1213691027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 801091604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344655690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1145747294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 801091604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 801091604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 801091604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344655690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1145747294 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 492 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25892500 # Total gap between requests +system.physmem.totGap 27431000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,307 +186,307 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.444444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.526762 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 350.678412 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 16.67% 16.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 24 33.33% 50.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation -system.physmem.totQLat 2786000 # Total ticks spent queuing -system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.732394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 270.110571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.824701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 18.31% 18.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 25.35% 43.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 9.86% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.41% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation +system.physmem.totQLat 3613750 # Total ticks spent queuing +system.physmem.totMemAccLat 12838750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7345.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26095.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1145.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1145.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.48 # Data bus utilization in percentage -system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.95 # Data bus utilization in percentage +system.physmem.busUtilRead 8.95 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 411 # Number of row buffer hits during reads +system.physmem.readRowHits 412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52627.03 # Average gap between requests -system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 55754.07 # Average gap between requests +system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2059200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16044930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20252445 # Total energy per rank (pJ) -system.physmem_0.averagePower 857.473194 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 279250 # Time in different power states +system.physmem_0.actBackEnergy 15743115 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20156895 # Total energy per rank (pJ) +system.physmem_0.averagePower 853.427679 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 520250 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22761250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22332250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 14873580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19192260 # Total energy per rank (pJ) -system.physmem_1.averagePower 812.585763 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2246250 # Time in different power states +system.physmem_1.actBackEnergy 15564420 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 518250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19277100 # Total energy per rank (pJ) +system.physmem_1.averagePower 816.177825 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2637000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21062250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22058500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 8578 # Number of BP lookups -system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3046 # Number of BTB hits +system.cpu.branchPred.lookups 8538 # Number of BP lookups +system.cpu.branchPred.condPredicted 5461 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3053 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 51.087684 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 51889 # number of cpu cycles simulated +system.cpu.numCycles 54966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed -system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 14246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 40057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 8538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 15957 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 6438 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.235488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.378208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20898 64.46% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5494 16.95% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 685 2.11% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 505 1.56% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 819 2.53% 87.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 909 2.80% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 334 1.03% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 371 1.14% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2407 7.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 6844 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 32422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155332 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.728760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11347 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12433 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 6847 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 640 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 30502 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 6918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups +system.cpu.rename.IdleCycles 11955 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1146 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9859 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 6898 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1409 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27684 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 1012 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51692 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 42838 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 768 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 767 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 3842 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3673 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 23655 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.676208 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.425800 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24009 74.05% 74.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3087 9.52% 83.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1572 4.85% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1483 4.57% 93.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 954 2.94% 95.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 709 2.19% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 413 1.27% 99.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 155 0.48% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32422 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111 49.33% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 49 21.78% 71.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 65 28.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16300 74.35% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3501 15.97% 90.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21921 # Type of FU issued -system.cpu.iq.rate 0.422459 # Inst issue rate -system.cpu.iq.fu_busy_cnt 226 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21924 # Type of FU issued +system.cpu.iq.rate 0.398865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 225 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22149 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 1147 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25507 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3673 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20914 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3347 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1127 # number of nop insts executed -system.cpu.iew.exec_refs 5373 # number of memory reference insts executed -system.cpu.iew.exec_branches 4425 # Number of branches executed +system.cpu.iew.exec_nop 1126 # number of nop insts executed +system.cpu.iew.exec_refs 5371 # number of memory reference insts executed +system.cpu.iew.exec_branches 4427 # Number of branches executed system.cpu.iew.exec_stores 2024 # Number of stores executed -system.cpu.iew.exec_rate 0.402956 # Inst execution rate -system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 20237 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9846 # num instructions producing a value -system.cpu.iew.wb_consumers 12767 # num instructions consuming a value +system.cpu.iew.exec_rate 0.380490 # Inst execution rate +system.cpu.iew.wb_sent 20501 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 20244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9848 # num instructions producing a value +system.cpu.iew.wb_consumers 12670 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back +system.cpu.iew.wb_rate 0.368300 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.777269 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10287 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1059 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30361 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.499391 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308685 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23816 78.44% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3429 11.29% 89.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1193 3.93% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 637 2.10% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 331 1.09% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 224 0.74% 97.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 397 1.31% 98.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 272 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30361 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -532,105 +532,105 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54809 # The number of ROB reads -system.cpu.rob.rob_writes 52997 # The number of ROB writes -system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54715 # The number of ROB reads +system.cpu.rob.rob_writes 52974 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads -system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 33401 # number of integer regfile reads -system.cpu.int_regfile_writes 18599 # number of integer regfile writes -system.cpu.misc_regfile_reads 7136 # number of misc regfile reads +system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads +system.cpu.ipc 0.262635 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.262635 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 33408 # number of integer regfile reads +system.cpu.int_regfile_writes 18606 # number of integer regfile writes +system.cpu.misc_regfile_reads 7133 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 98.556611 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4125 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.061224 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.556611 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024062 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024062 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 9489 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9489 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits -system.cpu.dcache.overall_hits::total 4118 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4119 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4119 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4119 # number of overall hits +system.cpu.dcache.overall_hits::total 4119 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 137 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 137 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses -system.cpu.dcache.overall_misses::total 548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 546 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 546 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 546 # number of overall misses +system.cpu.dcache.overall_misses::total 546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9397000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27538481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27538481 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36935481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36935481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36935481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36935481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3223 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4665 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4665 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4665 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4665 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042507 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042507 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.117042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67647.401099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67647.401099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.818182 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 398 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -639,135 +639,135 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5143250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5143250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6389250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6389250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11532500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11532500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020168 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031726 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79126.923077 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79126.923077 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76978.915663 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76978.915663 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 190.975563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5904 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.063584 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 190.975563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13252 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits -system.cpu.icache.overall_hits::total 5925 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses -system.cpu.icache.overall_misses::total 528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 13222 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13222 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5904 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5904 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5904 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5904 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5904 # number of overall hits +system.cpu.icache.overall_hits::total 5904 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 534 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 534 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 534 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 534 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 534 # number of overall misses +system.cpu.icache.overall_misses::total 534 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37367000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37367000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37367000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37367000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37367000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37367000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6438 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6438 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6438 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6438 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082945 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082945 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082945 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082945 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082945 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082945 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69975.655431 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69975.655431 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69975.655431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69975.655431 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 182 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 182 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 188 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 188 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 188 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 188 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 188 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 188 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26526250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26526250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26526250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26526250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26526250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26526250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053743 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.053743 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.053743 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76665.462428 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76665.462428 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 224.896195 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 190.368376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.527819 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006863 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses @@ -788,17 +788,17 @@ system.cpu.l2cache.demand_misses::total 492 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 492 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26158750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5078750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31237500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6304750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6304750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26158750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11383500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37542250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26158750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11383500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37542250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) @@ -821,17 +821,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995951 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76042.877907 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78134.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76375.305623 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75960.843373 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75960.843373 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76305.386179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76305.386179 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -851,17 +851,17 @@ system.cpu.l2cache.demand_mshr_misses::total 492 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4272750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26134000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21861250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31412250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21861250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31412250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses @@ -873,17 +873,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution @@ -908,10 +908,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 245000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.membus.trans_dist::ReadReq 409 # Transaction distribution system.membus.trans_dist::ReadResp 408 # Transaction distribution @@ -932,9 +932,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 492 # Request fanout histogram -system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2599750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 5faa1ad2c..56b893c5d 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 41368000 # Number of ticks simulated -final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 41368500 # Number of ticks simulated +final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 245276 # Simulator instruction rate (inst/s) -host_op_rate 245221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 668919684 # Simulator tick rate (ticks/s) -host_mem_usage 285672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 311873 # Simulator instruction rate (inst/s) +host_op_rate 311783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 850451247 # Simulator tick rate (ticks/s) +host_mem_usage 289340 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,40 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 331 # Transaction distribution -system.membus.trans_dist::ReadResp 331 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 416 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.1 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 82736 # number of cpu cycles simulated +system.cpu.numCycles 82737 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 82735.998000 # Number of busy cycles +system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched @@ -112,15 +89,123 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.991492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.991492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits +system.cpu.dcache.overall_hits::total 3529 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.dcache.overall_misses::total 138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4547500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4547500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 153.777491 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 153.777491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075087 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id @@ -139,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -157,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,36 +262,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14896500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14896500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14896500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14896500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14896500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14896500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53201.785714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53201.785714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.625818 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.105687 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.520131 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id @@ -230,17 +315,17 @@ system.cpu.l2cache.demand_misses::total 416 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17378000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses) @@ -263,17 +348,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995215 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.510574 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -293,17 +378,17 @@ system.cpu.l2cache.demand_mshr_misses::total 416 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13405500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5589000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5589000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses @@ -315,126 +400,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits -system.cpu.dcache.overall_hits::total 3529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -463,5 +440,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 420000 # La system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadReq 331 # Transaction distribution +system.membus.trans_dist::ReadResp 331 # Transaction distribution +system.membus.trans_dist::ReadExReq 85 # Transaction distribution +system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 416 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 416 # Request fanout histogram +system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index ffbae61d5..948908ba0 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,88 +1,88 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105542000 # Number of ticks simulated -final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000108 # Number of seconds simulated +sim_ticks 107944000 # Number of ticks simulated +final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163449 # Simulator instruction rate (inst/s) -host_op_rate 163449 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17392605 # Simulator tick rate (ticks/s) -host_mem_usage 309188 # Number of bytes of host memory used -host_seconds 6.07 # Real time elapsed on the host -sim_insts 991839 # Number of instructions simulated -sim_ops 991839 # Number of ops (including micro ops) simulated +host_inst_rate 162812 # Simulator instruction rate (inst/s) +host_op_rate 162812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17679745 # Simulator tick rate (ticks/s) +host_mem_usage 308116 # Number of bytes of host memory used +host_seconds 6.11 # Real time elapsed on the host +sim_insts 994048 # Number of instructions simulated +sim_ops 994048 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 664 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 665 # Number of read requests accepted +system.physmem.num_reads::total 669 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 214629808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100200104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47432002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11858000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 4150300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7707700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2964500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7707700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 396650115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 214629808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47432002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 4150300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2964500 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269176610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 214629808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100200104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47432002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11858000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 4150300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7707700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2964500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7707700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 396650115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 670 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 670 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 42880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side +system.physmem.bytesReadSys 42880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 115 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 27 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts -system.physmem.perBankRdBursts::4 65 # Per bank write bursts +system.physmem.perBankRdBursts::4 66 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts system.physmem.perBankRdBursts::6 18 # Per bank write bursts system.physmem.perBankRdBursts::7 24 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 22 # Per bank write bursts -system.physmem.perBankRdBursts::11 13 # Per bank write bursts +system.physmem.perBankRdBursts::9 29 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 14 # Per bank write bursts system.physmem.perBankRdBursts::12 65 # Per bank write bursts system.physmem.perBankRdBursts::13 38 # Per bank write bursts system.physmem.perBankRdBursts::14 17 # Per bank write bursts @@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 105514000 # Total gap between requests +system.physmem.totGap 107916000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 665 # Read request sizes (log2) +system.physmem.readPktSize::6 670 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,10 +120,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -216,556 +216,556 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation -system.physmem.totQLat 6421750 # Total ticks spent queuing -system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.702703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.430987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 234.776821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 43 29.05% 29.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39 26.35% 55.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25 16.89% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19 12.84% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 4.05% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 4.05% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 3.38% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.35% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 2.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation +system.physmem.totQLat 6539750 # Total ticks spent queuing +system.physmem.totMemAccLat 19102250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9760.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28510.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 397.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 397.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.busUtilRead 3.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 512 # Number of row buffer hits during reads +system.physmem.readRowHits 511 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 158667.67 # Average gap between requests -system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 161068.66 # Average gap between requests +system.physmem.pageHitRate 76.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2761200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ) -system.physmem_0.averagePower 738.913691 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states +system.physmem_0.actBackEnergy 39247065 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 26461500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76167750 # Total energy per rank (pJ) +system.physmem_0.averagePower 750.559832 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 46478250 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 54316750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.948851 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states +system.physmem_1.actBackEnergy 30855240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 33814500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 73943955 # Total energy per rank (pJ) +system.physmem_1.averagePower 728.745214 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 59727000 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 42022000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81296 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits +system.cpu0.branchPred.lookups 81450 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78581 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1205 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 78182 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75500 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.569543 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 747 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211085 # number of cpu cycles simulated +system.cpu0.numCycles 215889 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 20419 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 481443 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81450 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76247 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165590 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2709 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 2214 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7225 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 189580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.539524 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.227640 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32064 16.91% 16.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77818 41.05% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818 0.43% 58.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1146 0.60% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 623 0.33% 59.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 72992 38.50% 97.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 703 0.37% 98.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 447 0.24% 98.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2969 1.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::total 189580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.377277 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.230049 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing +system.cpu0.decode.BlockedCycles 19697 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152079 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 672 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1354 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 469796 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1354 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16409 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2266 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15970 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152076 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1505 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 466337 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1001 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 319451 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 929999 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 702902 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 305355 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14096 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle +system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4587 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148758 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75265 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72519 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72258 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 390345 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 12329 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.041339 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.140292 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 35140 18.54% 18.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4258 2.25% 20.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73622 38.83% 59.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73334 38.68% 98.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1646 0.87% 99.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 901 0.48% 99.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 423 0.22% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 182 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 74 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189580 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 91 32.73% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 84 30.22% 62.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 37.05% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164205 42.43% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 148197 38.29% 80.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74595 19.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued -system.cpu0.iq.rate 1.826459 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 386997 # Type of FU issued +system.cpu0.iq.rate 1.792574 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 403692 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 387275 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71895 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2491 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.iewSquashCycles 1354 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2232 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 464248 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148758 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75265 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 333 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1104 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 385946 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147890 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1051 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72677 # number of nop insts executed -system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76264 # Number of branches executed -system.cpu0.iew.exec_stores 74195 # Number of stores executed -system.cpu0.iew.exec_rate 1.821660 # Inst execution rate -system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 227520 # num instructions producing a value -system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value +system.cpu0.iew.exec_nop 72936 # number of nop insts executed +system.cpu0.iew.exec_refs 222349 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76534 # Number of branches executed +system.cpu0.iew.exec_stores 74459 # Number of stores executed +system.cpu0.iew.exec_rate 1.787706 # Inst execution rate +system.cpu0.iew.wb_sent 385475 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 385100 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 228400 # num instructions producing a value +system.cpu0.iew.wb_consumers 231722 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.783787 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.985664 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13801 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1205 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186928 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.409398 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.152220 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 35407 18.94% 18.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75555 40.42% 59.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1920 1.03% 60.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 633 0.34% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 494 0.26% 60.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71651 38.33% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 511 0.27% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 494 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 448740 # Number of instructions committed -system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186928 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 450384 # Number of instructions committed +system.cpu0.commit.committedOps 450384 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219085 # Number of memory references committed -system.cpu0.commit.loads 145719 # Number of loads committed +system.cpu0.commit.refs 219907 # Number of memory references committed +system.cpu0.commit.loads 146267 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75253 # Number of branches committed +system.cpu0.commit.branches 75527 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 302590 # Number of committed integer instructions. +system.cpu0.commit.int_insts 303686 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72259 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 158134 35.11% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 146351 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73640 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction -system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction +system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 645314 # The number of ROB reads -system.cpu0.rob.rob_writes 927635 # The number of ROB writes -system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 376671 # Number of Instructions Simulated -system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 687652 # number of integer regfile reads -system.cpu0.int_regfile_writes 310240 # number of integer regfile writes +system.cpu0.rob.rob_reads 649458 # The number of ROB reads +system.cpu0.rob.rob_writes 931043 # The number of ROB writes +system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 378041 # Number of Instructions Simulated +system.cpu0.committedOps 378041 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.571073 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.571073 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.751090 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.751090 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 690199 # number of integer regfile reads +system.cpu0.int_regfile_writes 311415 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads +system.cpu0.misc_regfile_reads 224240 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 140.939988 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 148370 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 867.660819 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits -system.cpu0.dcache.overall_hits::total 147973 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses -system.cpu0.dcache.overall_misses::total 1026 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.occ_blocks::cpu0.data 140.939988 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275273 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275273 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 598524 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 598524 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75399 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75399 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73059 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73059 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 148458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148458 # number of overall hits +system.cpu0.dcache.overall_hits::total 148458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 514 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 514 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 539 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 539 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1053 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1053 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1053 # number of overall misses +system.cpu0.dcache.overall_misses::total 1053 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17626915 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17626915 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36442515 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36442515 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 680000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 680000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 54069430 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 54069430 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 54069430 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 54069430 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75913 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75913 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73598 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73598 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 149511 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149511 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 149511 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 149511 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006771 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006771 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007324 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007324 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007043 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007043 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 79.692308 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002430 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 35745.961749 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 35745.961749 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41286.184358 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41286.184358 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17420.454545 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17420.454545 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 330 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 330 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 362 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 362 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 692 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 692 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 184 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6770753 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6770753 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8530978 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8530978 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 646500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 646500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15301731 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15301731 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15301731 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15301731 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002405 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002405 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002415 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002415 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 319 # number of replacements -system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 323 # number of replacements +system.cpu0.icache.tags.tagsinuse 240.188663 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6428 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.469055 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id +system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.188663 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469118 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.469118 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6347 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6347 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6347 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6347 # number of overall hits -system.cpu0.icache.overall_hits::total 6347 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 792 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 792 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 792 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 792 # number of overall misses -system.cpu0.icache.overall_misses::total 792 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36432996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 36432996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 36432996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 36432996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 36432996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 36432996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7139 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7139 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7839 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7839 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6428 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6428 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6428 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6428 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6428 # number of overall hits +system.cpu0.icache.overall_hits::total 6428 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses +system.cpu0.icache.overall_misses::total 797 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40514746 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40514746 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40514746 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40514746 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40514746 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40514746 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7225 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7225 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7225 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7225 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7225 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7225 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110311 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110311 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110311 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110311 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110311 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110311 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 50834.060226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 50834.060226 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,410 +774,410 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 182 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 182 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 182 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31043001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31043001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31043001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31043001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31043001 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31043001 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085121 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085121 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085121 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 48230 # Number of BP lookups -system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits +system.cpu1.branchPred.lookups 52261 # Number of BP lookups +system.cpu1.branchPred.condPredicted 48386 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1341 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 44394 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 43169 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.240618 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 160735 # number of cpu cycles simulated +system.cpu1.numCycles 162232 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 31153 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 288417 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52261 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44075 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 122623 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2833 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1159 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 21623 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156364 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.844523 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.218152 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 56063 35.85% 35.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 50599 32.36% 68.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6236 3.99% 72.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3531 2.26% 74.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 937 0.60% 75.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 32564 20.83% 95.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1222 0.78% 96.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 843 0.54% 97.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4369 2.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full -system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 156364 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.322137 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.777806 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18077 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 54814 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 78767 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3280 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1416 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 271927 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1416 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18807 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 25020 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13667 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 79411 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 18033 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 268621 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15397 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 31 # Number of times rename has blocked due to LQ full +system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 189765 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 514915 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 401460 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 175087 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14678 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 22640 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 74986 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 35614 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 35483 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 30428 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 223482 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12719 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.439008 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.385420 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 59519 38.06% 38.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20894 13.36% 51.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35016 22.39% 73.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 34585 22.12% 95.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3417 2.19% 98.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1600 1.02% 99.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 882 0.56% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 240 0.15% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 211 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156364 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 92 27.88% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 29 8.79% 36.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 110922 49.30% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 79078 35.14% 84.44% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 35009 15.56% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued -system.cpu1.iq.rate 1.263247 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 225009 # Type of FU issued +system.cpu1.iq.rate 1.386958 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 242381 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 225339 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30296 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2626 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1552 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1416 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7338 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 266019 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 165 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 74986 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 35614 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 34 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1125 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1578 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 223948 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 74035 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 32947 # number of nop insts executed -system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed -system.cpu1.iew.exec_branches 42219 # Number of branches executed -system.cpu1.iew.exec_stores 29534 # Number of stores executed -system.cpu1.iew.exec_rate 1.256422 # Inst execution rate -system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 112178 # num instructions producing a value -system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value +system.cpu1.iew.exec_nop 36391 # number of nop insts executed +system.cpu1.iew.exec_refs 108940 # number of memory reference insts executed +system.cpu1.iew.exec_branches 45914 # Number of branches executed +system.cpu1.iew.exec_stores 34905 # Number of stores executed +system.cpu1.iew.exec_rate 1.380418 # Inst execution rate +system.cpu1.iew.wb_sent 223649 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 223369 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 126652 # num instructions producing a value +system.cpu1.iew.wb_consumers 133295 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.376849 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.950163 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14380 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5466 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1341 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 153714 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.636819 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.057713 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 64759 42.13% 42.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42554 27.68% 69.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5173 3.37% 73.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6281 4.09% 77.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1529 0.99% 78.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30355 19.75% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 785 0.51% 98.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 966 0.63% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1312 0.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 226660 # Number of instructions committed -system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 153714 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 251602 # Number of instructions committed +system.cpu1.commit.committedOps 251602 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 92171 # Number of memory references committed -system.cpu1.commit.loads 63450 # Number of loads committed -system.cpu1.commit.membars 6533 # Number of memory barriers committed -system.cpu1.commit.branches 41215 # Number of branches committed +system.cpu1.commit.refs 106422 # Number of memory references committed +system.cpu1.commit.loads 72360 # Number of loads committed +system.cpu1.commit.membars 4751 # Number of memory barriers committed +system.cpu1.commit.branches 44778 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 155506 # Number of committed integer instructions. +system.cpu1.commit.int_insts 173320 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 35567 14.14% 14.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 104862 41.68% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 77111 30.65% 86.46% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 34062 13.54% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 395483 # The number of ROB reads -system.cpu1.rob.rob_writes 484550 # The number of ROB writes -system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 188125 # Number of Instructions Simulated -system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 343348 # number of integer regfile reads -system.cpu1.int_regfile_writes 161358 # number of integer regfile writes +system.cpu1.rob.rob_reads 417798 # The number of ROB reads +system.cpu1.rob.rob_writes 534614 # The number of ROB writes +system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 211284 # Number of Instructions Simulated +system.cpu1.committedOps 211284 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.767839 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.767839 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.302357 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.302357 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 386957 # number of integer regfile reads +system.cpu1.int_regfile_writes 181537 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads +system.cpu1.misc_regfile_reads 110600 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.579817 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 40184 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1435.142857 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.579817 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049961 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.049961 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits -system.cpu1.dcache.overall_hits::total 68186 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu1.dcache.tags.tag_accesses 311400 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 311400 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 43257 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43257 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 33840 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 33840 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 77097 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 77097 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 77097 # number of overall hits +system.cpu1.dcache.overall_hits::total 77097 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 466 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 466 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 153 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 153 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses -system.cpu1.dcache.overall_misses::total 559 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency +system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses +system.cpu1.dcache.overall_misses::total 619 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9865731 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9865731 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3999011 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3999011 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 673507 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 673507 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13864742 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13864742 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13864742 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13864742 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 43723 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 43723 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 33993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 33993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 77716 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 77716 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 77716 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 77716 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010658 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010658 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004501 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004501 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.826087 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007965 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007965 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007965 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007965 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1186,519 +1186,519 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 344 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 344 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_misses::cpu1.data 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 275 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1943270 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1943270 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1707489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1707489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 587993 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 587993 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3650759 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3650759 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3650759 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3650759 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003820 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003820 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003177 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003177 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.826087 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003539 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003539 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 388 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 385 # number of replacements +system.cpu1.icache.tags.tagsinuse 83.683741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21045 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 42.344064 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu1.icache.tags.occ_blocks::cpu1.inst 83.683741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.163445 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.163445 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 25352 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 25352 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 24292 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 24292 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 24292 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 24292 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 24292 # number of overall hits -system.cpu1.icache.overall_hits::total 24292 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 562 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 562 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 562 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 562 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 562 # number of overall misses -system.cpu1.icache.overall_misses::total 562 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu1.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 22120 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22120 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 21045 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21045 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21045 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21045 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21045 # number of overall hits +system.cpu1.icache.overall_hits::total 21045 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 578 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 578 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 578 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 578 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 578 # number of overall misses +system.cpu1.icache.overall_misses::total 578 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14251747 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14251747 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14251747 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14251747 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14251747 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14251747 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21623 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21623 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21623 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21623 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21623 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21623 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026731 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.026731 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026731 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.026731 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026731 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.026731 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24657.001730 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24657.001730 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11245503 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11245503 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11245503 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11245503 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11245503 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11245503 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022985 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022985 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022985 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 55295 # Number of BP lookups -system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits +system.cpu2.branchPred.lookups 51309 # Number of BP lookups +system.cpu2.branchPred.condPredicted 47950 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1280 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 43975 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 43053 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.903354 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 160375 # number of cpu cycles simulated +system.cpu2.numCycles 161860 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 31583 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 282068 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51309 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 43939 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 125716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2717 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1207 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 22884 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 412 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 159877 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.764281 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.167875 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 59518 37.23% 37.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51095 31.96% 69.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7306 4.57% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3438 2.15% 75.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 997 0.62% 76.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 31616 19.78% 96.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1254 0.78% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 769 0.48% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3884 2.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full -system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 159877 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.316996 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.742667 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17468 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 61085 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 76240 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3716 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1358 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 267722 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1358 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18170 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 29188 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12834 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 77782 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 20535 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 264399 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 18336 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 185298 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 503121 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 392507 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 170476 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14822 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 25168 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 73362 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 34382 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 35300 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 29228 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 218628 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13020 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.379166 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.379581 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 63376 39.64% 39.64% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23374 14.62% 54.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33553 20.99% 75.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 33206 20.77% 96.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3423 2.14% 98.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1623 1.02% 99.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 877 0.55% 99.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 230 0.14% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 215 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 159877 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 86 23.69% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 68 18.73% 42.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 108751 49.32% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 78120 35.43% 84.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 33626 15.25% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued -system.cpu2.iq.rate 1.514600 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 220497 # Type of FU issued +system.cpu2.iq.rate 1.362270 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 238674 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 220860 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28926 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2863 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1691 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1358 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8128 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 261616 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 204 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 73362 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 34382 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1045 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1500 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 219377 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 72164 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1120 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 39706 # number of nop insts executed -system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed -system.cpu2.iew.exec_branches 49059 # Number of branches executed -system.cpu2.iew.exec_stores 39036 # Number of stores executed -system.cpu2.iew.exec_rate 1.507585 # Inst execution rate -system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 138145 # num instructions producing a value -system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value +system.cpu2.iew.exec_nop 36005 # number of nop insts executed +system.cpu2.iew.exec_refs 105679 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45327 # Number of branches executed +system.cpu2.iew.exec_stores 33515 # Number of stores executed +system.cpu2.iew.exec_rate 1.355350 # Inst execution rate +system.cpu2.iew.wb_sent 219089 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 218768 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 123331 # num instructions producing a value +system.cpu2.iew.wb_consumers 129941 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.351588 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.949131 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14642 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6361 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1280 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 157221 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.570534 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.031430 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 69336 44.10% 44.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 41971 26.70% 70.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5151 3.28% 74.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7156 4.55% 78.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1534 0.98% 79.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28975 18.43% 98.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 827 0.53% 98.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1310 0.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 272860 # Number of instructions committed -system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 157221 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 246921 # Number of instructions committed +system.cpu2.commit.committedOps 246921 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 117938 # Number of memory references committed -system.cpu2.commit.loads 79744 # Number of loads committed -system.cpu2.commit.membars 3865 # Number of memory barriers committed -system.cpu2.commit.branches 48024 # Number of branches committed +system.cpu2.commit.refs 103190 # Number of memory references committed +system.cpu2.commit.loads 70499 # Number of loads committed +system.cpu2.commit.membars 5644 # Number of memory barriers committed +system.cpu2.commit.branches 44296 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 188084 # Number of committed integer instructions. +system.cpu2.commit.int_insts 169605 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 35083 14.21% 14.21% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 103004 41.72% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 76143 30.84% 86.76% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 32691 13.24% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 438358 # The number of ROB reads -system.cpu2.rob.rob_writes 577962 # The number of ROB writes -system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 230180 # Number of Instructions Simulated -system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 421380 # number of integer regfile reads -system.cpu2.int_regfile_writes 197053 # number of integer regfile writes +system.cpu2.rob.rob_reads 416888 # The number of ROB reads +system.cpu2.rob.rob_writes 525783 # The number of ROB writes +system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1983 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 46662 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 206194 # Number of Instructions Simulated +system.cpu2.committedOps 206194 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.784989 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.784989 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.273903 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.273903 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 376797 # number of integer regfile reads +system.cpu2.int_regfile_writes 176595 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads +system.cpu2.misc_regfile_reads 107278 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.900864 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 44302 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1582.214286 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 24.051885 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 38880 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1340.689655 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.900864 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050588 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.050588 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.051885 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.046976 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.046976 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 341013 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 341013 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 46548 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 46548 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 37978 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 37978 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 84526 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 84526 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 84526 # number of overall hits -system.cpu2.dcache.overall_hits::total 84526 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 448 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 448 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 149 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 149 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 597 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 597 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 597 # number of overall misses -system.cpu2.dcache.overall_misses::total 597 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7705986 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7705986 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3669012 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3669012 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 505508 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 505508 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 11374998 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 11374998 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 11374998 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 11374998 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 46996 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 46996 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 38127 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 38127 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 85123 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 85123 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 85123 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 85123 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009533 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009533 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003908 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003908 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.820896 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007013 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007013 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007013 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007013 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17200.861607 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17200.861607 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24624.241611 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 24624.241611 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9191.054545 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9191.054545 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 19053.597990 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 19053.597990 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 303893 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 303893 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42781 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42781 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 32487 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 32487 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 75268 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 75268 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 75268 # number of overall hits +system.cpu2.dcache.overall_hits::total 75268 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 440 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 440 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 573 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 573 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 573 # number of overall misses +system.cpu2.dcache.overall_misses::total 573 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7341783 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 7341783 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2962762 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2962762 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 594005 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 594005 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 10304545 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 10304545 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 10304545 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 10304545 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 43221 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 32620 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 32620 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 75841 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 75841 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 75841 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 75841 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010180 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010180 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004077 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004077 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.802817 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007555 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007555 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007555 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007555 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1707,519 +1707,518 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 289 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 330 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 330 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 285 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 31 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 316 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 316 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 316 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 257 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 257 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1424773 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1424773 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1555988 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1555988 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 508495 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 508495 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2980761 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2980761 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2980761 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2980761 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003586 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003586 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003127 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003127 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003389 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003389 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.083871 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.083871 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15254.784314 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15254.784314 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8920.964912 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8920.964912 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.tags.replacements 378 # number of replacements -system.cpu2.icache.tags.tagsinuse 84.872672 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 18881 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 38.532653 # Average number of references to valid blocks. +system.cpu2.icache.tags.replacements 384 # number of replacements +system.cpu2.icache.tags.tagsinuse 78.035025 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 22324 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 494 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.190283 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.872672 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165767 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.165767 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id +system.cpu2.icache.tags.occ_blocks::cpu2.inst 78.035025 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.152412 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.152412 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits -system.cpu2.icache.overall_hits::total 18881 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses -system.cpu2.icache.overall_misses::total 570 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13340243 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 13340243 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 13340243 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 13340243 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 13340243 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 13340243 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19451 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19451 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu2.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 23378 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 23378 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 22324 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 22324 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 22324 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 22324 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 22324 # number of overall hits +system.cpu2.icache.overall_hits::total 22324 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 560 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 560 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 560 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 560 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 560 # number of overall misses +system.cpu2.icache.overall_misses::total 560 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8454990 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8454990 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8454990 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8454990 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8454990 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8454990 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 22884 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 22884 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 22884 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 22884 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 22884 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 22884 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024471 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024471 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024471 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024471 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024471 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024471 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15098.196429 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15098.196429 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15098.196429 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15098.196429 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 66 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 66 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 66 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 494 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 494 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 494 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 494 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 494 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 494 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6668508 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6668508 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6668508 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6668508 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6668508 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6668508 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021587 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021587 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021587 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 49708 # Number of BP lookups -system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits +system.cpu3.branchPred.lookups 49957 # Number of BP lookups +system.cpu3.branchPred.condPredicted 46526 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1263 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 42773 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 41661 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.400229 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 160031 # number of cpu cycles simulated +system.cpu3.numCycles 161075 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32422 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 272949 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49957 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 42547 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 124988 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2685 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1170 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23669 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 411 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 159935 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.706625 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.149562 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 61940 38.73% 38.73% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 50129 31.34% 70.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7684 4.80% 74.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3433 2.15% 77.02% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1026 0.64% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 29810 18.64% 96.30% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1265 0.79% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 775 0.48% 97.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3873 2.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full -system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 159935 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.310147 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.694546 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17524 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 64435 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 72722 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3902 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1342 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 258692 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1342 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18198 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 31170 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12771 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 73832 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22612 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 255419 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 23 # Number of times rename has blocked due to LQ full +system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 178600 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 483471 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 377749 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 164114 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14486 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1167 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 27248 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 70256 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32624 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33902 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 27488 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 210626 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12659 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.332429 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.375890 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 65625 41.03% 41.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24603 15.38% 56.42% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31869 19.93% 76.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 31495 19.69% 96.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3384 2.12% 98.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1646 1.03% 99.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 234 0.15% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 159935 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 83 23.71% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 58 16.57% 40.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 59.71% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 105687 49.59% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 75490 35.42% 85.02% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31925 14.98% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued -system.cpu3.iq.rate 1.322737 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 213102 # Type of FU issued +system.cpu3.iq.rate 1.322999 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 230693 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 213452 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 27230 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2740 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewSquashCycles 1342 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8471 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 252649 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 70256 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32624 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1081 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1012 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1478 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 211973 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 69143 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1129 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34395 # number of nop insts executed -system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed -system.cpu3.iew.exec_branches 43728 # Number of branches executed -system.cpu3.iew.exec_stores 31474 # Number of stores executed -system.cpu3.iew.exec_rate 1.315601 # Inst execution rate -system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 117676 # num instructions producing a value -system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value +system.cpu3.iew.exec_nop 34658 # number of nop insts executed +system.cpu3.iew.exec_refs 100953 # number of memory reference insts executed +system.cpu3.iew.exec_branches 44015 # Number of branches executed +system.cpu3.iew.exec_stores 31810 # Number of stores executed +system.cpu3.iew.exec_rate 1.315989 # Inst execution rate +system.cpu3.iew.wb_sent 211700 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 211399 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 118601 # num instructions producing a value +system.cpu3.iew.wb_consumers 125234 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.312426 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.947035 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14249 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6748 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1263 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157342 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.514834 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.009338 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 72048 45.79% 45.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 40652 25.84% 71.63% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5170 3.29% 74.91% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7572 4.81% 79.73% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1532 0.97% 80.70% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 27266 17.33% 98.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 833 0.53% 98.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 969 0.62% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1300 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 236439 # Number of instructions committed -system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157342 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 238347 # Number of instructions committed +system.cpu3.commit.committedOps 238347 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 97502 # Number of memory references committed -system.cpu3.commit.loads 66856 # Number of loads committed -system.cpu3.commit.membars 6091 # Number of memory barriers committed -system.cpu3.commit.branches 42698 # Number of branches committed +system.cpu3.commit.refs 98515 # Number of memory references committed +system.cpu3.commit.loads 67516 # Number of loads committed +system.cpu3.commit.membars 6034 # Number of memory barriers committed +system.cpu3.commit.branches 42994 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 162319 # Number of committed integer instructions. +system.cpu3.commit.int_insts 163632 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33784 14.17% 14.17% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 100014 41.96% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 73550 30.86% 86.99% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30999 13.01% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 405464 # The number of ROB reads -system.cpu3.rob.rob_writes 504751 # The number of ROB writes -system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 196863 # Number of Instructions Simulated -system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 359772 # number of integer regfile reads -system.cpu3.int_regfile_writes 168916 # number of integer regfile writes +system.cpu3.rob.rob_reads 408052 # The number of ROB reads +system.cpu3.rob.rob_writes 507784 # The number of ROB writes +system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1140 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 47445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 198529 # Number of Instructions Simulated +system.cpu3.committedOps 198529 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.811342 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.811342 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.232525 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.232525 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 362535 # number of integer regfile reads +system.cpu3.int_regfile_writes 170128 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads +system.cpu3.misc_regfile_reads 102551 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.432858 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 36837 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1270.241379 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 23.026048 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 37058 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1323.500000 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.432858 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047720 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047720 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.026048 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.044973 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.044973 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 289352 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 289352 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 41209 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41209 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 30434 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 30434 # number of WriteReq hits +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 291822 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 291822 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41456 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41456 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 30794 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 30794 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 71643 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 71643 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 71643 # number of overall hits -system.cpu3.dcache.overall_hits::total 71643 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 419 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 419 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 560 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 560 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 560 # number of overall misses -system.cpu3.dcache.overall_misses::total 560 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5396537 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 5396537 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2783262 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2783262 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 481005 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 481005 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 8179799 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 8179799 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 8179799 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 8179799 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41628 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41628 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 30575 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 30575 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 72203 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 72203 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 72203 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 72203 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010065 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010065 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004612 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004612 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007756 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007756 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007756 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007756 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12879.563246 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12879.563246 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19739.446809 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19739.446809 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8438.684211 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 8438.684211 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 14606.783929 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 14606.783929 # average overall miss latency +system.cpu3.dcache.demand_hits::cpu3.data 72250 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 72250 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 72250 # number of overall hits +system.cpu3.dcache.overall_hits::total 72250 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 440 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 440 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 577 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 577 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 577 # number of overall misses +system.cpu3.dcache.overall_misses::total 577 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7521134 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 7521134 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3020012 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3020012 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 589507 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 589507 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 10541146 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 10541146 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 10541146 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 10541146 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41896 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41896 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30931 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30931 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 72827 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 72827 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 72827 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 72827 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010502 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010502 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004429 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004429 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007923 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007923 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007923 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007923 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2228,106 +2227,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 259 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 288 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 293 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 293 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 293 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 293 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1078521 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1078521 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1312238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1312238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 366995 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 366995 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2390759 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2390759 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2390759 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2390759 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003844 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003844 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003500 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003500 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003698 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003698 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.756250 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.756250 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12263.906542 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12263.906542 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6438.508772 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6438.508772 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.demand_mshr_hits::cpu3.data 322 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 322 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 322 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 255 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 255 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1429011 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1429011 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1527238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1527238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 508493 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 508493 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2956249 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2956249 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2956249 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2956249 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003628 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003628 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003330 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003330 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003501 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003501 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9401.388158 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9401.388158 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9416.537037 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9416.537037 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.tags.replacements 386 # number of replacements -system.cpu3.icache.tags.tagsinuse 78.630086 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 23274 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 495 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 47.018182 # Average number of references to valid blocks. +system.cpu3.icache.tags.replacements 387 # number of replacements +system.cpu3.icache.tags.tagsinuse 75.442206 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 23109 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 46.403614 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 78.630086 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.153574 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.153574 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 75.442206 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.147348 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.147348 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 24325 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 24325 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 23274 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23274 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23274 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23274 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23274 # number of overall hits -system.cpu3.icache.overall_hits::total 23274 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 556 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 556 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 556 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 556 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 556 # number of overall misses -system.cpu3.icache.overall_misses::total 556 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7666496 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7666496 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7666496 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7666496 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7666496 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7666496 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 23830 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 23830 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 23830 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 23830 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 23830 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 23830 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023332 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023332 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023332 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023332 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023332 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023332 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13788.661871 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13788.661871 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13788.661871 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13788.661871 # average overall miss latency +system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 24167 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 24167 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 23109 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23109 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23109 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23109 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23109 # number of overall hits +system.cpu3.icache.overall_hits::total 23109 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 560 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 560 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 560 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 560 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 560 # number of overall misses +system.cpu3.icache.overall_misses::total 560 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7349496 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7349496 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7349496 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7349496 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7349496 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7349496 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 23669 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 23669 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 23669 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 23669 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 23669 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 23669 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023660 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023660 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023660 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023660 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023660 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023660 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13124.100000 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13124.100000 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13124.100000 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13124.100000 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2336,277 +2335,277 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 61 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 61 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 61 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 61 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 495 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 495 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 495 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 495 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 495 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 495 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5988753 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5988753 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5988753 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5988753 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5988753 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5988753 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020772 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.020772 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.020772 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12098.490909 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6152504 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6152504 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6152504 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6152504 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6152504 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6152504 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021040 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.021040 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.021040 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12354.425703 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 421.782597 # Cycle average of tags in use -system.l2c.tags.total_refs 1661 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 531 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.128060 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 421.791819 # Cycle average of tags in use +system.l2c.tags.total_refs 1669 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 536 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.113806 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.793367 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 288.136506 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.239710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.908939 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.685353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 57.810668 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.358893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.126194 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.722968 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.783957 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 289.037601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 57.982294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 60.100309 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.287110 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 5.207527 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.713016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.004391 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.675614 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004397 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000882 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004410 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000917 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000079 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 531 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008102 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 20025 # Number of tag accesses -system.l2c.tags.data_accesses 20025 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 248 # number of ReadReq hits +system.l2c.tags.occ_task_id_blocks::1024 536 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008179 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 20118 # Number of tag accesses +system.l2c.tags.data_accesses 20118 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 251 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 483 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 489 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 414 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 481 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 491 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1661 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1669 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 248 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 483 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 414 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1661 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 248 # number of overall hits +system.l2c.demand_hits::total 1669 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 251 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 483 # number of overall hits -system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 409 # number of overall hits -system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 489 # number of overall hits +system.l2c.overall_hits::cpu1.inst 414 # number of overall hits +system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu2.inst 481 # number of overall hits +system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu3.inst 491 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1661 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses +system.l2c.overall_hits::total 1669 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 364 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 546 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 551 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 364 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 677 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 361 # number of overall misses -system.l2c.overall_misses::cpu0.data 168 # number of overall misses -system.l2c.overall_misses::cpu1.inst 15 # number of overall misses -system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 81 # number of overall misses -system.l2c.overall_misses::cpu2.data 20 # number of overall misses -system.l2c.overall_misses::cpu3.inst 6 # number of overall misses +system.l2c.demand_misses::total 682 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 364 # number of overall misses +system.l2c.overall_misses::cpu0.data 169 # number of overall misses +system.l2c.overall_misses::cpu1.inst 83 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 13 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 7 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 677 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24898500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5922000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1027000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5770000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 523250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 593000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 38883750 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6920500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 837000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 851750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9656500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24898500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12842500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1027000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 912000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5770000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1570500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 593000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 926750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 48540250 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24898500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12842500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1027000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 912000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5770000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1570500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 593000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 926750 # number of overall miss cycles -system.l2c.overall_miss_latency::total 48540250 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 609 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 498 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::total 682 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 27791500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 6004250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 6396000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 553250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 1121000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 96750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 495500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 82500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 42540750 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8131000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1125500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 956000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 926750 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11139250 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 27791500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 14135250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6396000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1678750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 1121000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1052750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 495500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1009250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 53680000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 27791500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 14135250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6396000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1678750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 1121000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1052750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 495500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1009250 # number of overall miss cycles +system.l2c.overall_miss_latency::total 53680000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 615 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 490 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 494 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 495 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 498 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2207 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2220 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 609 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 498 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 490 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 495 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 615 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 494 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2338 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 609 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 498 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 490 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 495 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2351 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 615 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 494 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2338 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.592775 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.030120 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.165306 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.012121 # miss rate for ReadReq accesses +system.l2c.overall_accesses::total 2351 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.591870 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.167002 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.026316 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.247395 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.248198 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.592775 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.030120 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.165306 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.012121 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.591870 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.167002 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.026316 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.289564 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.592775 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.030120 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.165306 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.012121 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.290089 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.591870 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.167002 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.026316 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.289564 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68970.914127 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 80027.027027 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 68466.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 71234.567901 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 98833.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 71215.659341 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73622.340426 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69750 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80557.692308 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 70979.166667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73713.740458 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 78525 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71699.039882 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 78525 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71699.039882 # average overall miss latency +system.l2c.overall_miss_rate::total 0.290089 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76350.274725 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 80056.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77060.240964 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 79035.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86230.769231 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 96750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 70785.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 77206.442831 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 86500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86576.923077 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79666.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 77229.166667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 85032.442748 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78709.677419 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78709.677419 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2617,219 +2616,219 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 360 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 12 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 76 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 5 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 534 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 78 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 360 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 12 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 76 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 665 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 360 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 12 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 76 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 665 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20340000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5009000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 701250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4539000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 390250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 31540750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 230023 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 180018 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 200020 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 170017 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 780078 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5761500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 687000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 888250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 700750 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8037500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 20340000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 10770500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 701250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 749500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 4539000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1324500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 390250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 763250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 39578250 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 20340000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 10770500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 701250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 749500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 4539000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1324500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 390250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 763250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 39578250 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 23217750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5067250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 5227250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 465250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 423750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 83750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 339500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 70000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 34894500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 391522 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 320018 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 303517 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 337019 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1352076 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6964500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 963500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 806000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 776750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9510750 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 23217750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12031750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 5227250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1428750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 423750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 889750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 339500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 846750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 44405250 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 23217750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12031750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5227250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1428750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 423750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 889750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 339500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 846750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 44405250 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.241957 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.242793 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284431 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.284985 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284431 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67689.189189 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59065.074906 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58395.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61354.961832 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.284985 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67563.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66464.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 83750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 67900 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64739.332096 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17796.454545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.777778 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17853.941176 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 17737.842105 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.473684 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74090.425532 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74115.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 64729.166667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72601.145038 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 534 # Transaction distribution -system.membus.trans_dist::ReadResp 533 # Transaction distribution -system.membus.trans_dist::UpgradeReq 274 # Transaction distribution -system.membus.trans_dist::UpgradeResp 78 # Transaction distribution -system.membus.trans_dist::ReadExReq 179 # Transaction distribution +system.membus.trans_dist::ReadReq 539 # Transaction distribution +system.membus.trans_dist::ReadResp 538 # Transaction distribution +system.membus.trans_dist::UpgradeReq 276 # Transaction distribution +system.membus.trans_dist::UpgradeResp 76 # Transaction distribution +system.membus.trans_dist::ReadExReq 171 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 244 # Total snoops (count) -system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1731 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1731 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 240 # Total snoops (count) +system.membus.snoop_fanout::samples 986 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 986 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 987 # Request fanout histogram -system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 986 # Request fanout histogram +system.membus.reqLayer0.occupancy 941000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution +system.membus.respLayer1.occupancy 3702674 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2762 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2761 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 401 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 401 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1229 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 988 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1023 # Total snoops (count) +system.toL2Bus.pkt_size::total 150464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1012 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram @@ -2847,23 +2846,23 @@ system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 1736971 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 994999 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 532769 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 762997 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 438748 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 744992 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 415244 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 747996 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 406758 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 564228327..67fefac90 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,115 +1,1160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262793500 # Number of ticks simulated -final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000260 # Number of seconds simulated +sim_ticks 260037500 # Number of ticks simulated +final_tick 260037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1021127 # Simulator instruction rate (inst/s) -host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 404381057 # Simulator tick rate (ticks/s) -host_mem_usage 299844 # Number of bytes of host memory used -host_seconds 0.65 # Real time elapsed on the host -sim_insts 663567 # Number of instructions simulated -sim_ops 663567 # Number of ops (including micro ops) simulated +host_inst_rate 961598 # Simulator instruction rate (inst/s) +host_op_rate 961579 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379344878 # Simulator tick rate (ticks/s) +host_mem_usage 302744 # Number of bytes of host memory used +host_seconds 0.69 # Real time elapsed on the host +sim_insts 659142 # Number of instructions simulated +sim_ops 659142 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 430 # Transaction distribution -system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 77 # Transaction distribution -system.membus.trans_dist::ReadExReq 208 # Transaction distribution -system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 261 # Total snoops (count) -system.membus.snoop_fanout::samples 915 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 915 # Request fanout histogram -system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.physmem.bw_read::cpu0.inst 70143729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40609527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1722828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3691775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 15013219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5660722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 246118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3691775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140779695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 70143729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1722828 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 15013219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 246118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 87125895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 70143729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40609527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1722828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3691775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 15013219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5660722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 246118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3691775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 140779695 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.numCycles 520075 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 157392 # Number of instructions committed +system.cpu0.committedOps 157392 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108420 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 390 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 25835 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108420 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 313418 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110026 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_mem_refs 73430 # number of memory refs +system.cpu0.num_load_insts 48613 # Number of load instructions +system.cpu0.num_store_insts 24817 # Number of store instructions +system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu0.num_busy_cycles 520074.998000 # Number of busy cycles +system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu0.Branches 26700 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23427 14.88% 14.88% # Class of executed instruction +system.cpu0.op_class::IntAlu 60513 38.43% 53.31% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::MemRead 48697 30.93% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 24817 15.76% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 157454 # Class of executed instruction +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 145.649829 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 72898 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 436.514970 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.649829 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284472 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284472 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 293953 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 293953 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48433 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48433 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24583 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24583 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 73016 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73016 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73016 # number of overall hits +system.cpu0.dcache.overall_hits::total 73016 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses +system.cpu0.dcache.overall_misses::total 353 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4637996 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4637996 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6976000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11613996 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11613996 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11613996 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11613996 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48603 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48603 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 73369 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73369 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73369 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73369 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003498 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003498 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007389 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007389 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004811 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004811 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004811 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004811 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4372004 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4372004 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6701500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6701500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11073504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11073504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11073504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11073504 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003498 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003498 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004811 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004811 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.581030 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 156988 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 336.162741 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.581030 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415197 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.415197 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 157922 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 157922 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 156988 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 156988 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 156988 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 156988 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 156988 # number of overall hits +system.cpu0.icache.overall_hits::total 156988 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18041500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18041500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18041500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18041500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18041500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18041500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 157455 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 157455 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 157455 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 157455 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 157455 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 157455 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002966 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002966 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002966 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002966 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002966 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002966 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38632.762313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38632.762313 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17341000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17341000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17341000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17341000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17341000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17341000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002966 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002966 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002966 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 520075 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 168980 # Number of instructions committed +system.cpu1.committedOps 168980 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110320 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 637 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 33339 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110320 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 270098 # number of times the integer registers were read +system.cpu1.num_int_register_writes 102062 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 53149 # number of memory refs +system.cpu1.num_load_insts 40825 # Number of load instructions +system.cpu1.num_store_insts 12324 # Number of store instructions +system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles +system.cpu1.num_busy_cycles 452347.998260 # Number of busy cycles +system.cpu1.not_idle_fraction 0.869775 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.130225 # Percentage of idle cycles +system.cpu1.Branches 34992 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25772 15.25% 15.25% # Class of executed instruction +system.cpu1.op_class::IntAlu 74368 44.00% 59.25% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::MemRead 56548 33.46% 92.71% # Class of executed instruction +system.cpu1.op_class::MemWrite 12324 7.29% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 169012 # Class of executed instruction +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 25.995164 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26990 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 899.666667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.995164 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050772 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050772 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 212815 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 212815 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 40655 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40655 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 12144 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 12144 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 52799 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 52799 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 52799 # number of overall hits +system.cpu1.dcache.overall_hits::total 52799 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 162 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses +system.cpu1.dcache.overall_misses::total 270 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2619475 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2619475 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1982498 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1982498 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 237000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4601973 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4601973 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4601973 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4601973 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40817 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40817 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 12252 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 12252 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 53069 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 53069 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 53069 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 53069 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003969 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003969 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008815 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008815 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005088 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005088 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005088 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005088 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4232.142857 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2358525 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2358525 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1818502 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1818502 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 153000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4177027 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4177027 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4177027 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4177027 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003969 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008815 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008815 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005088 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005088 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2732.142857 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 65.697365 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 168647 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 460.784153 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.697365 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128315 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.128315 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 169379 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 169379 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 168647 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 168647 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 168647 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 168647 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 168647 # number of overall hits +system.cpu1.icache.overall_hits::total 168647 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses +system.cpu1.icache.overall_misses::total 366 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5333988 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5333988 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5333988 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5333988 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5333988 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5333988 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 169013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 169013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 169013 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 169013 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 169013 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 169013 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002166 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002166 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002166 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14573.737705 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14573.737705 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4778012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4778012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4778012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4778012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4778012 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4778012 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.numCycles 520075 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.committedInsts 164869 # Number of instructions committed +system.cpu2.committedOps 164869 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110069 # Number of integer alu accesses +system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu2.num_func_calls 637 # number of times a function call or return occured +system.cpu2.num_conditional_control_insts 31409 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110069 # number of integer instructions +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_int_register_reads 276820 # number of times the integer registers were read +system.cpu2.num_int_register_writes 105549 # number of times the integer registers were written +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_mem_refs 54829 # number of memory refs +system.cpu2.num_load_insts 40701 # Number of load instructions +system.cpu2.num_store_insts 14128 # Number of store instructions +system.cpu2.num_idle_cycles 67985.001739 # Number of idle cycles +system.cpu2.num_busy_cycles 452089.998261 # Number of busy cycles +system.cpu2.not_idle_fraction 0.869278 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.130722 # Percentage of idle cycles +system.cpu2.Branches 33062 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23842 14.46% 14.46% # Class of executed instruction +system.cpu2.op_class::IntAlu 74244 45.02% 59.48% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::MemRead 52687 31.95% 91.43% # Class of executed instruction +system.cpu2.op_class::MemWrite 14128 8.57% 100.00% # Class of executed instruction +system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::total 164901 # Class of executed instruction +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 27.767003 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30481 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1051.068966 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.767003 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054232 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.054232 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 219531 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 219531 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40534 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40534 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 13949 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 13949 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 54483 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54483 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54483 # number of overall hits +system.cpu2.dcache.overall_hits::total 54483 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 159 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses +system.cpu2.dcache.overall_misses::total 267 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2767480 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2767480 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2022500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2022500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 237000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4789980 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4789980 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4789980 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4789980 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40693 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40693 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14057 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14057 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 54750 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 54750 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 54750 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 54750 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003907 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003907 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007683 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007683 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004877 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004877 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004877 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004877 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4232.142857 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17940 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17940 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17940 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17940 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2514020 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2514020 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1860500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1860500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 153000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4374520 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4374520 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4374520 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4374520 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003907 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003907 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007683 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007683 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004877 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004877 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2732.142857 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 70.145256 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164536 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.551913 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.145256 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137002 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.137002 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 165268 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 165268 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 164536 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 164536 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 164536 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 164536 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 164536 # number of overall hits +system.cpu2.icache.overall_hits::total 164536 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses +system.cpu2.icache.overall_misses::total 366 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7445997 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7445997 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7445997 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7445997 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7445997 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7445997 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 164902 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 164902 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 164902 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 164902 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 164902 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 164902 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 20344.254098 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 20344.254098 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6894003 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6894003 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6894003 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6894003 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6894003 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6894003 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.numCycles 520075 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.committedInsts 167901 # Number of instructions committed +system.cpu3.committedOps 167901 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 110672 # Number of integer alu accesses +system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu3.num_func_calls 637 # number of times a function call or return occured +system.cpu3.num_conditional_control_insts 32621 # number of instructions that are conditional controls +system.cpu3.num_int_insts 110672 # number of integer instructions +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_int_register_reads 274378 # number of times the integer registers were read +system.cpu3.num_int_register_writes 104026 # number of times the integer registers were written +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_mem_refs 54219 # number of memory refs +system.cpu3.num_load_insts 41000 # Number of load instructions +system.cpu3.num_store_insts 13219 # Number of store instructions +system.cpu3.num_idle_cycles 68239.001738 # Number of idle cycles +system.cpu3.num_busy_cycles 451835.998262 # Number of busy cycles +system.cpu3.not_idle_fraction 0.868790 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.131210 # Percentage of idle cycles +system.cpu3.Branches 34277 # Number of branches fetched +system.cpu3.op_class::No_OpClass 25056 14.92% 14.92% # Class of executed instruction +system.cpu3.op_class::IntAlu 74547 44.39% 59.31% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::MemRead 55111 32.82% 92.13% # Class of executed instruction +system.cpu3.op_class::MemWrite 13219 7.87% 100.00% # Class of executed instruction +system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::total 167933 # Class of executed instruction +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 26.810589 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 28657 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 988.172414 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.810589 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052364 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.052364 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 217093 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 217093 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40832 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40832 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 13038 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 13038 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 53870 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 53870 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 53870 # number of overall hits +system.cpu3.dcache.overall_hits::total 53870 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 160 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 160 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses +system.cpu3.dcache.overall_misses::total 268 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2513476 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2513476 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2024000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2024000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 244500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 244500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4537476 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4537476 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4537476 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4537476 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 40992 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 40992 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 13146 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 13146 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 54138 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 54138 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 54138 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 54138 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003903 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003903 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008215 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008215 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.816901 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004950 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004950 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004950 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004950 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4215.517241 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4215.517241 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597 # average overall miss latency +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2256524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2256524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1862000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1862000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 157500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 157500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4118524 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4118524 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4118524 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4118524 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003903 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003903 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008215 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008215 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2715.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2715.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.tags.replacements 281 # number of replacements +system.cpu3.icache.tags.tagsinuse 67.819588 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 167567 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 456.585831 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.819588 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132460 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.132460 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 168301 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 168301 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 167567 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 167567 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 167567 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 167567 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 167567 # number of overall hits +system.cpu3.icache.overall_hits::total 167567 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses +system.cpu3.icache.overall_misses::total 367 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5144490 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5144490 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5144490 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5144490 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5144490 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5144490 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167934 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167934 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167934 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167934 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167934 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167934 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002185 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002185 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002185 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002185 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002185 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002185 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14017.683924 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14017.683924 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14017.683924 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14017.683924 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4586010 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4586010 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4586010 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4586010 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4586010 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4586010 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002185 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002185 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002185 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12495.940054 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.046261 # Cycle average of tags in use +system.l2c.tags.tagsinuse 349.350598 # Cycle average of tags in use system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.790402 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 51.556867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.123938 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.773027 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.843763 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.030296 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.831027 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.890412 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.950361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.237281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.226273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.814088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 47.344433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.154120 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.888026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.845603 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000722 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id @@ -118,10 +1163,10 @@ system.l2c.tags.tag_accesses 15709 # Nu system.l2c.tags.data_accesses 15709 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 302 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 3 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits @@ -131,91 +1176,91 @@ system.l2c.UpgradeReq_hits::cpu0.data 2 # nu system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 302 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 182 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 300 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 354 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits +system.l2c.overall_hits::cpu1.inst 352 # number of overall hits +system.l2c.overall_hits::cpu1.data 9 # number of overall hits +system.l2c.overall_hits::cpu2.inst 302 # number of overall hits +system.l2c.overall_hits::cpu2.data 3 # number of overall hits system.l2c.overall_hits::cpu3.inst 358 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 64 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 64 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses system.l2c.demand_misses::total 592 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 285 # number of overall misses system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 66 # number of overall misses -system.l2c.overall_misses::cpu1.data 23 # number of overall misses -system.l2c.overall_misses::cpu2.inst 12 # number of overall misses -system.l2c.overall_misses::cpu2.data 16 # number of overall misses +system.l2c.overall_misses::cpu1.inst 14 # number of overall misses +system.l2c.overall_misses::cpu1.data 16 # number of overall misses +system.l2c.overall_misses::cpu2.inst 64 # number of overall misses +system.l2c.overall_misses::cpu2.data 23 # number of overall misses system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 592 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3434000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23498000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5172500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 730500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7449500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8624000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3434000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 835000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30947500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8624000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3434000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 835000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30947500 # number of overall miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 14963000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 3465000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 714500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 104000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 3356500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 420000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 103500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23584500 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 744000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 791500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 740000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7473000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14963000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 714500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 848000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 3356500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1211500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 843500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 31057500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14963000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 714500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 848000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 3356500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1211500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 843500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 31057500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) @@ -228,39 +1273,39 @@ system.l2c.ReadReq_accesses::total 1670 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses @@ -276,54 +1321,54 @@ system.l2c.ReadExReq_miss_rate::cpu3.data 1 # m system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.174863 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.174863 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52030.303030 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52217.777778 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52247.474747 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52178.571429 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52461.267606 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52276.182432 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52276.182432 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52501.754386 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51035.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52445.312500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50888.888889 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 51750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52410 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53142.857143 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52766.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52857.142857 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52626.760563 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 53000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52461.993243 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 53000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52461.993243 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -334,104 +1379,104 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 61 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 61 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 61 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3962500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5716000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6602500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22939000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6602500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22939000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11542500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2673000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 283500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2475000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 324000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17419500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1134000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 649996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 648000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 688500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3120496 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4009500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 575500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 611500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 571000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5767500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 11542500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6682500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 283500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 616000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 2475000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 935500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 40500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 611500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 23187000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 11542500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6682500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 283500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 616000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2475000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 935500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 40500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 611500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 23187000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -445,62 +1490,87 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40025.252525 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40253.521127 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40510.465116 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40525.922078 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41107.142857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40785.714286 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution +system.membus.trans_dist::ReadReq 430 # Transaction distribution +system.membus.trans_dist::ReadResp 430 # Transaction distribution +system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 77 # Transaction distribution +system.membus.trans_dist::ReadExReq 208 # Transaction distribution +system.membus.trans_dist::ReadExResp 142 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 261 # Total snoops (count) +system.membus.snoop_fanout::samples 914 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 914 # Request fanout histogram +system.membus.reqLayer0.occupancy 679142 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2961502 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2217 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2217 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution @@ -509,23 +1579,23 @@ system.toL2Bus.trans_dist::ReadExResp 429 # Tr system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4812 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1037 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram +system.toL2Bus.snoops 1029 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2921 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -536,1099 +1606,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 2921 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2921 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1466989 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) -system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525587 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158574 # Number of instructions committed -system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls -system.cpu0.num_int_insts 109208 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 74021 # number of memory refs -system.cpu0.num_load_insts 49007 # Number of load instructions -system.cpu0.num_store_insts 25014 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 525586.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26897 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 49091 30.95% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 25014 15.77% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158636 # Class of executed instruction -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits -system.cpu0.icache.overall_hits::total 158170 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits -system.cpu0.dcache.overall_hits::total 73607 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses -system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525586 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 163471 # Number of instructions committed -system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111731 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read -system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 58020 # number of memory refs -system.cpu1.num_load_insts 41540 # Number of load instructions -system.cpu1.num_store_insts 16480 # Number of store instructions -system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles -system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles -system.cpu1.Branches 31528 # Number of branches fetched -system.cpu1.op_class::No_OpClass 22316 13.65% 13.65% # Class of executed instruction -system.cpu1.op_class::IntAlu 75095 45.93% 59.58% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::MemRead 49612 30.34% 89.92% # Class of executed instruction -system.cpu1.op_class::MemWrite 16480 10.08% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 163503 # Class of executed instruction -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 163870 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits -system.cpu1.icache.overall_hits::total 163138 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses -system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits -system.cpu1.dcache.overall_hits::total 57685 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses -system.cpu1.dcache.overall_misses::total 263 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525586 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 164866 # Number of instructions committed -system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112988 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read -system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59208 # number of memory refs -system.cpu2.num_load_insts 42171 # Number of load instructions -system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles -system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles -system.cpu2.Branches 31596 # Number of branches fetched -system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction -system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::MemRead 49752 30.17% 89.67% # Class of executed instruction -system.cpu2.op_class::MemWrite 17037 10.33% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 164898 # Class of executed instruction -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165265 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits -system.cpu2.icache.overall_hits::total 164533 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses -system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58876 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58876 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58876 # number of overall hits -system.cpu2.dcache.overall_hits::total 58876 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses -system.cpu2.dcache.overall_misses::total 262 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59138 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59138 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003605 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003605 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 525586 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 176656 # Number of instructions committed -system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls -system.cpu3.num_int_insts 108218 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read -system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 46164 # number of memory refs -system.cpu3.num_load_insts 39753 # Number of load instructions -system.cpu3.num_store_insts 6411 # Number of store instructions -system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles -system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles -system.cpu3.Branches 39890 # Number of branches fetched -system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction -system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::MemRead 66272 37.51% 96.37% # Class of executed instruction -system.cpu3.op_class::MemWrite 6411 3.63% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 176688 # Class of executed instruction -system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 177056 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits -system.cpu3.icache.overall_hits::total 176322 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses -system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002077 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002077 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002077 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14025.882834 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14025.882834 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits -system.cpu3.dcache.overall_hits::total 45779 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses -system.cpu3.dcache.overall_misses::total 288 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 503996 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 552488 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 431973 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 550497 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 423980 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 554490 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 428476 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index a27123aa4..4a7304d33 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.001493 # Number of seconds simulated -sim_ticks 1493307500 # Number of ticks simulated -final_tick 1493307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000729 # Number of seconds simulated +sim_ticks 728722500 # Number of ticks simulated +final_tick 728722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 295462472 # Simulator tick rate (ticks/s) -host_mem_usage 222068 # Number of bytes of host memory used -host_seconds 5.05 # Real time elapsed on the host +host_tick_rate 162031375 # Simulator tick rate (ticks/s) +host_mem_usage 277108 # Number of bytes of host memory used +host_seconds 4.50 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 74794 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 78736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 78807 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 78188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77250 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 74477 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78325 # Number of bytes read from this memory -system.physmem.bytes_read::total 619989 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 384000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5518 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5402 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5514 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5530 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5340 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5402 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory -system.physmem.bytes_written::total 427483 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10974 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10915 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6000 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5518 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5402 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5400 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5514 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5530 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5340 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5402 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49483 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 50086134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 52725912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 52773458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 52358941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 51730806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 49873854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 53178599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 52450684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 415178388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 257147306 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 3695153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 3617473 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 3616134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 3692475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 3703189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 3575955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 3617473 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 3600732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 286265890 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 257147306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 53781288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 56343385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 56389592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 56051416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 55433995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 53449809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 56796072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 56051416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 701444277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 79470 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78418 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 80729 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80022 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 80096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 78976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78470 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 78262 # Number of bytes read from this memory +system.physmem.bytes_read::total 634443 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 400000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5381 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5473 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5390 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5494 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5433 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5395 # Number of bytes written to this memory +system.physmem.bytes_written::total 443379 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87540 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5381 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5473 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5390 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5494 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5433 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5395 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49629 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 109053858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 107610236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 110781539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 109811348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 109912896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 108375959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 107681593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 107396162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 870623591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 548905791 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7384155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 7470608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7510403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 7396506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 7367688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7539221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7455513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7403367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 608433251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 548905791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 116438013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 115080844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 118291942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 117207853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 117280583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 115915180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 115137106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 114799529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479056843 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99767 # number of read accesses completed -system.cpu0.num_writes 55259 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22696 # number of replacements -system.cpu0.l1c.tags.tagsinuse 395.365301 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13357 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 23083 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.578651 # Average number of references to valid blocks. +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 54791 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22240 # number of replacements +system.cpu0.l1c.tags.tagsinuse 394.087405 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13441 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.593789 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 395.365301 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.772198 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.772198 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 272 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 339665 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 339665 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8708 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8708 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1150 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1150 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9858 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9858 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9858 # number of overall hits -system.cpu0.l1c.overall_hits::total 9858 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36982 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36982 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23775 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23775 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60757 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60757 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60757 # number of overall misses -system.cpu0.l1c.overall_misses::total 60757 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 2501825237 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 2501825237 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1853114266 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1853114266 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 4354939503 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 4354939503 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 4354939503 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 4354939503 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45690 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45690 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24925 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24925 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70615 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70615 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70615 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70615 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809411 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.809411 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953862 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953862 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860398 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860398 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860398 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860398 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67649.809015 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 67649.809015 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 77943.817708 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 77943.817708 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 71677.987771 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 71677.987771 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 71677.987771 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 71677.987771 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 2197094 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 394.087405 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.769702 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.769702 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337290 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337290 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8682 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8682 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1111 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1111 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9793 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9793 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9793 # number of overall hits +system.cpu0.l1c.overall_hits::total 9793 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36727 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36727 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23639 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23639 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60366 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60366 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60366 # number of overall misses +system.cpu0.l1c.overall_misses::total 60366 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1016702315 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1016702315 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 918792240 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 918792240 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1935494555 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1935494555 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1935494555 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1935494555 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45409 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24750 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24750 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70159 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70159 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70159 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70159 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808804 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808804 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955111 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955111 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860417 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860417 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860417 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860417 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27682.694339 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 27682.694339 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38867.644147 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38867.644147 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 32062.660355 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 32062.660355 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 32062.660355 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 32062.660355 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1074391 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 60506 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61970 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.312002 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.337276 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9747 # number of writebacks -system.cpu0.l1c.writebacks::total 9747 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36982 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36982 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23775 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23775 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60757 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60757 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60757 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60757 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2423727133 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2423727133 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1803343082 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1803343082 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 4227070215 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 4227070215 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4227070215 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 4227070215 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1077807594 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1077807594 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4091615147 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4091615147 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5169422741 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5169422741 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953862 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953862 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860398 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860398 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65538.022092 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65538.022092 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 75850.392513 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 75850.392513 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9656 # number of writebacks +system.cpu0.l1c.writebacks::total 9656 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36727 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36727 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23639 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23639 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60366 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60366 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60366 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60366 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 960514497 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 960514497 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 882874166 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 882874166 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1843388663 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1843388663 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1843388663 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1843388663 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 755586835 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 755586835 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1939842714 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1939842714 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2695429549 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2695429549 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808804 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808804 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955111 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955111 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860417 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860417 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26152.816647 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26152.816647 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37348.202800 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37348.202800 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 54988 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22397 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.796271 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13630 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22804 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.597702 # Average number of references to valid blocks. +system.cpu1.num_reads 99410 # number of read accesses completed +system.cpu1.num_writes 55132 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22295 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.820804 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13496 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22679 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.595088 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.796271 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.773040 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.773040 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 269 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338465 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338465 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8882 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8882 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1141 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1141 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 10023 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 10023 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 10023 # number of overall hits -system.cpu1.l1c.overall_hits::total 10023 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36639 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36639 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23767 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23767 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60406 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60406 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60406 # number of overall misses -system.cpu1.l1c.overall_misses::total 60406 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 2485954076 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 2485954076 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1862028208 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1862028208 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 4347982284 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 4347982284 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 4347982284 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 4347982284 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24908 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70429 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70429 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70429 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70429 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804881 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.804881 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954191 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954191 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857686 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857686 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857686 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857686 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67849.943394 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 67849.943394 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78345.109101 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 78345.109101 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 71979.311393 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 71979.311393 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 71979.311393 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 71979.311393 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 2202198 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.820804 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.769181 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.769181 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338268 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338268 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8726 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8726 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1171 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1171 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9897 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9897 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9897 # number of overall hits +system.cpu1.l1c.overall_hits::total 9897 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36573 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36573 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23897 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23897 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60470 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60470 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60470 # number of overall misses +system.cpu1.l1c.overall_misses::total 60470 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1020722242 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1020722242 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 921634198 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 921634198 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1942356440 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1942356440 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1942356440 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1942356440 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45299 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25068 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70367 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70367 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70367 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70367 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807369 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807369 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953287 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953287 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859352 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859352 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859352 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859352 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27909.174582 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 27909.174582 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38566.941373 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38566.941373 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 32120.992889 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 32120.992889 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 32120.992889 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 32120.992889 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1066797 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 60277 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61607 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.534632 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.316165 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks -system.cpu1.l1c.writebacks::total 9809 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36639 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36639 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23767 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23767 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60406 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60406 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60406 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60406 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2408616840 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2408616840 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1812196150 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1812196150 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4220812990 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 4220812990 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4220812990 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 4220812990 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1084723149 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1084723149 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4036922188 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 4036922188 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5121645337 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5121645337 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804881 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804881 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954191 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954191 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857686 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857686 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65739.153361 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65739.153361 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76248.417975 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76248.417975 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9694 # number of writebacks +system.cpu1.l1c.writebacks::total 9694 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36573 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36573 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23897 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23897 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60470 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60470 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60470 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60470 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 964784026 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 964784026 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 885327122 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 885327122 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1850111148 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1850111148 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1850111148 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1850111148 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740106955 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740106955 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1954561172 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1954561172 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2694668127 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2694668127 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807369 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807369 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953287 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953287 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859352 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859352 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26379.679709 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26379.679709 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37047.626146 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37047.626146 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99645 # number of read accesses completed -system.cpu2.num_writes 55347 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22638 # number of replacements -system.cpu2.l1c.tags.tagsinuse 395.541236 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13666 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.593323 # Average number of references to valid blocks. +system.cpu2.num_reads 99274 # number of read accesses completed +system.cpu2.num_writes 54884 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22456 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.843880 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13581 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22857 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.594172 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 395.541236 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.772541 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.772541 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 271 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339287 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339287 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8844 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8844 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1130 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9974 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9974 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9974 # number of overall hits -system.cpu2.l1c.overall_hits::total 9974 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36761 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36761 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23865 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23865 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60626 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60626 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60626 # number of overall misses -system.cpu2.l1c.overall_misses::total 60626 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 2497854261 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 2497854261 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1869962350 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1869962350 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 4367816611 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 4367816611 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 4367816611 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 4367816611 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45605 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45605 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70600 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70600 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70600 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70600 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806074 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806074 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954791 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954791 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858725 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858725 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858725 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858725 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67948.485106 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 67948.485106 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78355.849571 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 78355.849571 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 72045.271187 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 72045.271187 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 72045.271187 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 72045.271187 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 2198319 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.843880 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.769226 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.769226 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 373 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337451 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337451 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8813 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8813 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1134 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9947 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9947 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9947 # number of overall hits +system.cpu2.l1c.overall_hits::total 9947 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36457 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36457 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23816 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23816 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60273 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60273 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60273 # number of overall misses +system.cpu2.l1c.overall_misses::total 60273 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1014308258 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1014308258 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 924910230 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 924910230 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1939218488 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1939218488 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1939218488 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1939218488 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45270 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45270 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24950 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70220 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70220 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70220 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70220 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805324 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805324 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954549 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954549 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858345 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858345 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858345 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858345 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27822.043997 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 27822.043997 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38835.666359 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 38835.666359 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 32173.916812 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 32173.916812 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 32173.916812 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 32173.916812 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1061117 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60200 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61178 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.516927 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.344748 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9871 # number of writebacks -system.cpu2.l1c.writebacks::total 9871 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36761 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36761 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23865 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23865 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60626 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60626 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60626 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60626 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2420242117 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2420242117 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1819999216 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1819999216 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4240241333 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 4240241333 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4240241333 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 4240241333 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1065167222 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1065167222 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3984850744 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3984850744 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 5050017966 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5050017966 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806074 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806074 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954791 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954791 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858725 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858725 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65837.221974 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65837.221974 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76262.275969 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76262.275969 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9940 # number of writebacks +system.cpu2.l1c.writebacks::total 9940 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36457 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36457 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23816 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23816 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60273 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60273 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60273 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60273 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958559384 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958559384 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 888663772 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 888663772 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847223156 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1847223156 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847223156 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1847223156 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 735013046 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 735013046 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1939097223 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1939097223 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2674110269 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2674110269 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805324 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805324 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954549 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954549 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858345 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858345 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26292.876101 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26292.876101 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37313.729090 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37313.729090 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98252 # number of read accesses completed -system.cpu3.num_writes 55235 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22381 # number of replacements -system.cpu3.l1c.tags.tagsinuse 396.107709 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13213 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22778 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.580077 # Average number of references to valid blocks. +system.cpu3.num_reads 99869 # number of read accesses completed +system.cpu3.num_writes 54874 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22370 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.431339 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13240 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22771 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.581441 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 396.107709 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.773648 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.773648 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 335638 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 335638 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8470 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8470 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1156 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1156 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9626 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9626 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9626 # number of overall hits -system.cpu3.l1c.overall_hits::total 9626 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36183 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36183 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23969 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23969 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60152 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60152 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60152 # number of overall misses -system.cpu3.l1c.overall_misses::total 60152 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 2454128819 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 2454128819 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1887224651 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1887224651 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 4341353470 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 4341353470 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 4341353470 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 4341353470 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44653 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44653 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25125 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25125 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69778 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69778 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69778 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69778 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810315 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.810315 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953990 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953990 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.862048 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.862048 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.862048 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.862048 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67825.465522 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 67825.465522 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78736.061204 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 78736.061204 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 72173.052766 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 72173.052766 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 72173.052766 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 72173.052766 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 2184377 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.431339 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768421 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768421 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336829 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336829 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8648 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8648 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1128 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1128 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9776 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9776 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9776 # number of overall hits +system.cpu3.l1c.overall_hits::total 9776 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36458 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36458 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23788 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23788 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60246 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60246 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60246 # number of overall misses +system.cpu3.l1c.overall_misses::total 60246 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1012578921 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1012578921 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 920459168 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 920459168 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1933038089 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1933038089 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1933038089 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1933038089 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45106 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24916 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24916 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70022 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70022 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70022 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70022 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808274 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808274 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954728 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954728 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860387 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860387 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860387 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860387 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27773.847194 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 27773.847194 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38694.264671 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38694.264671 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 32085.749909 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 32085.749909 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 32085.749909 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 32085.749909 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1072737 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 59819 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61848 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.516441 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.344732 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9931 # number of writebacks -system.cpu3.l1c.writebacks::total 9931 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36183 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36183 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23969 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60152 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60152 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60152 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60152 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2377731501 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2377731501 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1837004571 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1837004571 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4214736072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 4214736072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4214736072 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 4214736072 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1072192160 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1072192160 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 4016794612 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 4016794612 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 5088986772 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 5088986772 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.810315 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.810315 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953990 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953990 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.862048 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.862048 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.862048 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.862048 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.050825 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.050825 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76640.851558 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76640.851558 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9757 # number of writebacks +system.cpu3.l1c.writebacks::total 9757 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36458 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23788 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60246 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60246 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60246 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60246 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 956791627 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 956791627 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 884289164 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 884289164 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1841080791 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1841080791 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1841080791 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1841080791 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 756050699 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 756050699 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1926314708 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1926314708 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2682365407 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2682365407 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808274 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808274 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954728 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954728 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860387 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860387 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26243.667426 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26243.667426 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37173.749958 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37173.749958 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99562 # number of read accesses completed -system.cpu4.num_writes 54813 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22626 # number of replacements -system.cpu4.l1c.tags.tagsinuse 395.713168 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13359 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 23019 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.580347 # Average number of references to valid blocks. +system.cpu4.num_reads 98774 # number of read accesses completed +system.cpu4.num_writes 54829 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22505 # number of replacements +system.cpu4.l1c.tags.tagsinuse 395.050000 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13373 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22916 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.583566 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 395.713168 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.772877 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.772877 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337886 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337886 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8660 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1130 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9790 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9790 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9790 # number of overall hits -system.cpu4.l1c.overall_hits::total 9790 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36748 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36748 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23725 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23725 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60473 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60473 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60473 # number of overall misses -system.cpu4.l1c.overall_misses::total 60473 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 2479360793 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 2479360793 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1851125976 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1851125976 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 4330486769 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 4330486769 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 4330486769 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 4330486769 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45408 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45408 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24855 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24855 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70263 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70263 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70263 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70263 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809285 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.809285 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954536 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954536 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860666 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860666 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860666 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860666 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67469.271607 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 67469.271607 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78024.277176 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 78024.277176 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 71610.251997 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 71610.251997 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 71610.251997 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 71610.251997 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 2193235 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 395.050000 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.771582 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.771582 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337873 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337873 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8531 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8531 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1209 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1209 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9740 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9740 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9740 # number of overall hits +system.cpu4.l1c.overall_hits::total 9740 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36518 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36518 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24001 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24001 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60519 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60519 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60519 # number of overall misses +system.cpu4.l1c.overall_misses::total 60519 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1017641988 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1017641988 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 934552595 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 934552595 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1952194583 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1952194583 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1952194583 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1952194583 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25210 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25210 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70259 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70259 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70259 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70259 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.810628 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.810628 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952043 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952043 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.861370 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.861370 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.861370 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.861370 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27866.859850 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 27866.859850 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38938.069039 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 38938.069039 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 32257.548588 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 32257.548588 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 32257.548588 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 32257.548588 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1063629 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 60223 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61473 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.418561 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.302377 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9708 # number of writebacks -system.cpu4.l1c.writebacks::total 9708 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36748 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36748 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23725 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23725 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60473 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60473 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2401684855 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2401684855 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1801504708 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1801504708 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4203189563 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 4203189563 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4203189563 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 4203189563 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1091799507 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1091799507 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 4121360584 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 4121360584 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5213160091 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5213160091 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809285 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809285 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954536 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954536 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860666 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860666 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65355.525607 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65355.525607 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 75932.759031 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75932.759031 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9914 # number of writebacks +system.cpu4.l1c.writebacks::total 9914 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36518 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36518 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24001 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24001 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60519 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60519 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60519 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60519 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 961775196 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 961775196 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 898026173 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 898026173 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1859801369 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1859801369 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1859801369 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1859801369 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 728267014 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 728267014 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1921671690 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1921671690 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2649938704 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2649938704 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.810628 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.810628 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952043 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952043 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861370 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.861370 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861370 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.861370 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26337.017252 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26337.017252 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37416.198200 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37416.198200 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98672 # number of read accesses completed -system.cpu5.num_writes 54809 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22472 # number of replacements -system.cpu5.l1c.tags.tagsinuse 396.252013 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13351 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22867 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.583854 # Average number of references to valid blocks. +system.cpu5.num_reads 99305 # number of read accesses completed +system.cpu5.num_writes 54996 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22529 # number of replacements +system.cpu5.l1c.tags.tagsinuse 394.380527 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13364 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.582792 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 396.252013 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.773930 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.773930 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 336301 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 336301 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8563 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8563 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1084 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1084 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9647 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9647 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9647 # number of overall hits -system.cpu5.l1c.overall_hits::total 9647 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36411 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36411 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23882 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23882 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60293 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60293 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60293 # number of overall misses -system.cpu5.l1c.overall_misses::total 60293 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 2486246489 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 2486246489 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1881159650 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1881159650 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 4367406139 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 4367406139 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 4367406139 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 4367406139 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44974 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44974 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24966 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24966 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69940 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69940 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69940 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69940 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.809601 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.809601 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956581 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.956581 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.862067 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.862067 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.862067 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.862067 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 68282.840048 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 68282.840048 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78768.932669 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 78768.932669 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 72436.371370 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 72436.371370 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 72436.371370 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 72436.371370 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 2200429 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 394.380527 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.770274 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.770274 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337468 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337468 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8640 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8640 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1161 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1161 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9801 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9801 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9801 # number of overall hits +system.cpu5.l1c.overall_hits::total 9801 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36580 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36580 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23798 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23798 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60378 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60378 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60378 # number of overall misses +system.cpu5.l1c.overall_misses::total 60378 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1015127570 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1015127570 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 927119253 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 927119253 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1942246823 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1942246823 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1942246823 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1942246823 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45220 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45220 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24959 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70179 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70179 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70179 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70179 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808934 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808934 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953484 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953484 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860343 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860343 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860343 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860343 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27750.890377 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 27750.890377 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38957.864232 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 38957.864232 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 32168.121220 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 32168.121220 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 32168.121220 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 32168.121220 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1066593 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 60083 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61522 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.623155 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.336774 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9941 # number of writebacks -system.cpu5.l1c.writebacks::total 9941 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36411 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36411 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23882 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23882 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60293 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60293 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60293 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60293 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2409268523 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2409268523 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1831238342 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1831238342 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4240506865 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 4240506865 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4240506865 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 4240506865 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1068031665 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1068031665 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 3938248323 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 3938248323 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 5006279988 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 5006279988 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.809601 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.809601 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956581 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956581 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.862067 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.862067 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.862067 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.862067 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 66168.699651 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 66168.699651 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76678.600703 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76678.600703 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9775 # number of writebacks +system.cpu5.l1c.writebacks::total 9775 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36580 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36580 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23798 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23798 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60378 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60378 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 959195658 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 959195658 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890981649 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890981649 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1850177307 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1850177307 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1850177307 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1850177307 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 738489342 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 738489342 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1963680665 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1963680665 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2702170007 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2702170007 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808934 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808934 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953484 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953484 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860343 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860343 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860343 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860343 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26221.860525 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26221.860525 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37439.349903 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37439.349903 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30643.236063 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99484 # number of read accesses completed -system.cpu6.num_writes 54995 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22115 # number of replacements -system.cpu6.l1c.tags.tagsinuse 396.164371 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13666 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22491 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.607621 # Average number of references to valid blocks. +system.cpu6.num_reads 99342 # number of read accesses completed +system.cpu6.num_writes 54737 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22276 # number of replacements +system.cpu6.l1c.tags.tagsinuse 393.125800 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13636 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.601155 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 396.164371 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.773759 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.773759 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338129 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338129 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8797 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8797 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1207 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1207 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 10004 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 10004 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 10004 # number of overall hits -system.cpu6.l1c.overall_hits::total 10004 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36456 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36456 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23912 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23912 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60368 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60368 # number of overall misses -system.cpu6.l1c.overall_misses::total 60368 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 2466938162 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 2466938162 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1877191258 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1877191258 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 4344129420 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 4344129420 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 4344129420 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 4344129420 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45253 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45253 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25119 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805604 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805604 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951949 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951949 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.857841 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.857841 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.857841 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.857841 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67668.920397 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 67668.920397 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78504.150970 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 78504.150970 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 71960.797442 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 71960.797442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 71960.797442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 71960.797442 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 2202006 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 393.125800 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.767824 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.767824 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337855 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337855 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8799 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8799 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1154 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1154 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9953 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9953 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9953 # number of overall hits +system.cpu6.l1c.overall_hits::total 9953 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36552 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36552 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23805 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23805 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60357 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60357 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60357 # number of overall misses +system.cpu6.l1c.overall_misses::total 60357 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1017275565 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1017275565 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 923819144 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 923819144 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1941094709 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1941094709 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1941094709 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1941094709 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45351 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45351 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24959 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70310 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70310 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805980 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805980 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953764 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953764 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858441 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858441 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858441 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858441 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27830.913903 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 27830.913903 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38807.777526 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 38807.777526 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 32160.225144 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 32160.225144 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 32160.225144 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 32160.225144 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1069531 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 60316 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61695 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.507825 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.335781 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9723 # number of writebacks -system.cpu6.l1c.writebacks::total 9723 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36456 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23912 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23912 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60368 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60368 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 2389944958 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2389944958 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1827130108 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1827130108 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 4217075066 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 4217075066 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4217075066 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 4217075066 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1090860454 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1090860454 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 4034817264 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 4034817264 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 5125677718 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 5125677718 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805604 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805604 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951949 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951949 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857841 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.857841 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857841 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.857841 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65556.971637 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 65556.971637 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76410.593342 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76410.593342 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 69856.133481 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9809 # number of writebacks +system.cpu6.l1c.writebacks::total 9809 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36552 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36552 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23805 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23805 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60357 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60357 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60357 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60357 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 961362717 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 961362717 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 887609672 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 887609672 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1848972389 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1848972389 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1848972389 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1848972389 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 744037855 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 744037855 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1951627727 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1951627727 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2695665582 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2695665582 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805980 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805980 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953764 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953764 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858441 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858441 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858441 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858441 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26301.234324 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26301.234324 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37286.690695 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37286.690695 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30633.934573 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98571 # number of read accesses completed -system.cpu7.num_writes 54904 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22064 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.954913 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13425 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22470 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.597463 # Average number of references to valid blocks. +system.cpu7.num_reads 99062 # number of read accesses completed +system.cpu7.num_writes 54686 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22200 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.753023 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13454 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22591 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.595547 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.954913 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.771396 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.771396 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 334895 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 334895 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8604 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8604 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1157 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1157 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9761 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9761 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9761 # number of overall hits -system.cpu7.l1c.overall_hits::total 9761 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35973 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35973 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23939 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23939 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59912 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59912 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59912 # number of overall misses -system.cpu7.l1c.overall_misses::total 59912 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 2452832630 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 2452832630 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1890055104 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1890055104 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 4342887734 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 4342887734 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 4342887734 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 4342887734 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44577 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44577 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25096 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25096 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69673 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69673 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69673 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69673 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806986 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806986 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953897 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953897 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859903 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859903 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859903 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859903 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 68185.378756 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 68185.378756 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78952.968127 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 78952.968127 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 72487.777641 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 72487.777641 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 72487.777641 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 72487.777641 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 2195658 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 394.753023 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.771002 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.771002 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337139 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337139 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8690 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8690 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1182 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9872 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9872 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9872 # number of overall hits +system.cpu7.l1c.overall_hits::total 9872 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36466 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36466 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60256 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60256 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60256 # number of overall misses +system.cpu7.l1c.overall_misses::total 60256 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1009807130 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1009807130 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 916976125 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 916976125 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1926783255 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1926783255 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1926783255 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1926783255 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24972 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70128 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70128 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70128 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70128 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807556 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807556 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952667 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.952667 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859229 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859229 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859229 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859229 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27691.743816 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 27691.743816 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38544.603825 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 38544.603825 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 31976.620668 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 31976.620668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 31976.620668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 31976.620668 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1063264 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 59807 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61445 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 36.712392 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.304321 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9796 # number of writebacks -system.cpu7.l1c.writebacks::total 9796 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35973 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35973 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23939 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59912 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59912 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59912 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59912 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2376889288 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2376889288 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1839857154 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1839857154 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4216746442 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 4216746442 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4216746442 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 4216746442 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1084884512 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1084884512 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 4029557689 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 4029557689 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5114442201 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5114442201 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806986 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806986 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953897 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953897 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859903 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859903 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859903 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859903 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 66074.258138 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 66074.258138 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76856.057229 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76856.057229 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 70382.334791 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9819 # number of writebacks +system.cpu7.l1c.writebacks::total 9819 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36466 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36466 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60256 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60256 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60256 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60256 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 953998318 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 953998318 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 880753723 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 880753723 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1834752041 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1834752041 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1834752041 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1834752041 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 752742732 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 752742732 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1947143716 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1947143716 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2699886448 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2699886448 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807556 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807556 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952667 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952667 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859229 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859229 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859229 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859229 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26161.309658 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26161.309658 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37022.014418 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37022.014418 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,566 +1037,565 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12730 # number of replacements -system.l2c.tags.tagsinuse 780.951688 # Cycle average of tags in use -system.l2c.tags.total_refs 149721 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13527 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.068308 # Average number of references to valid blocks. +system.l2c.tags.replacements 13121 # number of replacements +system.l2c.tags.tagsinuse 779.163229 # Cycle average of tags in use +system.l2c.tags.total_refs 150276 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13897 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.813557 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.352338 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 5.728717 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.680211 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.211499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 5.648633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.142733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 5.860524 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.858945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.468088 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713235 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006524 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.005516 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.005999 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.005723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006698 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.762648 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 424 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.778320 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1954074 # Number of tag accesses -system.l2c.tags.data_accesses 1954074 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10705 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10659 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10665 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10689 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10651 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10616 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85337 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 75478 # number of Writeback hits -system.l2c.Writeback_hits::total 75478 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 365 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 341 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 333 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 338 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2772 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1956 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1860 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1936 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1874 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1916 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1911 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15192 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12601 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12589 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12550 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12527 # number of demand (read+write) hits -system.l2c.demand_hits::total 100529 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12661 # number of overall hits -system.l2c.overall_hits::cpu1 12519 # number of overall hits -system.l2c.overall_hits::cpu2 12601 # number of overall hits -system.l2c.overall_hits::cpu3 12563 # number of overall hits -system.l2c.overall_hits::cpu4 12589 # number of overall hits -system.l2c.overall_hits::cpu5 12519 # number of overall hits -system.l2c.overall_hits::cpu6 12550 # number of overall hits -system.l2c.overall_hits::cpu7 12527 # number of overall hits -system.l2c.overall_hits::total 100529 # number of overall hits -system.l2c.ReadReq_misses::cpu0 637 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 698 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 718 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 649 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 657 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 655 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 700 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 686 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5400 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1869 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1879 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1945 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1927 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1931 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2008 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1996 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1999 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15554 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4360 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4327 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4376 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4482 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4415 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4364 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4427 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4401 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35152 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 4997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5025 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5094 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5131 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5072 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5019 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5127 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5087 # number of demand (read+write) misses -system.l2c.demand_misses::total 40552 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 4997 # number of overall misses -system.l2c.overall_misses::cpu1 5025 # number of overall misses -system.l2c.overall_misses::cpu2 5094 # number of overall misses -system.l2c.overall_misses::cpu3 5131 # number of overall misses -system.l2c.overall_misses::cpu4 5072 # number of overall misses -system.l2c.overall_misses::cpu5 5019 # number of overall misses -system.l2c.overall_misses::cpu6 5127 # number of overall misses -system.l2c.overall_misses::cpu7 5087 # number of overall misses -system.l2c.overall_misses::total 40552 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 37351962 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 41387952 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 42368449 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 38023954 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 38587461 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 38640955 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 40955466 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 40550959 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 317867158 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 53532000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 54034500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 55090000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 53743000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 53806000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57327000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 56366500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 57375499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 441274499 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 232668482 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 231079974 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 233454479 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 239997471 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 235674978 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 232806977 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 236584974 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 235413970 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1877681305 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 270020444 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 272467926 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 275822928 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 278021425 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 274262439 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 271447932 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 277540440 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 275964929 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2195548463 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 270020444 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 272467926 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 275822928 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 278021425 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 274262439 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 271447932 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 277540440 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 275964929 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2195548463 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11383 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11338 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11334 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11351 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11302 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 90737 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 75478 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 75478 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2234 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2220 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2276 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2264 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2348 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2334 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2342 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18326 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6316 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6187 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6331 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6204 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6326 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50344 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17658 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17544 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17695 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17694 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17661 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17538 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17677 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17614 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 141081 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17658 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17544 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17695 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17694 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17661 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17538 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17677 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17614 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 141081 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.056163 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.061460 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.063077 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.057241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.057988 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.057791 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.061669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.060697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.059513 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.836616 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.846396 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.842721 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.846661 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852915 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.855196 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.855184 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.853544 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.848739 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.690310 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.699370 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.693283 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.705160 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.697362 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.703417 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.699810 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.697243 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.698236 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.282988 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.286423 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.287878 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.289985 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.287186 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.286179 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.290038 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.288804 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.287438 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.282988 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.286423 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.287878 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.289985 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.287186 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.286179 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.290038 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288804 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.287438 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 58637.302983 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 59295.060172 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 59008.981894 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 58588.526965 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 58732.817352 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 58993.824427 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 58507.808571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59112.185131 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58864.288519 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28642.054575 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28757.051623 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28323.907455 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27889.465490 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 27864.319006 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28549.302789 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28239.729459 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28702.100550 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28370.483413 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53364.330734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53404.200139 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53348.829753 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53546.959170 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53380.515968 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53347.153300 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53441.376553 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53491.017950 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53416.058972 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54036.510706 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54222.472836 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54146.628975 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54184.647242 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54073.824724 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54084.066946 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54133.107080 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54249.052290 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54141.558074 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54036.510706 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54222.472836 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54146.628975 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54184.647242 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54073.824724 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54084.066946 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54133.107080 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54249.052290 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54141.558074 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 6543 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 725.457797 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.718013 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.568954 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.219418 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.731947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.474998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.998802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.991847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.001453 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.708455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006561 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006323 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006835 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.760902 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 566 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1961425 # Number of tag accesses +system.l2c.tags.data_accesses 1961425 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10766 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10671 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10889 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10673 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85829 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 75598 # number of Writeback hits +system.l2c.Writeback_hits::total 75598 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 323 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 342 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 356 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 330 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2745 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1821 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1892 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1922 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1886 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1863 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15171 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12615 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12658 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12630 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12554 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12639 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12593 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12775 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12536 # number of demand (read+write) hits +system.l2c.demand_hits::total 101000 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12615 # number of overall hits +system.l2c.overall_hits::cpu1 12658 # number of overall hits +system.l2c.overall_hits::cpu2 12630 # number of overall hits +system.l2c.overall_hits::cpu3 12554 # number of overall hits +system.l2c.overall_hits::cpu4 12639 # number of overall hits +system.l2c.overall_hits::cpu5 12593 # number of overall hits +system.l2c.overall_hits::cpu6 12775 # number of overall hits +system.l2c.overall_hits::cpu7 12536 # number of overall hits +system.l2c.overall_hits::total 101000 # number of overall hits +system.l2c.ReadReq_misses::cpu0 705 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 721 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 716 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 685 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 694 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 690 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 691 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 715 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5617 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1952 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1970 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1832 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1968 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1954 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1963 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1919 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15493 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4418 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4338 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4348 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4457 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4447 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4501 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4407 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35289 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5059 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5064 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5142 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5141 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5191 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5098 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5088 # number of demand (read+write) misses +system.l2c.demand_misses::total 40906 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5123 # number of overall misses +system.l2c.overall_misses::cpu1 5059 # number of overall misses +system.l2c.overall_misses::cpu2 5064 # number of overall misses +system.l2c.overall_misses::cpu3 5142 # number of overall misses +system.l2c.overall_misses::cpu4 5141 # number of overall misses +system.l2c.overall_misses::cpu5 5191 # number of overall misses +system.l2c.overall_misses::cpu6 5098 # number of overall misses +system.l2c.overall_misses::cpu7 5088 # number of overall misses +system.l2c.overall_misses::total 40906 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 42571447 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 44584934 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 43709432 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 42098938 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 42802932 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 42467936 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 42434429 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 44394419 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 345064467 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 57799000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 58024000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 57179999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53990500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 56201500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 57084499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 56659000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 56222499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 453160997 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 241579958 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 237098460 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 238347956 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 243950461 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 243322462 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 246152957 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 241076464 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 238492966 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1930021684 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 284151405 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 281683394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 282057388 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 286049399 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 286125394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 288620893 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 283510893 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 282887385 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2275086151 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 284151405 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 281683394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 282057388 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 286049399 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 286125394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 288620893 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 283510893 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 282887385 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2275086151 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11499 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11487 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11361 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11388 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91446 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 75598 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 75598 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2258 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2312 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2166 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2324 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2284 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2324 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2265 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18238 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6239 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6230 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6295 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6350 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6394 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6423 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6293 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6236 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50460 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17738 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17694 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17780 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17784 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17873 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17624 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141906 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17738 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17694 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17780 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17784 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17873 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17624 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141906 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.061310 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.062767 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.062813 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060374 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.060952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.060734 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.059672 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.062785 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.061424 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.846855 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.856953 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.852076 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.845799 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.846816 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.855517 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.844664 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.847241 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849490 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.708126 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.696308 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.690707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.701890 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.695496 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.700763 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.700302 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.701251 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.699346 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.288815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.285545 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286199 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.290574 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.289145 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.291892 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.285235 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.288697 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.288261 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.288815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.285545 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.286199 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.290574 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.289145 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291892 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.285235 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.288697 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.288261 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60385.031206 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61837.633842 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61046.692737 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61458.303650 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61675.694524 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61547.733333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61410.172214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 62090.096503 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61432.164323 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29610.143443 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29986.563307 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29025.380203 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29470.796943 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28557.672764 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29214.175537 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28863.474274 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29297.810839 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29249.402763 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54680.841557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54656.168741 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54817.837167 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54734.229527 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54716.092197 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54688.504110 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54703.077831 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54537.609421 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54691.878036 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55465.821784 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55679.658826 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55698.536335 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55629.988137 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55655.591130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55600.249085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55612.179874 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55598.935731 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55617.419229 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55465.821784 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55679.658826 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55698.536335 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55629.988137 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55655.591130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55600.249085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55612.179874 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55598.935731 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55617.419229 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 10446 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 914 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1464 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.158643 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.135246 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6000 # number of writebacks -system.l2c.writebacks::total 6000 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 14 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 1 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 6250 # number of writebacks +system.l2c.writebacks::total 6250 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 1 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 15 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 35 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 35 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 635 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 695 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 716 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 643 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 657 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 651 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 698 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 684 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5379 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1869 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1879 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1943 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1926 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1931 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2008 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1995 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1999 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15550 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4360 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4323 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4372 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4482 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4414 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4363 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4425 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4399 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35138 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 4995 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5018 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5088 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5125 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5071 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5014 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5123 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5083 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40517 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 4995 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5018 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5088 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5125 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5071 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5014 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5123 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5083 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40517 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 29596962 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 32869452 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 33629449 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 29976455 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 30615961 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 30583955 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 32395466 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 32146959 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 251814659 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76123000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76358500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 79146000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78403000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 78530000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81677500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 81182000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 81450499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 632870499 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 179654482 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 178405975 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 180144979 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 185516471 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 181991978 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 179667478 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182702975 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 181859470 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1449943808 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 209251444 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 211275427 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 213774428 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 215492926 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 212607939 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 210251433 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 215098441 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 214006429 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1701758467 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 209251444 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 211275427 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 213774428 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 215492926 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 212607939 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 210251433 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 215098441 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 214006429 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1701758467 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 401930986 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 402911994 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 395709487 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 399023483 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405620989 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 396449489 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 404605985 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 402179993 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3208432406 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 228006492 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 223295497 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 223196996 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 228513495 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 229209992 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 220676995 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 224532992 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 222245997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1799678456 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 629937478 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 626207491 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 618906483 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 627536978 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634830981 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 617126484 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 629138977 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 624425990 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5008110862 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055987 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.061196 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062901 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.056712 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.057988 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.057438 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.061492 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.059281 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.836616 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.846396 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.846221 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852915 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855196 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.854756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853544 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.848521 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690310 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.698723 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.692649 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.705160 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.697204 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.703256 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.699494 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.697958 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.287190 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.287190 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46609.388976 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47294.175540 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46968.504190 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46619.681182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46599.636225 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46979.961598 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46411.842407 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46998.478070 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46814.400260 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40729.266988 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40637.839276 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40733.916624 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40707.684320 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40668.047644 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40676.045817 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40692.731830 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40745.622311 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40699.067460 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41205.156422 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41269.020356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41204.249543 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41391.448237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41230.624830 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41179.802430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41288.807910 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41341.093430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41264.266834 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 64 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 698 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 714 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 712 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 688 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 687 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 684 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 709 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5568 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1951 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1970 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1832 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1968 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1954 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1963 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1919 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15492 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4416 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4335 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4345 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4456 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4447 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4499 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4406 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4370 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35274 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5114 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5049 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5057 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5132 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5135 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5186 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5090 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5079 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40842 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5114 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5049 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5057 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5132 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5135 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5186 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5090 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5079 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40842 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 33845945 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 35679430 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 34970423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 33623934 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34265930 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 34048934 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 33977929 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 35572914 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 275985439 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81779494 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81207491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 82576991 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 76840996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 82448987 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81922493 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82161995 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80384488 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 649322935 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 187970446 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 184467447 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 185588937 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189921941 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 189397436 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 191605943 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 187621956 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 185423942 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1501998048 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 221816391 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 220146877 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 220559360 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 223545875 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 223663366 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 225654877 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 221599885 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 220996856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1777983487 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 221816391 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 220146877 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 220559360 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 223545875 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 223663366 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 225654877 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 221599885 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 220996856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1777983487 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420548415 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 410318426 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 408411942 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 419559934 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 403725937 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410458428 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413026934 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 417703437 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3303753453 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230815972 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 233216955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 233429960 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229986451 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230895448 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 235553969 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233378955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230983963 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1858261673 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 651364387 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 643535381 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 641841902 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 649546385 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 634621385 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 646012397 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 646405889 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 648687400 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5162015126 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060701 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059580 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060425 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.060470 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059067 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062259 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.060888 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846421 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856953 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.852076 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.845799 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846816 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855517 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844664 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.847241 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.849435 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.707806 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.695827 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.690230 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.701732 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695496 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.700452 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.700143 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.700770 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.699049 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.287810 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.287810 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48489.892550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49971.190476 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49115.762640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49739.547337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49805.130814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49561.767103 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49675.334795 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50173.362482 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49566.350395 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41916.706304 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41967.695607 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41917.254315 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.775109 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41894.810467 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41925.533777 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41855.320937 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41888.737884 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41913.434999 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42565.771286 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42553.044291 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42713.219102 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42621.620512 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42589.933888 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42588.562569 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42583.285520 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42431.108009 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42580.882463 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1625,109 +1624,108 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 122833 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 120785 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 123722 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121674 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 83923 # Transaction distribution -system.membus.trans_dist::ReadResp 83923 # Transaction distribution -system.membus.trans_dist::WriteReq 43483 # Transaction distribution -system.membus.trans_dist::WriteResp 43481 # Transaction distribution -system.membus.trans_dist::Writeback 6000 # Transaction distribution +system.membus.trans_dist::ReadReq 84424 # Transaction distribution +system.membus.trans_dist::ReadResp 84420 # Transaction distribution +system.membus.trans_dist::WriteReq 43379 # Transaction distribution +system.membus.trans_dist::WriteResp 43377 # Transaction distribution +system.membus.trans_dist::Writeback 6250 # Transaction distribution system.membus.trans_dist::UpgradeReq 58661 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47607 # Transaction distribution -system.membus.trans_dist::ReadExReq 50527 # Transaction distribution -system.membus.trans_dist::ReadExResp 3086 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 420691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1047472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1047472 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58495 # Total snoops (count) -system.membus.snoop_fanout::samples 122833 # Request fanout histogram +system.membus.trans_dist::UpgradeResp 47649 # Transaction distribution +system.membus.trans_dist::ReadExReq 50299 # Transaction distribution +system.membus.trans_dist::ReadExResp 3116 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 421575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1077818 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1077818 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 58193 # Total snoops (count) +system.membus.snoop_fanout::samples 123722 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 122833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 123722 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 122833 # Request fanout histogram -system.membus.reqLayer0.occupancy 472878500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 31.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 318922500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 21.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 559080 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 259825 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 297207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 123722 # Request fanout histogram +system.membus.reqLayer0.occupancy 350831336 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 48.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 312389376 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 42.9 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 560254 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 259972 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 298234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 370692 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370683 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43483 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43481 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75478 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29380 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29380 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161449 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161449 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120254 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120627 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119815 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119764 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 961915 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1743799 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1739946 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1755311 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1759542 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1748105 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1744654 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1747573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 13981678 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 323561 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 559080 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.688315 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.176863 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 371185 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371180 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43379 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43375 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 75598 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29248 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29247 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161278 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120544 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120292 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120320 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120179 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120443 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120589 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 963055 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1746802 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1746902 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1761658 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1764505 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756981 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1763838 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1750408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14042106 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322707 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 560254 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.690126 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.177666 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 52722 9.43% 9.43% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 250233 44.76% 54.19% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141253 25.27% 79.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 69107 12.36% 91.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 29981 5.36% 97.18% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11505 2.06% 99.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3559 0.64% 99.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 720 0.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 52995 9.46% 9.46% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 250263 44.67% 54.13% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141259 25.21% 79.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 69446 12.40% 91.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 30460 5.44% 97.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11695 2.09% 99.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3486 0.62% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 650 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 559080 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1490758741 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 160617515 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 10.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 159518006 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 159700003 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 158882050 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 159826982 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 158824012 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 159298538 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 158114013 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 560254 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 719277462 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100586935 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100589620 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100255865 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100593415 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100466351 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100465013 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100397923 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100485866 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index f348549bd..b29e580fa 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000667 # Number of seconds simulated -sim_ticks 667077000 # Number of ticks simulated -final_tick 667077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000476 # Number of seconds simulated +sim_ticks 475552000 # Number of ticks simulated +final_tick 475552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 152389795 # Simulator tick rate (ticks/s) -host_mem_usage 222064 # Number of bytes of host memory used -host_seconds 4.38 # Real time elapsed on the host +host_tick_rate 102852654 # Simulator tick rate (ticks/s) +host_mem_usage 276856 # Number of bytes of host memory used +host_seconds 4.62 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 82891 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 81142 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 81431 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 77551 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77581 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 78240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78400 # Number of bytes read from this memory -system.physmem.bytes_read::total 640052 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 398656 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5632 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5599 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5418 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5436 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5426 # Number of bytes written to this memory -system.physmem.bytes_written::total 442654 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11008 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10927 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87353 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6229 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5632 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5599 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5418 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5426 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 124260018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 121638132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 122071365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 116254945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 124147587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 116299917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 117287809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 117527662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959487435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 597616167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 8184962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 8442803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 8393334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 8122001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 8238929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 8148984 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 8291397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 8133994 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 663572571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 597616167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 132444980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 130080935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 130464699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 124376946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 132386516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 124448902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 125579206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 125661655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1623060007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 82626 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 79372 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 82635 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 78892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79911 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 82560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 82806 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 80499 # Number of bytes read from this memory +system.physmem.bytes_read::total 649301 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 411072 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5529 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5498 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5527 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5415 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5350 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5500 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5539 # Number of bytes written to this memory +system.physmem.bytes_written::total 454846 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10947 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88160 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6423 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5529 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5527 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5416 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5415 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5500 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5539 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 173747561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 166904986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 173766486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 165895633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 168038406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 173608775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 174126068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 169274864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1365362778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 864410201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 11626489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 11561301 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 11622283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11388870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 11386767 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 11250084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 11565507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 11647517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 956459020 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 864410201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 185374050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 178466288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 185388769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 177284503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 179425173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 184858859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 185691575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 180922381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2321821799 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 55151 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22523 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.206747 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13668 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22921 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596309 # Average number of references to valid blocks. +system.cpu0.num_writes 55373 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22370 # number of replacements +system.cpu0.l1c.tags.tagsinuse 390.859535 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13365 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.587292 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.206747 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.767982 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.767982 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338453 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338453 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8785 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8785 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1208 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1208 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9993 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9993 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9993 # number of overall hits -system.cpu0.l1c.overall_hits::total 9993 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36702 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36702 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23741 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23741 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60443 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60443 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60443 # number of overall misses -system.cpu0.l1c.overall_misses::total 60443 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 964033198 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 964033198 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 878854454 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 878854454 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1842887652 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1842887652 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1842887652 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1842887652 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45487 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45487 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24949 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24949 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70436 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70436 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70436 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70436 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806868 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806868 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951581 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.951581 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858127 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858127 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858127 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858127 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26266.503133 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 26266.503133 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37018.426098 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 37018.426098 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.678739 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30489.678739 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.678739 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30489.678739 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1018774 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 390.859535 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.763398 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.763398 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338979 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338979 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8642 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8642 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1137 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1137 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9779 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9779 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9779 # number of overall hits +system.cpu0.l1c.overall_hits::total 9779 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36791 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36791 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23910 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23910 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60701 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60701 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60701 # number of overall misses +system.cpu0.l1c.overall_misses::total 60701 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 598271123 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 598271123 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 653921249 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 653921249 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1252192372 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1252192372 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1252192372 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1252192372 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45433 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45433 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25047 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25047 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70480 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70480 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70480 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70480 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809786 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809786 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954605 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954605 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861251 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861251 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861251 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861251 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16261.344432 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16261.344432 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27349.278503 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 27349.278503 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20628.859030 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20628.859030 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20628.859030 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20628.859030 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 775639 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63007 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66482 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.169219 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.666902 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9806 # number of writebacks -system.cpu0.l1c.writebacks::total 9806 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36702 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36702 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23741 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23741 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60443 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60443 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 885636434 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 885636434 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 828679478 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 828679478 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1714315912 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1714315912 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1714315912 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1714315912 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 700887059 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 700887059 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1711925608 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1711925608 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2412812667 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2412812667 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806868 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806868 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951581 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951581 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858127 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858127 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24130.467931 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24130.467931 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34904.994651 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34904.994651 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9788 # number of writebacks +system.cpu0.l1c.writebacks::total 9788 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36791 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36791 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23910 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23910 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60701 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60701 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60701 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60701 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 540766367 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 540766367 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 617095733 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 617095733 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1157862100 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1157862100 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1157862100 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1157862100 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 641214054 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 641214054 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 990476120 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 990476120 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1631690174 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1631690174 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809786 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809786 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954605 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954605 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861251 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861251 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14698.332935 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14698.332935 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25809.106357 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25809.106357 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99761 # number of read accesses completed -system.cpu1.num_writes 55328 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22642 # number of replacements -system.cpu1.l1c.tags.tagsinuse 394.589952 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13581 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.589632 # Average number of references to valid blocks. +system.cpu1.num_reads 99552 # number of read accesses completed +system.cpu1.num_writes 55312 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22247 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.170580 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13534 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.597712 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 394.589952 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.770684 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.770684 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339246 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339246 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8788 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8788 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1121 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9909 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9909 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9909 # number of overall hits -system.cpu1.l1c.overall_hits::total 9909 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36866 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36866 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23806 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23806 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60672 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60672 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60672 # number of overall misses -system.cpu1.l1c.overall_misses::total 60672 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 969094954 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 969094954 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 879252966 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 879252966 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1848347920 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1848347920 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1848347920 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1848347920 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45654 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45654 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24927 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24927 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70581 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70581 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70581 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70581 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807509 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807509 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955029 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859608 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859608 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859608 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859608 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26286.956925 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 26286.956925 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36934.090817 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 36934.090817 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30464.595200 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30464.595200 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30464.595200 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30464.595200 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1015089 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.170580 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.764005 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.764005 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338702 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338702 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8670 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8670 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1145 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1145 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9815 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9815 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9815 # number of overall hits +system.cpu1.l1c.overall_hits::total 9815 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36464 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36464 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 24184 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 24184 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60648 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60648 # number of overall misses +system.cpu1.l1c.overall_misses::total 60648 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 591998971 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 591998971 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 660686123 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 660686123 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1252685094 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1252685094 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1252685094 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1252685094 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45134 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45134 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25329 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25329 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70463 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70463 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70463 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70463 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807905 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807905 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954795 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954795 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860707 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860707 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860707 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860707 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16235.162654 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16235.162654 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27319.141705 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 27319.141705 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20655.010784 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20655.010784 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20655.010784 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20655.010784 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 776857 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62996 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66458 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.113547 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.689443 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9956 # number of writebacks -system.cpu1.l1c.writebacks::total 9956 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36866 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36866 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23806 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23806 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60672 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60672 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60672 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60672 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 890415084 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 890415084 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 828850208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 828850208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1719265292 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1719265292 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1719265292 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1719265292 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 690509167 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 690509167 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1720529946 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1720529946 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2411039113 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2411039113 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807509 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807509 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955029 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859608 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859608 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24152.744643 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24152.744643 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34816.861632 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34816.861632 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9776 # number of writebacks +system.cpu1.l1c.writebacks::total 9776 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36464 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36464 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24184 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 24184 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60648 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60648 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 534984781 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 534984781 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 623377675 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 623377675 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1158362456 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1158362456 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1158362456 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1158362456 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 640712682 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 640712682 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 989782156 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 989782156 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1630494838 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1630494838 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807905 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807905 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954795 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954795 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860707 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860707 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14671.587895 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14671.587895 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25776.450339 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25776.450339 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99243 # number of read accesses completed -system.cpu2.num_writes 55132 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22573 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.676253 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13694 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22978 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.595961 # Average number of references to valid blocks. +system.cpu2.num_reads 99606 # number of read accesses completed +system.cpu2.num_writes 55482 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22450 # number of replacements +system.cpu2.l1c.tags.tagsinuse 391.646892 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13596 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22843 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.595193 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.676253 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.770852 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.770852 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338823 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338823 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8940 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8940 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1180 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1180 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 10120 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 10120 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 10120 # number of overall hits -system.cpu2.l1c.overall_hits::total 10120 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36529 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36529 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23864 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23864 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60393 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60393 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60393 # number of overall misses -system.cpu2.l1c.overall_misses::total 60393 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 963156898 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 963156898 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 890183991 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 890183991 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1853340889 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1853340889 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1853340889 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1853340889 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45469 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45469 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25044 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25044 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70513 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70513 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70513 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70513 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803383 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.803383 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952883 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.952883 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856480 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856480 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856480 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856480 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26366.911166 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26366.911166 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37302.379777 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 37302.379777 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30688.008362 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30688.008362 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30688.008362 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30688.008362 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1016015 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 391.646892 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.764935 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.764935 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338700 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338700 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1179 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1179 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9940 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9940 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9940 # number of overall hits +system.cpu2.l1c.overall_hits::total 9940 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36421 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36421 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24109 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24109 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60530 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60530 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60530 # number of overall misses +system.cpu2.l1c.overall_misses::total 60530 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 592390101 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 592390101 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 664239589 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 664239589 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1256629690 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1256629690 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1256629690 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1256629690 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45182 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45182 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25288 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25288 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70470 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70470 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70470 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70470 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806095 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806095 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953377 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953377 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858947 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858947 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858947 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858947 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16265.069630 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16265.069630 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27551.519723 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 27551.519723 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20760.444243 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20760.444243 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20760.444243 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20760.444243 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 773028 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62631 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66120 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.222238 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.691289 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9915 # number of writebacks -system.cpu2.l1c.writebacks::total 9915 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36529 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36529 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23864 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23864 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60393 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60393 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60393 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60393 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 885079158 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 885079158 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 839760037 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 839760037 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1724839195 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1724839195 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1724839195 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1724839195 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 685753748 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 685753748 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1712116464 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1712116464 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2397870212 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2397870212 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803383 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803383 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952883 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952883 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856480 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856480 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24229.493225 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24229.493225 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35189.408188 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35189.408188 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9975 # number of writebacks +system.cpu2.l1c.writebacks::total 9975 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36421 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36421 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24109 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24109 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60530 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60530 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535479769 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535479769 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 627082203 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 627082203 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162561972 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1162561972 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162561972 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1162561972 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 634925616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 634925616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 991782664 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 991782664 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1626708280 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1626708280 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806095 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806095 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953377 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953377 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858947 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858947 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14702.500453 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14702.500453 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26010.295035 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26010.295035 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99256 # number of read accesses completed -system.cpu3.num_writes 54955 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22662 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.489449 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13390 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 23054 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.580810 # Average number of references to valid blocks. +system.cpu3.num_reads 99549 # number of read accesses completed +system.cpu3.num_writes 55104 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22310 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.032656 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13513 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22709 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.595050 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.489449 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770487 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770487 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337690 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337690 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8629 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8629 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1137 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1137 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9766 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9766 # number of overall hits -system.cpu3.l1c.overall_hits::total 9766 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36563 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36563 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23903 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23903 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60466 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60466 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60466 # number of overall misses -system.cpu3.l1c.overall_misses::total 60466 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 960736157 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 960736157 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 887839747 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 887839747 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1848575904 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1848575904 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1848575904 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1848575904 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45192 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45192 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25040 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25040 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70232 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70232 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70232 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70232 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809059 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.809059 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954593 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954593 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860947 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860947 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860947 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860947 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26276.185133 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 26276.185133 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 37143.444212 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 37143.444212 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30572.154665 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30572.154665 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30572.154665 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30572.154665 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1022448 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.032656 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.763736 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.763736 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 338332 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338332 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8654 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8654 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1182 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9836 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9836 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9836 # number of overall hits +system.cpu3.l1c.overall_hits::total 9836 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36530 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36530 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 24013 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 24013 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60543 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60543 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60543 # number of overall misses +system.cpu3.l1c.overall_misses::total 60543 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 590001438 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 590001438 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 660132360 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 660132360 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1250133798 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1250133798 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1250133798 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1250133798 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45184 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45184 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25195 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25195 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70379 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70379 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70379 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70379 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808472 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808472 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953086 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953086 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860242 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860242 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860242 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860242 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16151.148043 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16151.148043 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27490.624245 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 27490.624245 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20648.692632 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20648.692632 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20648.692632 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20648.692632 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 774871 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63227 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66332 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.171066 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.681707 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9928 # number of writebacks -system.cpu3.l1c.writebacks::total 9928 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36563 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36563 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23903 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60466 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60466 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60466 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60466 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 882571457 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882571457 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 837312821 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 837312821 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1719884278 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1719884278 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719884278 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1719884278 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 700068981 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 700068981 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1667398980 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1667398980 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2367467961 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2367467961 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809059 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809059 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954593 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954593 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860947 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860947 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24138.376419 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24138.376419 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 35029.612224 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35029.612224 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9907 # number of writebacks +system.cpu3.l1c.writebacks::total 9907 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36530 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36530 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24013 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 24013 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60543 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60543 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60543 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60543 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 532881722 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 532881722 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 623079094 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 623079094 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155960816 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1155960816 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155960816 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1155960816 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 642783574 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 642783574 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 972713175 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 972713175 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1615496749 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1615496749 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808472 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808472 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953086 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953086 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860242 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860242 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14587.509499 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14587.509499 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25947.573981 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25947.573981 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99292 # number of read accesses completed -system.cpu4.num_writes 54781 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22192 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.392100 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13471 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22589 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.596352 # Average number of references to valid blocks. +system.cpu4.num_reads 99755 # number of read accesses completed +system.cpu4.num_writes 55257 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22302 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.084224 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13540 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.596660 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.392100 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.768344 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.768344 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 369 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 336466 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 336466 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8698 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8698 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1159 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1159 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9857 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9857 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9857 # number of overall hits -system.cpu4.l1c.overall_hits::total 9857 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36438 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36438 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23701 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23701 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60139 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60139 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60139 # number of overall misses -system.cpu4.l1c.overall_misses::total 60139 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 959750489 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 959750489 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 883613878 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 883613878 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1843364367 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1843364367 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1843364367 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1843364367 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45136 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45136 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24860 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24860 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69996 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69996 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69996 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69996 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807294 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807294 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953379 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953379 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859178 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859178 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859178 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859178 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26339.274631 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 26339.274631 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37281.712924 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 37281.712924 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30651.729610 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30651.729610 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30651.729610 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30651.729610 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1023771 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 391.084224 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.763836 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.763836 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338305 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338305 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8852 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8852 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1084 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1084 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9936 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9936 # number of overall hits +system.cpu4.l1c.overall_hits::total 9936 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36600 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36600 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23847 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23847 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60447 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60447 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60447 # number of overall misses +system.cpu4.l1c.overall_misses::total 60447 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 590829220 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 590829220 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 656323200 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 656323200 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1247152420 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1247152420 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1247152420 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1247152420 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45452 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45452 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24931 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24931 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70383 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70383 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70383 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70383 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805245 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805245 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956520 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956520 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858830 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858830 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858830 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858830 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16142.874863 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16142.874863 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27522.254372 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 27522.254372 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20632.164045 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20632.164045 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20632.164045 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20632.164045 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 780817 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 62867 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66569 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.284712 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.729439 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9698 # number of writebacks -system.cpu4.l1c.writebacks::total 9698 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36438 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36438 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23701 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23701 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60139 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60139 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60139 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60139 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 881959493 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 881959493 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 833428166 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 833428166 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1715387659 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1715387659 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1715387659 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1715387659 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 703007482 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 703007482 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1705988496 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1705988496 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2408995978 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2408995978 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807294 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807294 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953379 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953379 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859178 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859178 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24204.388084 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24204.388084 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35164.261677 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35164.261677 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9856 # number of writebacks +system.cpu4.l1c.writebacks::total 9856 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36600 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36600 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23847 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23847 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60447 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60447 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533635904 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533635904 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 619552810 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 619552810 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1153188714 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1153188714 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1153188714 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1153188714 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 651255905 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 651255905 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 973411350 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 973411350 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1624667255 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1624667255 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805245 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805245 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956520 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956520 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858830 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858830 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14580.215956 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14580.215956 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25980.324988 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25980.324988 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99672 # number of read accesses completed -system.cpu5.num_writes 54824 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22459 # number of replacements -system.cpu5.l1c.tags.tagsinuse 393.671106 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13533 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22853 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.592176 # Average number of references to valid blocks. +system.cpu5.num_reads 99495 # number of read accesses completed +system.cpu5.num_writes 54912 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22132 # number of replacements +system.cpu5.l1c.tags.tagsinuse 389.508075 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13369 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22545 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.592992 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 393.671106 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.768889 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.768889 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337969 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337969 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8696 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8696 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1170 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9866 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9866 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9866 # number of overall hits -system.cpu5.l1c.overall_hits::total 9866 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36658 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36658 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23786 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23786 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60444 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60444 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60444 # number of overall misses -system.cpu5.l1c.overall_misses::total 60444 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 958216057 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 958216057 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 885896912 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 885896912 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1844112969 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1844112969 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1844112969 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1844112969 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45354 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45354 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24956 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24956 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70310 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70310 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808264 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808264 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953117 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953117 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859679 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859679 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859679 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859679 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26139.343581 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26139.343581 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37244.467838 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 37244.467838 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30509.446248 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30509.446248 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30509.446248 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30509.446248 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1026604 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 389.508075 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.760758 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.760758 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 409 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337023 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337023 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8615 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8615 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1193 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1193 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9808 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9808 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9808 # number of overall hits +system.cpu5.l1c.overall_hits::total 9808 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36426 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36426 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23853 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23853 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60279 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60279 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60279 # number of overall misses +system.cpu5.l1c.overall_misses::total 60279 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 593740716 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 593740716 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 656837719 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 656837719 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1250578435 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1250578435 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1250578435 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1250578435 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45041 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45041 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25046 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25046 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70087 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70087 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70087 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70087 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808730 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808730 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952368 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952368 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860060 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860060 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860060 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860060 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16299.915335 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16299.915335 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27536.901815 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 27536.901815 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20746.502679 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20746.502679 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20746.502679 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20746.502679 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 781949 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 63359 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66475 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.202970 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.763054 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9812 # number of writebacks -system.cpu5.l1c.writebacks::total 9812 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36658 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36658 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23786 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23786 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60444 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60444 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60444 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60444 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 879872261 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 879872261 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 835586106 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 835586106 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1715458367 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1715458367 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1715458367 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1715458367 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 707107291 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 707107291 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1680181552 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1680181552 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2387288843 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2387288843 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808264 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808264 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953117 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953117 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859679 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859679 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24002.189454 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24002.189454 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35129.324224 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35129.324224 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9742 # number of writebacks +system.cpu5.l1c.writebacks::total 9742 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36426 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36426 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23853 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23853 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60279 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60279 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60279 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60279 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 536794980 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 536794980 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 620108209 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 620108209 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156903189 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1156903189 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156903189 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1156903189 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648821919 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648821919 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 955346733 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 955346733 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1604168652 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1604168652 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808730 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808730 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952368 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952368 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860060 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860060 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14736.588700 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14736.588700 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 25997.074121 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 25997.074121 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99511 # number of read accesses completed -system.cpu6.num_writes 54977 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22541 # number of replacements -system.cpu6.l1c.tags.tagsinuse 393.448229 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13464 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.586948 # Average number of references to valid blocks. +system.cpu6.num_reads 99492 # number of read accesses completed +system.cpu6.num_writes 55188 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22041 # number of replacements +system.cpu6.l1c.tags.tagsinuse 390.749630 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13460 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22445 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.599688 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 393.448229 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.768454 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.768454 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337704 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337704 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8641 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8641 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1220 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1220 # number of WriteReq hits +system.cpu6.l1c.tags.occ_blocks::cpu6 390.749630 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.763183 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.763183 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337459 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337459 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1158 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1158 # number of WriteReq hits system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits system.cpu6.l1c.overall_hits::total 9861 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36671 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36671 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23713 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23713 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60384 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60384 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60384 # number of overall misses -system.cpu6.l1c.overall_misses::total 60384 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 960694665 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 960694665 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 879536054 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 879536054 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1840230719 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1840230719 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1840230719 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1840230719 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45312 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45312 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24933 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24933 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70245 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70245 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70245 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70245 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.809300 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.809300 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951069 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951069 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859620 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859620 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26197.667503 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 26197.667503 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37090.880698 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 37090.880698 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 30475.468982 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 30475.468982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 30475.468982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30475.468982 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1019991 # number of cycles access was blocked +system.cpu6.l1c.ReadReq_misses::cpu6 36430 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36430 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23907 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23907 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60337 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60337 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60337 # number of overall misses +system.cpu6.l1c.overall_misses::total 60337 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 592106528 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 592106528 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 650271582 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 650271582 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1242378110 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1242378110 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1242378110 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1242378110 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45133 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45133 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25065 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70198 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70198 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70198 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70198 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807170 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807170 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953800 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953800 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859526 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859526 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859526 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859526 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16253.267307 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16253.267307 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27200.049442 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 27200.049442 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20590.651010 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20590.651010 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20590.651010 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20590.651010 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 773385 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62969 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66167 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.198304 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.688379 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9771 # number of writebacks -system.cpu6.l1c.writebacks::total 9771 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36671 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36671 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23713 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23713 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60384 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60384 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60384 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60384 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 882425777 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 882425777 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 829351266 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 829351266 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1711777043 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1711777043 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1711777043 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1711777043 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702299487 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702299487 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1717296024 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1717296024 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2419595511 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2419595511 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.809300 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.809300 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951069 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951069 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24063.313708 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24063.313708 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34974.539957 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34974.539957 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9775 # number of writebacks +system.cpu6.l1c.writebacks::total 9775 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36430 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36430 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23907 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23907 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60337 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60337 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60337 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60337 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 535158836 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 535158836 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 613445646 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 613445646 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148604482 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1148604482 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148604482 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1148604482 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 648116847 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 648116847 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 997038722 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 997038722 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1645155569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1645155569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807170 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807170 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953800 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953800 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859526 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859526 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14690.058633 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14690.058633 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25659.666458 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25659.666458 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98836 # number of read accesses completed -system.cpu7.num_writes 54806 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22352 # number of replacements -system.cpu7.l1c.tags.tagsinuse 393.572142 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13400 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22745 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.589140 # Average number of references to valid blocks. +system.cpu7.num_reads 99953 # number of read accesses completed +system.cpu7.num_writes 55743 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22636 # number of replacements +system.cpu7.l1c.tags.tagsinuse 393.668569 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13591 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 23039 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.589913 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 393.572142 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.768696 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.768696 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 363 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 336509 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 336509 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8699 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8699 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1106 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9805 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9805 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9805 # number of overall hits -system.cpu7.l1c.overall_hits::total 9805 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36228 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36228 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23958 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23958 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60186 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60186 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60186 # number of overall misses -system.cpu7.l1c.overall_misses::total 60186 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 952764751 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 952764751 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 890612165 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 890612165 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1843376916 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1843376916 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1843376916 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1843376916 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44927 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44927 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25064 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25064 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69991 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69991 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69991 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69991 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806375 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806375 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955873 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955873 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859911 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859911 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859911 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859911 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26299.126394 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 26299.126394 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37173.894524 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37173.894524 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30628.001794 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30628.001794 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30628.001794 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30628.001794 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1021665 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 393.668569 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.768884 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.768884 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 340053 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 340053 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8802 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8802 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1188 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9990 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9990 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9990 # number of overall hits +system.cpu7.l1c.overall_hits::total 9990 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36601 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36601 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24152 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24152 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60753 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60753 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60753 # number of overall misses +system.cpu7.l1c.overall_misses::total 60753 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 595212008 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 595212008 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 656742976 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 656742976 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1251954984 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1251954984 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1251954984 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1251954984 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45403 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45403 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25340 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25340 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70743 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70743 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70743 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70743 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806136 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.806136 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953118 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953118 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858785 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858785 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858785 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858785 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16262.178848 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16262.178848 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27192.074197 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 27192.074197 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20607.294850 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20607.294850 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20607.294850 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20607.294850 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 772653 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62785 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66243 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.272438 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.663919 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9931 # number of writebacks -system.cpu7.l1c.writebacks::total 9931 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36228 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36228 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23958 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23958 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60186 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60186 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60186 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60186 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 875407713 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 875407713 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 839967251 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 839967251 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1715374964 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1715374964 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1715374964 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1715374964 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 702238586 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 702238586 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1694350083 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1694350083 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2396588669 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2396588669 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806375 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806375 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955873 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955873 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859911 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859911 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24163.843243 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24163.843243 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35059.990442 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35059.990442 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9979 # number of writebacks +system.cpu7.l1c.writebacks::total 9979 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36601 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36601 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24152 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24152 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60753 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60753 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60753 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60753 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538040158 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538040158 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 619565494 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 619565494 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1157605652 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1157605652 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1157605652 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1157605652 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639132078 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639132078 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 986824111 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 986824111 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1625956189 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1625956189 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806136 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806136 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953118 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953118 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858785 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858785 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14700.149122 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14700.149122 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25652.761428 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25652.761428 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,567 +1037,566 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13277 # number of replacements -system.l2c.tags.tagsinuse 783.059977 # Cycle average of tags in use -system.l2c.tags.total_refs 151520 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14056 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.779738 # Average number of references to valid blocks. +system.l2c.tags.replacements 13510 # number of replacements +system.l2c.tags.tagsinuse 783.849989 # Cycle average of tags in use +system.l2c.tags.total_refs 151949 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14294 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.630264 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 729.095705 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.040995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.066153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.783419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.143521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.879919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.083313 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.867349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.099602 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.712008 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006901 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006624 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006976 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.005941 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.005957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764707 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 779 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 598 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.760742 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1976800 # Number of tag accesses -system.l2c.tags.data_accesses 1976800 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10861 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10670 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10859 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10920 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10735 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86470 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76237 # number of Writeback hits -system.l2c.Writeback_hits::total 76237 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 346 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 369 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 358 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 342 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 356 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2777 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1915 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1982 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1977 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1937 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1931 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15500 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12853 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12857 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12666 # number of demand (read+write) hits -system.l2c.demand_hits::total 101970 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12644 # number of overall hits -system.l2c.overall_hits::cpu1 12776 # number of overall hits -system.l2c.overall_hits::cpu2 12853 # number of overall hits -system.l2c.overall_hits::cpu3 12647 # number of overall hits -system.l2c.overall_hits::cpu4 12710 # number of overall hits -system.l2c.overall_hits::cpu5 12817 # number of overall hits -system.l2c.overall_hits::cpu6 12857 # number of overall hits -system.l2c.overall_hits::cpu7 12666 # number of overall hits -system.l2c.overall_hits::total 101970 # number of overall hits -system.l2c.ReadReq_misses::cpu0 765 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 708 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 735 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 684 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 695 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 674 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5719 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1992 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1980 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1951 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1975 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1990 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2015 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15885 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4350 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4268 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4368 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4431 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4387 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4359 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4476 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35010 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5100 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5076 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5166 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5071 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5054 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5150 # number of demand (read+write) misses -system.l2c.demand_misses::total 40729 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5115 # number of overall misses -system.l2c.overall_misses::cpu1 4997 # number of overall misses -system.l2c.overall_misses::cpu2 5100 # number of overall misses -system.l2c.overall_misses::cpu3 5076 # number of overall misses -system.l2c.overall_misses::cpu4 5166 # number of overall misses -system.l2c.overall_misses::cpu5 5071 # number of overall misses -system.l2c.overall_misses::cpu6 5054 # number of overall misses -system.l2c.overall_misses::cpu7 5150 # number of overall misses -system.l2c.overall_misses::total 40729 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 46620930 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 44960918 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 44432427 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 43382432 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 44487433 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 41294425 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 42419930 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 41189936 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 348788431 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 57711996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 58106496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 57659498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 57666495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 55433497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57841495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 59041000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 57235498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 460695975 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 234061451 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 229252453 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 235963436 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 234901447 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 238651447 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 236178452 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 234894949 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 241135947 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1885039582 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 280682381 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 274213371 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 280395863 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 278283879 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 283138880 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 277472877 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 277314879 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 282325883 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2233828013 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 280682381 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 274213371 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 280395863 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 278283879 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 283138880 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 277472877 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 277314879 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 282325883 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2233828013 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11509 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11590 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11600 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11378 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11545 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11543 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11615 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11409 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 92189 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76237 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76237 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2336 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2320 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2370 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18662 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6250 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6183 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6353 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6331 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6407 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50510 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17953 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17723 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17876 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17888 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17911 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17816 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142699 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17953 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17723 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17876 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17888 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17911 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17816 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142699 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.066470 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.062899 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.062845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.062225 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.063664 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.059257 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.059836 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.059076 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.062036 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.852740 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.851247 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.840948 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.848945 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852395 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.859240 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.857082 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.846948 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.851195 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.696000 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.690280 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.688021 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.688416 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.699889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.691411 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692344 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.698611 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.693130 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.288023 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.281157 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.284075 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.286407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288991 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.283486 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.282173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.289066 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.285419 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.288023 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.281157 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.284075 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.286407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288991 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.283486 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.282173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.289066 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285419 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60942.392157 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61674.784636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 60949.831276 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61274.621469 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 60527.119728 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 60371.966374 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61035.870504 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61112.664688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 60987.660605 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28971.885542 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 29346.715152 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29553.817529 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 28661.279821 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28067.593418 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29066.077889 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29300.744417 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29053.552284 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29001.949953 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53807.230115 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53714.257966 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53983.856326 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53777.803800 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53859.500564 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53835.981764 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53887.347786 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53873.089142 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53842.890089 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54874.365787 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54875.599560 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54979.580980 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54823.459220 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54808.145567 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54717.585683 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54870.375742 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54820.559806 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54846.129613 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54874.365787 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54875.599560 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54979.580980 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54823.459220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54808.145567 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54717.585683 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54870.375742 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54820.559806 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54846.129613 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 11130 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 725.717756 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.606207 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.042760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.314362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.280142 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.903512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.337678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.211948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.435623 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.708709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007428 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006878 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006742 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765479 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 680 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1986932 # Number of tag accesses +system.l2c.tags.data_accesses 1986932 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10772 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10720 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10796 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10828 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10876 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10784 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10741 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86242 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77037 # number of Writeback hits +system.l2c.Writeback_hits::total 77037 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 331 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 373 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 321 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 366 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2816 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2031 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1999 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1974 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2000 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1993 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1967 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15914 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12803 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12770 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12828 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12869 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12764 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12711 # number of demand (read+write) hits +system.l2c.demand_hits::total 102156 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12803 # number of overall hits +system.l2c.overall_hits::cpu1 12719 # number of overall hits +system.l2c.overall_hits::cpu2 12770 # number of overall hits +system.l2c.overall_hits::cpu3 12828 # number of overall hits +system.l2c.overall_hits::cpu4 12869 # number of overall hits +system.l2c.overall_hits::cpu5 12764 # number of overall hits +system.l2c.overall_hits::cpu6 12692 # number of overall hits +system.l2c.overall_hits::cpu7 12711 # number of overall hits +system.l2c.overall_hits::total 102156 # number of overall hits +system.l2c.ReadReq_misses::cpu0 731 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 674 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 746 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 694 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 702 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 746 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 727 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5742 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1949 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2075 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2001 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2024 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1976 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1982 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1991 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1901 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15899 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4324 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4508 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4412 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4451 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4429 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4405 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35131 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5104 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 4998 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5254 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5106 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5153 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5175 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 4951 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5132 # number of demand (read+write) misses +system.l2c.demand_misses::total 40873 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5104 # number of overall misses +system.l2c.overall_misses::cpu1 4998 # number of overall misses +system.l2c.overall_misses::cpu2 5254 # number of overall misses +system.l2c.overall_misses::cpu3 5106 # number of overall misses +system.l2c.overall_misses::cpu4 5153 # number of overall misses +system.l2c.overall_misses::cpu5 5175 # number of overall misses +system.l2c.overall_misses::cpu6 4951 # number of overall misses +system.l2c.overall_misses::cpu7 5132 # number of overall misses +system.l2c.overall_misses::total 40873 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 45095926 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 41549422 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 46449929 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 42922928 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 43252423 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 45919927 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 44260438 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 44979437 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 354430430 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 56379995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 59258495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 58685995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 56511495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 59771492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 56753497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 61514994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 54850495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 463726458 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 240858936 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 238452262 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 247966448 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 242840437 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 244973443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 243557270 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 233129438 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 242077945 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1933856179 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 285954862 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 280001684 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 294416377 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 285763365 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 288225866 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 289477197 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 277389876 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 287057382 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2288286609 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 285954862 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 280001684 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 294416377 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 285763365 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 288225866 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 289477197 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 277389876 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 287057382 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2288286609 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11503 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11394 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11542 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11522 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11578 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11447 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11468 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91984 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77037 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77037 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2280 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2448 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2364 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2377 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2297 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2345 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2337 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2267 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18715 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6404 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6482 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6444 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6409 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6196 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6375 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51045 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18024 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17934 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17939 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17843 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143029 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18024 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17934 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17939 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17843 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143029 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.063549 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.059154 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064634 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060233 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.060632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.064701 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.063073 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.063394 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.062424 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.854825 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.847631 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.846447 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851493 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.860253 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.845203 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.851947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.838553 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849532 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.682854 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.683853 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.695464 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.688085 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.690720 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.691059 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.682537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.690980 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.688236 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.285028 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.282102 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.291500 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.284711 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.285928 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.288478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.280621 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.287620 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.285767 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.285028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.282102 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.291500 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.284711 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.285928 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.288478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.280621 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.287620 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.285767 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 61690.733242 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61646.026706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 62265.320375 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61848.599424 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61613.138177 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61554.861930 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61302.545706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 61869.927098 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61725.954371 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28927.652642 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28558.310843 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29328.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27920.699111 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 30248.730769 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28634.458628 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30896.531391 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 28853.495529 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29167.020442 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55078.649897 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55146.221554 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55005.866903 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55040.896872 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55037.843855 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54991.481147 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55126.374557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54955.265607 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55047.000626 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56025.639107 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56022.745898 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56036.615341 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55966.189777 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55933.604890 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55937.622609 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56027.040194 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55934.797740 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55985.286350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56025.639107 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56022.745898 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56036.615341 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55966.189777 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55933.604890 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55937.622609 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56027.040194 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55934.797740 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55985.286350 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17581 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1567 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3250 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.102744 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.409538 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6229 # number of writebacks -system.l2c.writebacks::total 6229 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 11 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6423 # number of writebacks +system.l2c.writebacks::total 6423 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 21 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 758 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 722 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 718 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 704 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 730 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 673 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 692 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 669 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5666 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1992 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1980 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1951 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2012 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1974 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1990 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2015 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1969 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15883 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4346 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4265 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4369 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4364 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4383 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4358 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4474 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34989 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5104 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4987 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5087 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5068 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5160 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5050 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5143 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40655 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5104 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4987 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5087 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5068 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5160 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5056 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5050 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5143 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40655 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 37179930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 35966920 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 35314428 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 34763932 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 35492434 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 32731425 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 33928930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 32969437 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 278347436 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81798995 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81126494 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80135996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 82599489 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81068996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81609993 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82618495 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80871496 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 651829954 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 181281952 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 177509453 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 183001436 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 181913947 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 184978447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 182997452 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182077949 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 186899447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1460660083 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 218461882 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 213476373 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 218315864 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 216677879 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 220470881 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 215728877 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 216006879 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 219868884 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1739007519 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 218461882 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 213476373 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 218315864 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 216677879 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 220470881 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 215728877 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 216006879 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 219868884 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1739007519 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 407707447 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 401123946 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 397019445 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 405812955 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407128948 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410535950 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408564954 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406637950 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3244531595 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230392811 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237768794 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237208468 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229246463 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 232269476 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230268468 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 234242974 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227836970 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1859234424 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 638100258 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 638892740 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 634227913 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 635059418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 639398424 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 640804418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 642807928 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 634474920 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5103766019 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065861 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.061897 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061874 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063231 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058304 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059578 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.058638 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.061461 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852740 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851247 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840948 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.848945 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851964 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.859240 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.857082 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.846518 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.851088 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.695360 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689795 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.687707 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687786 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.699731 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690780 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.692186 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698299 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.692714 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284900 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284900 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49050.039578 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49815.678670 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49184.440111 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49380.585227 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.772603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48635.104012 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49030.245665 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49281.669656 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49125.915284 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41063.752510 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40972.976768 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41074.318811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41053.423956 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41068.387031 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41010.046734 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41001.734491 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41072.369731 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41039.473273 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41712.368155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41620.035873 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41886.343786 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41685.139093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41755.857111 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41751.643167 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41780.162689 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41774.574654 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41746.265483 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 100 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 725 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 661 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 738 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 690 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 692 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 741 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 711 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 723 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5681 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2001 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2023 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1976 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1991 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1901 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15897 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4368 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4317 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4505 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4406 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4442 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4423 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4402 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35092 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5093 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 4978 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5096 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5134 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5164 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4940 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5125 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40773 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5093 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 4978 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5096 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5134 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5164 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4940 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5125 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40773 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 36140918 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 33131910 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 37333917 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 34463914 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34507911 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 36862423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 35293427 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 36098935 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 283833355 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 82188451 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 87682473 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 84603955 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85652462 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 83560954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83969963 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 84367474 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80329284 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 672355016 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 188025870 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 186115345 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193429372 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189404867 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 191140359 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 189945201 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 182082372 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 188836863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1508980249 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 224166788 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 219247255 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 230763289 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 223868781 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 225648270 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 226807624 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 217375799 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 224935798 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1792813604 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 224166788 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 219247255 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 230763289 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 223868781 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 225648270 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 226807624 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 217375799 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 224935798 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1792813604 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 419997297 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 420394389 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 416554764 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 421667758 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 426680271 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 424776767 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 425015068 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 419160275 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3374246589 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 245735705 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 245037892 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 243130891 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 240328902 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241689545 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 236933897 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 244635896 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 245230718 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1942723446 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 665733002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 665432281 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 659685655 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 661996660 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 668369816 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 661710664 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 669650964 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 664390993 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5316970035 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.063027 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.058013 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.063940 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059885 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.059769 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064267 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.062112 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063045 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.061761 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854825 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847222 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.846447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851073 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.860253 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845203 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838553 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.849426 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.682074 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682746 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.695002 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687149 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.689323 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.682537 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.690510 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.687472 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285068 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285068 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49849.542069 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50123.918306 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50587.963415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49947.701449 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49866.923410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49746.859649 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49639.137834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49929.370678 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49961.864989 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42169.548999 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42276.987946 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42280.837081 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42339.328720 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42287.932186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42366.278002 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42374.421899 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42256.330352 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42294.459080 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43046.215659 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43112.194811 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42936.597558 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42987.940763 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43030.247411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42944.879267 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43055.656656 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42897.969786 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43000.691012 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1626,64 +1625,64 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 84242 # Transaction distribution -system.membus.trans_dist::ReadResp 84239 # Transaction distribution -system.membus.trans_dist::WriteReq 43998 # Transaction distribution -system.membus.trans_dist::WriteResp 43998 # Transaction distribution -system.membus.trans_dist::Writeback 6229 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58563 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47765 # Transaction distribution -system.membus.trans_dist::ReadExReq 50044 # Transaction distribution -system.membus.trans_dist::ReadExResp 3111 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 422189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 422189 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1082703 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1082703 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57731 # Total snoops (count) -system.membus.snoop_fanout::samples 123701 # Request fanout histogram +system.membus.trans_dist::ReadReq 84922 # Transaction distribution +system.membus.trans_dist::ReadResp 84916 # Transaction distribution +system.membus.trans_dist::WriteReq 43774 # Transaction distribution +system.membus.trans_dist::WriteResp 43771 # Transaction distribution +system.membus.trans_dist::Writeback 6423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58524 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47755 # Transaction distribution +system.membus.trans_dist::ReadExReq 50059 # Transaction distribution +system.membus.trans_dist::ReadExResp 3238 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 423382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 423382 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1104141 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1104141 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57586 # Total snoops (count) +system.membus.snoop_fanout::samples 124108 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123701 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 124108 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123701 # Request fanout histogram -system.membus.reqLayer0.occupancy 290076020 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 43.5 # Layer utilization (%) -system.membus.respLayer0.occupancy 312416500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 46.8 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 371224 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371216 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43998 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43997 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 76237 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29460 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29459 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161009 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161004 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121112 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120671 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120387 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120891 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120940 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 965857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1759071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1770038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776630 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1763929 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1758071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1768584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1767034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1770802 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14134159 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 321748 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 561380 # Request fanout histogram +system.membus.snoop_fanout::total 124108 # Request fanout histogram +system.membus.reqLayer0.occupancy 285888056 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 60.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 306910429 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 64.5 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 371514 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371497 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43774 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43771 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 77037 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29480 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29478 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162492 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162484 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121222 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 121316 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 121170 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 121269 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120825 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 121366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 969045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1773466 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1761542 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1792162 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785037 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1774053 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1756466 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1780883 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14206666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322486 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 565861 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1694,29 +1693,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 561380 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 565861 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 561380 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 655414034 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 160915376 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 161401861 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 160885313 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 160977419 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 160313901 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 24.0 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 161018393 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 160998320 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 160391036 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 24.0 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 565861 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 447470354 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 94.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102002382 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101806870 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101634818 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101702738 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101696707 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101422885 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101516818 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101999422 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 0808c4e4e..5b3332128 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 8581932612 # Simulator tick rate (ticks/s) -host_mem_usage 264172 # Number of bytes of host memory used -host_seconds 11.65 # Real time elapsed on the host +host_tick_rate 8616438631 # Simulator tick rate (ticks/s) +host_mem_usage 263800 # Number of bytes of host memory used +host_seconds 11.61 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -278,15 +278,15 @@ system.cpu.retryTicks 0 # Ti system.membus.trans_dist::ReadReq 1666397 # Transaction distribution system.membus.trans_dist::ReadResp 1666397 # Transaction distribution system.membus.trans_dist::WriteReq 1666879 # Transaction distribution -system.membus.trans_dist::WriteResp 1666879 # Transaction distribution -system.membus.pkt_count_system.monitor-master::system.physmem.port 6666552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6666552 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::WriteResp 1666878 # Transaction distribution +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666551 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11428907481 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 11.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 11028299087 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 11.0 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets @@ -339,8 +339,8 @@ system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1063154535.263763 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107915844.091091 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154851.723305 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107909478.113936 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -392,55 +392,55 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 75229.617239 # Read request-response latency -system.monitor.readLatencyHist::gmean 69644.568825 # Read request-response latency -system.monitor.readLatencyHist::stdev 40693.683003 # Read request-response latency +system.monitor.readLatencyHist::mean 78736.863581 # Read request-response latency +system.monitor.readLatencyHist::gmean 73318.978124 # Read request-response latency +system.monitor.readLatencyHist::stdev 40691.515724 # Read request-response latency system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 444791 26.69% 26.69% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1023501 61.42% 88.11% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 76998 4.62% 92.73% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 56964 3.42% 96.15% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 25239 1.51% 97.67% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 9180 0.55% 98.22% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7794 0.47% 98.69% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 7780 0.47% 99.15% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7547 0.45% 99.61% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 3313 0.20% 99.80% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1429 0.09% 99.89% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 850 0.05% 99.94% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 662 0.04% 99.98% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 284 0.02% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 42 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::524288-557055 1 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 439224 26.36% 26.36% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1018381 61.11% 87.47% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 80826 4.85% 92.32% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 59766 3.59% 95.91% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 27643 1.66% 97.57% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 9933 0.60% 98.16% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7785 0.47% 98.63% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 7834 0.47% 99.10% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7851 0.47% 99.57% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 3709 0.22% 99.79% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1488 0.09% 99.88% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 851 0.05% 99.93% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 701 0.04% 99.98% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 330 0.02% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 51 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::524288-557055 2 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency -system.monitor.writeLatencyHist::samples 1666879 # Write request-response latency -system.monitor.writeLatencyHist::mean 10556.022655 # Write request-response latency -system.monitor.writeLatencyHist::gmean 10498.307841 # Write request-response latency -system.monitor.writeLatencyHist::stdev 1185.079839 # Write request-response latency -system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::3072-4095 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::4096-5119 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::5120-6143 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::9216-10239 1276777 76.60% 76.60% # Write request-response latency -system.monitor.writeLatencyHist::10240-11263 91385 5.48% 82.08% # Write request-response latency -system.monitor.writeLatencyHist::11264-12287 111087 6.66% 88.74% # Write request-response latency -system.monitor.writeLatencyHist::12288-13311 90448 5.43% 94.17% # Write request-response latency -system.monitor.writeLatencyHist::13312-14335 61415 3.68% 97.85% # Write request-response latency -system.monitor.writeLatencyHist::14336-15359 31809 1.91% 99.76% # Write request-response latency -system.monitor.writeLatencyHist::15360-16383 3958 0.24% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::16384-17407 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::19456-20479 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::total 1666879 # Write request-response latency +system.monitor.writeLatencyHist::samples 1666878 # Write request-response latency +system.monitor.writeLatencyHist::mean 17579.367741 # Write request-response latency +system.monitor.writeLatencyHist::gmean 17571.346759 # Write request-response latency +system.monitor.writeLatencyHist::stdev 555.431458 # Write request-response latency +system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::6144-8191 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::8192-10239 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::10240-12287 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::12288-14335 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::14336-16383 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::16384-18431 1620268 97.20% 97.20% # Write request-response latency +system.monitor.writeLatencyHist::18432-20479 30675 1.84% 99.04% # Write request-response latency +system.monitor.writeLatencyHist::20480-22527 12936 0.78% 99.82% # Write request-response latency +system.monitor.writeLatencyHist::22528-24575 2999 0.18% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::24576-26623 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::26624-28671 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::28672-30719 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::38912-40959 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::total 1666878 # Write request-response latency system.monitor.ittReadRead::samples 1666396 # Read-to-read inter transaction time system.monitor.ittReadRead::mean 60009.683149 # Read-to-read inter transaction time system.monitor.ittReadRead::stdev 42949.620471 # Read-to-read inter transaction time @@ -526,12 +526,12 @@ system.monitor.ittReqReq::min_value 28000 # Re system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.210000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.260000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.281532 # Outstanding read transactions -system.monitor.outstandingReadsHist::0 27 27.00% 27.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 46 46.00% 73.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 18 18.00% 91.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.284091 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 26 26.00% 26.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 43 43.00% 69.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 22 22.00% 91.00% # Outstanding read transactions system.monitor.outstandingReadsHist::3 4 4.00% 95.00% # Outstanding read transactions system.monitor.outstandingReadsHist::4 1 1.00% 96.00% # Outstanding read transactions system.monitor.outstandingReadsHist::5 3 3.00% 99.00% # Outstanding read transactions @@ -551,11 +551,11 @@ system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions -system.monitor.outstandingWritesHist::mean 0.190000 # Outstanding write transactions +system.monitor.outstandingWritesHist::mean 0.320000 # Outstanding write transactions system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions -system.monitor.outstandingWritesHist::stdev 0.394277 # Outstanding write transactions -system.monitor.outstandingWritesHist::0 81 81.00% 81.00% # Outstanding write transactions -system.monitor.outstandingWritesHist::1 19 19.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::stdev 0.468826 # Outstanding write transactions +system.monitor.outstandingWritesHist::0 68 68.00% 68.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::1 32 32.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions |