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authorSteve Reinhardt <stever@gmail.com>2012-07-23 00:39:12 -0400
committerSteve Reinhardt <stever@gmail.com>2012-07-23 00:39:12 -0400
commit42596d27e95696e1c9bb0b421ad910091860d11e (patch)
tree90e23bbb23816cbca0c92bf6772ead6f848ae59b /tests/quick/se
parent882a4b65bd768de48efca51fb5477f70517a2bfa (diff)
downloadgem5-42596d27e95696e1c9bb0b421ad910091860d11e.tar.xz
test: Update eio ref outputs due to recent changes
Actual stats updates covering period since original ref outputs were clobbered.
Diffstat (limited to 'tests/quick/se')
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini13
-rwxr-xr-xtests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr1
-rwxr-xr-xtests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout6
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt42
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini23
-rwxr-xr-xtests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout8
-rw-r--r--tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt129
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini39
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout6
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt133
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini35
-rwxr-xr-xtests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout8
-rw-r--r--tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt1137
13 files changed, 944 insertions, 636 deletions
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 7c413d69b..3fc579691 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@@ -85,19 +85,20 @@ output=cout
system=system
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
index 850fc5669..b8e6dc45f 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
@@ -1,3 +1,4 @@
+warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
index 94e5c0a9b..3fdf9580f 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 29 2012 00:47:21
-gem5 started Feb 29 2012 00:51:57
+gem5 compiled Jul 22 2012 20:21:46
+gem5 started Jul 23 2012 00:28:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 5065b3dff..32e1aa3e7 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3174528 # Simulator instruction rate (inst/s)
-host_op_rate 3174125 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1586983445 # Simulator tick rate (ticks/s)
-host_mem_usage 203780 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 1870393 # Simulator instruction rate (inst/s)
+host_op_rate 1870272 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 935134836 # Simulator tick rate (ticks/s)
+host_mem_usage 212756 # Number of bytes of host memory used
+host_seconds 0.27 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 2872676 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 2000076 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 417562 # Number of bytes written to this memory
-system.physmem.num_reads 624454 # Number of read requests responded to by this memory
-system.physmem.num_writes 56340 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 11489991621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 7999808012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 1670144451 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 13160136072 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory
+system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 2000076 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 2000076 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 417562 # Number of bytes written to this memory
+system.physmem.bytes_written::total 417562 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 500019 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 124435 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 624454 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 56340 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 56340 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7999808012 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3490183609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 11489991621 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7999808012 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7999808012 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1670144451 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1670144451 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 4fea94adf..b45e06437 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -88,7 +87,7 @@ size=64
[system.cpu.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -120,7 +119,7 @@ size=48
[system.cpu.l2cache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -144,13 +143,12 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -168,19 +166,20 @@ output=cout
system=system
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
index 51a8ca57b..a532af78a 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 29 2012 00:47:21
-gem5 started Feb 29 2012 00:51:57
+gem5 compiled Jul 22 2012 20:21:46
+gem5 started Jul 23 2012 00:28:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
->Exiting @ tick 727929000 because a thread reached the max instruction count
+>Exiting @ tick 729729000 because a thread reached the max instruction count
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index a62b8b2ca..c39a44a4e 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,25 +1,32 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000728 # Number of seconds simulated
-sim_ticks 727929000 # Number of ticks simulated
-final_tick 727929000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000730 # Number of seconds simulated
+sim_ticks 729729000 # Number of ticks simulated
+final_tick 729729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1742138 # Simulator instruction rate (inst/s)
-host_op_rate 1742023 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2535976572 # Simulator tick rate (ticks/s)
-host_mem_usage 212652 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
+host_inst_rate 1176795 # Simulator instruction rate (inst/s)
+host_op_rate 1176746 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1717342738 # Simulator tick rate (ticks/s)
+host_mem_usage 221204 # Number of bytes of host memory used
+host_seconds 0.43 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 54848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 857 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 75348008 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 35432027 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 75348008 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::total 54848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 35344628 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 39817521 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 75162149 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 35344628 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 35344628 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 35344628 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 39817521 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 75162149 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -53,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 1455858 # number of cpu cycles simulated
+system.cpu.numCycles 1459458 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
@@ -72,18 +79,18 @@ system.cpu.num_mem_refs 180793 # nu
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1455858 # Number of busy cycles
+system.cpu.num_busy_cycles 1459458 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 264.795716 # Cycle average of tags in use
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 264.952126 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.129371 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.129371 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 264.795716 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.129295 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.129295 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
@@ -109,17 +116,23 @@ system.cpu.icache.demand_accesses::total 500020 # nu
system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
@@ -135,21 +148,27 @@ system.cpu.icache.demand_mshr_miss_latency::total 21359000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21359000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 286.968386 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 287.175167 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.070111 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.070111 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data 286.968386 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.070061 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.070061 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
@@ -183,19 +202,27 @@ system.cpu.dcache.demand_accesses::total 180775 # nu
system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
@@ -215,25 +242,33 @@ system.cpu.dcache.demand_mshr_miss_latency::total 24062000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 481.117902 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 264.958770 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 216.460700 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.008086 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.006606 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.014692 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 264.802343 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 216.315558 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.008081 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.006601 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.014683 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
@@ -269,24 +304,32 @@ system.cpu.l2cache.overall_accesses::cpu.data 454
system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
@@ -313,18 +356,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18160000
system.cpu.l2cache.overall_mshr_miss_latency::total 34280000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index f80f13394..0853f81cf 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
@@ -62,7 +62,7 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -91,7 +91,7 @@ size=64
[system.cpu0.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -145,6 +145,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
@@ -168,7 +169,7 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -197,7 +198,7 @@ size=64
[system.cpu1.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -251,6 +252,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu2.interrupts
@@ -274,7 +276,7 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -303,7 +305,7 @@ size=64
[system.cpu2.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -357,6 +359,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
+fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu3.interrupts
@@ -380,7 +383,7 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -409,7 +412,7 @@ size=64
[system.cpu3.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -454,7 +457,7 @@ system=system
[system.l2c]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
@@ -478,19 +481,20 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[0]
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.l2c.mem_side system.system_port
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false
@@ -499,13 +503,12 @@ zero=false
port=system.membus.master[0]
[system.toL2Bus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 9e07934a0..93473d0a5 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 29 2012 00:47:21
-gem5 started Feb 29 2012 00:51:57
+gem5 compiled Jul 22 2012 20:21:46
+gem5 started Jul 23 2012 00:28:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 8880fe952..84894234a 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -4,22 +4,59 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3384594 # Simulator instruction rate (inst/s)
-host_op_rate 3384489 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 423074550 # Simulator tick rate (ticks/s)
-host_mem_usage 1140672 # Number of bytes of host memory used
-host_seconds 0.59 # Real time elapsed on the host
+host_inst_rate 2922206 # Simulator instruction rate (inst/s)
+host_op_rate 2922133 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 365280152 # Simulator tick rate (ticks/s)
+host_mem_usage 1149344 # Number of bytes of host memory used
+host_seconds 0.68 # Real time elapsed on the host
sim_insts 2000004 # Number of instructions simulated
sim_ops 2000004 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 219392 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 3428 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 877513594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 412646416 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 877513594 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 103161604 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 116216795 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 103161604 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 116216795 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 103161604 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 116216795 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 103161604 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 116216795 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 877513594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 412646416 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 116216795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 116216795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 116216795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
@@ -103,14 +140,17 @@ system.cpu0.icache.demand_accesses::total 500019 # n
system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -148,15 +188,19 @@ system.cpu0.dcache.demand_accesses::total 180775 # n
system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
@@ -245,14 +289,17 @@ system.cpu1.icache.demand_accesses::total 500019 # n
system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -290,15 +337,19 @@ system.cpu1.dcache.demand_accesses::total 180775 # n
system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
@@ -387,14 +438,17 @@ system.cpu2.icache.demand_accesses::total 500019 # n
system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -432,15 +486,19 @@ system.cpu2.dcache.demand_accesses::total 180775 # n
system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
@@ -529,14 +587,17 @@ system.cpu3.icache.demand_accesses::total 500019 # n
system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
@@ -574,15 +635,19 @@ system.cpu3.dcache.demand_accesses::total 180775 # n
system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
@@ -716,10 +781,12 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
@@ -728,6 +795,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
@@ -736,12 +804,13 @@ system.l2c.overall_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 2501d9722..8d9896222 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
-physmem=system.physmem
readfile=
symbolfile=
work_begin_ckpt_count=0
@@ -59,7 +58,7 @@ icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -88,7 +87,7 @@ size=64
[system.cpu0.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -162,7 +161,7 @@ icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -191,7 +190,7 @@ size=64
[system.cpu1.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -265,7 +264,7 @@ icache_port=system.cpu2.icache.cpu_side
[system.cpu2.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -294,7 +293,7 @@ size=64
[system.cpu2.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -368,7 +367,7 @@ icache_port=system.cpu3.icache.cpu_side
[system.cpu3.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
@@ -397,7 +396,7 @@ size=64
[system.cpu3.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
@@ -442,7 +441,7 @@ system=system
[system.l2c]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
@@ -466,19 +465,20 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[0]
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.l2c.mem_side system.system_port
[system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
file=
+in_addr_map=true
latency=30000
latency_var=0
null=false
@@ -487,13 +487,12 @@ zero=false
port=system.membus.master[0]
[system.toL2Bus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index ae6fe41da..ed2a31412 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 29 2012 00:47:21
-gem5 started Feb 29 2012 00:51:57
+gem5 compiled Jul 22 2012 20:21:46
+gem5 started Jul 23 2012 00:28:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
@@ -15,4 +17,4 @@ main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
->>>>Exiting @ tick 728920000 because a thread reached the max instruction count
+>>>>Exiting @ tick 731328000 because a thread reached the max instruction count
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 08b853160..8620acfdf 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,25 +1,62 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000729 # Number of seconds simulated
-sim_ticks 728920000 # Number of ticks simulated
-final_tick 728920000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000731 # Number of seconds simulated
+sim_ticks 731328000 # Number of ticks simulated
+final_tick 731328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1560894 # Simulator instruction rate (inst/s)
-host_op_rate 1560871 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 568880584 # Simulator tick rate (ticks/s)
-host_mem_usage 223172 # Number of bytes of host memory used
-host_seconds 1.28 # Real time elapsed on the host
-sim_insts 1999954 # Number of instructions simulated
-sim_ops 1999954 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 219392 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 3428 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 300982275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 141535422 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 300982275 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 1393062 # Simulator instruction rate (inst/s)
+host_op_rate 1393035 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 509417209 # Simulator tick rate (ticks/s)
+host_mem_usage 231840 # Number of bytes of host memory used
+host_seconds 1.44 # Real time elapsed on the host
+sim_insts 1999829 # Number of instructions simulated
+sim_ops 1999829 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
+system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 35267349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 39730463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35267349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 39730463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 35267349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 39730463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 35267349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 39730463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 299991249 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 35267349 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 141069397 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 39730463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 39730463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 39730463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 35267349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 39730463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 299991249 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
@@ -53,7 +90,7 @@ system.cpu0.itb.data_misses 0 # DT
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.numCycles 1457840 # number of cpu cycles simulated
+system.cpu0.numCycles 1462656 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 500001 # Number of instructions committed
@@ -72,18 +109,18 @@ system.cpu0.num_mem_refs 180793 # nu
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_store_insts 56350 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 1457840 # Number of busy cycles
+system.cpu0.num_busy_cycles 1462656 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use
+system.cpu0.icache.tagsinuse 216.308996 # Cycle average of tags in use
system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 216.390931 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.422639 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.422639 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::cpu0.inst 216.308996 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.422479 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.422479 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
@@ -96,12 +133,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 463 #
system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23474000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 23474000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 23474000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 23474000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 23474000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 23474000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23730000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 23730000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 23730000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 23730000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 23730000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 23730000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
@@ -109,17 +146,23 @@ system.cpu0.icache.demand_accesses::total 500020 # n
system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50699.784017 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50699.784017 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50699.784017 # average overall miss latency
+system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51252.699784 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 51252.699784 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51252.699784 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 51252.699784 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51252.699784 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 51252.699784 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
@@ -128,28 +171,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 463
system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22085000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 22085000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22085000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 22085000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22085000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 22085000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22341000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 22341000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22341000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 22341000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22341000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 22341000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47699.784017 # average overall mshr miss latency
+system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48252.699784 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 48252.699784 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48252.699784 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 48252.699784 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse 273.374896 # Cycle average of tags in use
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 273.518805 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.534216 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.534216 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::cpu0.data 273.374896 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.533935 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.533935 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
@@ -166,14 +215,14 @@ system.cpu0.dcache.demand_misses::cpu0.data 463 #
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
system.cpu0.dcache.overall_misses::total 463 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17785000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 17785000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7793000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 7793000 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 25578000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 25578000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 25578000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 25578000 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17838000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 17838000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7843000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 7843000 # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 25681000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 25681000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 25681000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 25681000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
@@ -183,19 +232,27 @@ system.cpu0.dcache.demand_accesses::total 180775 # n
system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 54891.975309 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 56064.748201 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 55244.060475 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 55244.060475 # average overall miss latency
+system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 55055.555556 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 55055.555556 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 56424.460432 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 56424.460432 # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 55466.522678 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 55466.522678 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 55466.522678 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 55466.522678 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
@@ -208,22 +265,30 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 463
system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16813000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16813000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7376000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7376000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24189000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 24189000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24189000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 24189000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16866000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16866000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7426000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7426000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24292000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 24292000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24292000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 24292000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51891.975309 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53064.748201 # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52244.060475 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52244.060475 # average overall mshr miss latency
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52055.555556 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52055.555556 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53424.460432 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53424.460432 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52466.522678 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52466.522678 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52466.522678 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52466.522678 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
@@ -258,7 +323,7 @@ system.cpu1.itb.data_misses 0 # DT
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu1.numCycles 1457840 # number of cpu cycles simulated
+system.cpu1.numCycles 1462656 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 499993 # Number of instructions committed
@@ -277,18 +342,18 @@ system.cpu1.num_mem_refs 180792 # nu
system.cpu1.num_load_insts 124443 # Number of load instructions
system.cpu1.num_store_insts 56349 # Number of store instructions
system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_busy_cycles 1457840 # Number of busy cycles
+system.cpu1.num_busy_cycles 1462656 # Number of busy cycles
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0 # Percentage of idle cycles
system.cpu1.icache.replacements 152 # number of replacements
-system.cpu1.icache.tagsinuse 216.386658 # Cycle average of tags in use
+system.cpu1.icache.tagsinuse 216.301902 # Cycle average of tags in use
system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 216.386658 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.422630 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.422630 # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::cpu1.inst 216.301902 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.422465 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.422465 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits
@@ -301,12 +366,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 463 #
system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
system.cpu1.icache.overall_misses::total 463 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23473000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 23473000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 23473000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 23473000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 23473000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 23473000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23746000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 23746000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 23746000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 23746000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 23746000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 23746000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 500012 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 500012 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 500012 # number of demand (read+write) accesses
@@ -314,17 +379,23 @@ system.cpu1.icache.demand_accesses::total 500012 # n
system.cpu1.icache.overall_accesses::cpu1.inst 500012 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 500012 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 50697.624190 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 50697.624190 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 50697.624190 # average overall miss latency
+system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 51287.257019 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 51287.257019 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 51287.257019 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 51287.257019 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 51287.257019 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 51287.257019 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
@@ -333,28 +404,34 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 463
system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22084000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 22084000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22084000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 22084000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22084000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 22084000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22357000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 22357000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22357000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 22357000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22357000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 22357000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47697.624190 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47697.624190 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47697.624190 # average overall mshr miss latency
+system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48287.257019 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48287.257019 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 48287.257019 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 48287.257019 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48287.257019 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 48287.257019 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 61 # number of replacements
-system.cpu1.dcache.tagsinuse 273.512548 # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse 273.364257 # Cycle average of tags in use
system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 273.512548 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.534204 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.534204 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::cpu1.data 273.364257 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.533915 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.533915 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
@@ -371,14 +448,14 @@ system.cpu1.dcache.demand_misses::cpu1.data 463 #
system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
system.cpu1.dcache.overall_misses::total 463 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17785000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 17785000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7803000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 7803000 # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 25588000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 25588000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 25588000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 25588000 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17819000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 17819000 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7855000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 7855000 # number of WriteReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 25674000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 25674000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 25674000 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 25674000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses)
@@ -388,19 +465,27 @@ system.cpu1.dcache.demand_accesses::total 180774 # n
system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 54891.975309 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 56136.690647 # average WriteReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 55265.658747 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 55265.658747 # average overall miss latency
+system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 54996.913580 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 54996.913580 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 56510.791367 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 56510.791367 # average WriteReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 55451.403888 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 55451.403888 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 55451.403888 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 55451.403888 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
@@ -413,43 +498,51 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 463
system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16813000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16813000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7386000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7386000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24199000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 24199000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24199000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 24199000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16847000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16847000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7438000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7438000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24285000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 24285000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24285000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 24285000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51891.975309 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53136.690647 # average WriteReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52265.658747 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52265.658747 # average overall mshr miss latency
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51996.913580 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51996.913580 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53510.791367 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53510.791367 # average WriteReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52451.403888 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52451.403888 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52451.403888 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52451.403888 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 124433 # DTB read hits
+system.cpu2.dtb.read_hits 124431 # DTB read hits
system.cpu2.dtb.read_misses 8 # DTB read misses
system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_accesses 124441 # DTB read accesses
+system.cpu2.dtb.read_accesses 124439 # DTB read accesses
system.cpu2.dtb.write_hits 56339 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
system.cpu2.dtb.write_acv 0 # DTB write access violations
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
-system.cpu2.dtb.data_hits 180772 # DTB hits
+system.cpu2.dtb.data_hits 180770 # DTB hits
system.cpu2.dtb.data_misses 18 # DTB misses
system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_accesses 180790 # DTB accesses
-system.cpu2.itb.fetch_hits 500001 # ITB hits
+system.cpu2.dtb.data_accesses 180788 # DTB accesses
+system.cpu2.itb.fetch_hits 499999 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_accesses 500014 # ITB accesses
+system.cpu2.itb.fetch_accesses 500012 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
@@ -463,73 +556,79 @@ system.cpu2.itb.data_misses 0 # DT
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.workload.num_syscalls 18 # Number of system calls
-system.cpu2.numCycles 1457840 # number of cpu cycles simulated
+system.cpu2.numCycles 1462656 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 499982 # Number of instructions committed
-system.cpu2.committedOps 499982 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 474671 # Number of integer alu accesses
+system.cpu2.committedInsts 499980 # Number of instructions committed
+system.cpu2.committedOps 499980 # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses 474669 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 474671 # number of integer instructions
+system.cpu2.num_int_insts 474669 # number of integer instructions
system.cpu2.num_fp_insts 32 # number of float instructions
-system.cpu2.num_int_register_reads 654261 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 371526 # number of times the integer registers were written
+system.cpu2.num_int_register_reads 654257 # number of times the integer registers were read
+system.cpu2.num_int_register_writes 371524 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu2.num_mem_refs 180789 # number of memory refs
-system.cpu2.num_load_insts 124440 # Number of load instructions
+system.cpu2.num_mem_refs 180788 # number of memory refs
+system.cpu2.num_load_insts 124439 # Number of load instructions
system.cpu2.num_store_insts 56349 # Number of store instructions
system.cpu2.num_idle_cycles 0 # Number of idle cycles
-system.cpu2.num_busy_cycles 1457840 # Number of busy cycles
+system.cpu2.num_busy_cycles 1462656 # Number of busy cycles
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0 # Percentage of idle cycles
system.cpu2.icache.replacements 152 # number of replacements
-system.cpu2.icache.tagsinuse 216.383557 # Cycle average of tags in use
-system.cpu2.icache.total_refs 499538 # Total number of references to valid blocks.
+system.cpu2.icache.tagsinuse 216.295599 # Cycle average of tags in use
+system.cpu2.icache.total_refs 499536 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs 1078.915767 # Average number of references to valid blocks.
+system.cpu2.icache.avg_refs 1078.911447 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst 216.383557 # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst 0.422624 # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total 0.422624 # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst 499538 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 499538 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 499538 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 499538 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 499538 # number of overall hits
-system.cpu2.icache.overall_hits::total 499538 # number of overall hits
+system.cpu2.icache.occ_blocks::cpu2.inst 216.295599 # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst 0.422452 # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total 0.422452 # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst 499536 # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total 499536 # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst 499536 # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total 499536 # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst 499536 # number of overall hits
+system.cpu2.icache.overall_hits::total 499536 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
system.cpu2.icache.overall_misses::total 463 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23483000 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 23483000 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 23483000 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 23483000 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 23483000 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 23483000 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 500001 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 500001 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 500001 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 500001 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 500001 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 500001 # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23755000 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total 23755000 # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst 23755000 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total 23755000 # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst 23755000 # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total 23755000 # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst 499999 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total 499999 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst 499999 # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total 499999 # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst 499999 # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total 499999 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 50719.222462 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 50719.222462 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 50719.222462 # average overall miss latency
+system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 51306.695464 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 51306.695464 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 51306.695464 # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 51306.695464 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 51306.695464 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 51306.695464 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
@@ -538,36 +637,42 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 463
system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22094000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 22094000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22094000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 22094000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22094000 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 22094000 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22366000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total 22366000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22366000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 22366000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22366000 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 22366000 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47719.222462 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47719.222462 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47719.222462 # average overall mshr miss latency
+system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48306.695464 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48306.695464 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48306.695464 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 48306.695464 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48306.695464 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 48306.695464 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 61 # number of replacements
-system.cpu2.dcache.tagsinuse 273.508588 # Cycle average of tags in use
-system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks.
+system.cpu2.dcache.tagsinuse 273.355742 # Cycle average of tags in use
+system.cpu2.dcache.total_refs 180307 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
+system.cpu2.dcache.avg_refs 389.431965 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data 273.508588 # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data 0.534196 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total 0.534196 # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
+system.cpu2.dcache.occ_blocks::cpu2.data 273.355742 # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data 0.533898 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total 0.533898 # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits::cpu2.data 124107 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 180309 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 180309 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 180309 # number of overall hits
-system.cpu2.dcache.overall_hits::total 180309 # number of overall hits
+system.cpu2.dcache.demand_hits::cpu2.data 180307 # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total 180307 # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data 180307 # number of overall hits
+system.cpu2.dcache.overall_hits::total 180307 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
@@ -576,36 +681,44 @@ system.cpu2.dcache.demand_misses::cpu2.data 463 #
system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
system.cpu2.dcache.overall_misses::total 463 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17794000 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 17794000 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7797000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 7797000 # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 25591000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 25591000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 25591000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 25591000 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 124433 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17835000 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total 17835000 # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7847000 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total 7847000 # number of WriteReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data 25682000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total 25682000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data 25682000 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total 25682000 # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data 124431 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total 124431 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 180772 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 180772 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
+system.cpu2.dcache.demand_accesses::cpu2.data 180770 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total 180770 # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data 180770 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total 180770 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 54919.753086 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 56093.525180 # average WriteReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 55272.138229 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 55272.138229 # average overall miss latency
+system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 55046.296296 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 55046.296296 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 56453.237410 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 56453.237410 # average WriteReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 55468.682505 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 55468.682505 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 55468.682505 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 55468.682505 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
@@ -618,43 +731,51 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 463
system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16822000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16822000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7380000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7380000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24202000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 24202000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24202000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 24202000 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16863000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16863000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7430000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7430000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24293000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 24293000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24293000 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 24293000 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51919.753086 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53093.525180 # average WriteReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52272.138229 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52272.138229 # average overall mshr miss latency
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52046.296296 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52046.296296 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53453.237410 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53453.237410 # average WriteReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52468.682505 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52468.682505 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52468.682505 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52468.682505 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.fetch_acv 0 # ITB acv
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
-system.cpu3.dtb.read_hits 124431 # DTB read hits
+system.cpu3.dtb.read_hits 124394 # DTB read hits
system.cpu3.dtb.read_misses 8 # DTB read misses
system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_accesses 124439 # DTB read accesses
-system.cpu3.dtb.write_hits 56339 # DTB write hits
+system.cpu3.dtb.read_accesses 124402 # DTB read accesses
+system.cpu3.dtb.write_hits 56326 # DTB write hits
system.cpu3.dtb.write_misses 10 # DTB write misses
system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_accesses 56349 # DTB write accesses
-system.cpu3.dtb.data_hits 180770 # DTB hits
+system.cpu3.dtb.write_accesses 56336 # DTB write accesses
+system.cpu3.dtb.data_hits 180720 # DTB hits
system.cpu3.dtb.data_misses 18 # DTB misses
system.cpu3.dtb.data_acv 0 # DTB access violations
-system.cpu3.dtb.data_accesses 180788 # DTB accesses
-system.cpu3.itb.fetch_hits 499997 # ITB hits
+system.cpu3.dtb.data_accesses 180738 # DTB accesses
+system.cpu3.itb.fetch_hits 499874 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_accesses 500010 # ITB accesses
+system.cpu3.itb.fetch_accesses 499887 # ITB accesses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.read_acv 0 # DTB read access violations
@@ -668,73 +789,79 @@ system.cpu3.itb.data_misses 0 # DT
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.cpu3.numCycles 1457840 # number of cpu cycles simulated
+system.cpu3.numCycles 1462656 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 499978 # Number of instructions committed
-system.cpu3.committedOps 499978 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 474667 # Number of integer alu accesses
+system.cpu3.committedInsts 499855 # Number of instructions committed
+system.cpu3.committedOps 499855 # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses 474546 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu3.num_func_calls 14357 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 474667 # number of integer instructions
+system.cpu3.num_func_calls 14355 # number of times a function call or return occured
+system.cpu3.num_conditional_control_insts 38164 # number of instructions that are conditional controls
+system.cpu3.num_int_insts 474546 # number of integer instructions
system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 371523 # number of times the integer registers were written
+system.cpu3.num_int_register_reads 654094 # number of times the integer registers were read
+system.cpu3.num_int_register_writes 371430 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu3.num_mem_refs 180787 # number of memory refs
-system.cpu3.num_load_insts 124438 # Number of load instructions
-system.cpu3.num_store_insts 56349 # Number of store instructions
+system.cpu3.num_mem_refs 180738 # number of memory refs
+system.cpu3.num_load_insts 124402 # Number of load instructions
+system.cpu3.num_store_insts 56336 # Number of store instructions
system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_busy_cycles 1457840 # Number of busy cycles
+system.cpu3.num_busy_cycles 1462656 # Number of busy cycles
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0 # Percentage of idle cycles
system.cpu3.icache.replacements 152 # number of replacements
-system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use
-system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks.
+system.cpu3.icache.tagsinuse 216.273354 # Cycle average of tags in use
+system.cpu3.icache.total_refs 499411 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs 1078.907127 # Average number of references to valid blocks.
+system.cpu3.icache.avg_refs 1078.641469 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst 216.381810 # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst 0.422621 # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total 0.422621 # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst 499534 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 499534 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 499534 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 499534 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 499534 # number of overall hits
-system.cpu3.icache.overall_hits::total 499534 # number of overall hits
+system.cpu3.icache.occ_blocks::cpu3.inst 216.273354 # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst 0.422409 # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total 0.422409 # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst 499411 # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total 499411 # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst 499411 # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total 499411 # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst 499411 # number of overall hits
+system.cpu3.icache.overall_hits::total 499411 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
system.cpu3.icache.overall_misses::total 463 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23492000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 23492000 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 23492000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 23492000 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst 23492000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total 23492000 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 499997 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 499997 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 499997 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 499997 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 499997 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 499997 # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23893000 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total 23893000 # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst 23893000 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total 23893000 # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst 23893000 # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total 23893000 # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 499874 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 499874 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst 499874 # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total 499874 # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst 499874 # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total 499874 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 50738.660907 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 50738.660907 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 50738.660907 # average overall miss latency
+system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 51604.751620 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 51604.751620 # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 51604.751620 # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 51604.751620 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 51604.751620 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 51604.751620 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
@@ -743,36 +870,42 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 463
system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22103000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 22103000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22103000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 22103000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22103000 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 22103000 # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22504000 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total 22504000 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22504000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total 22504000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22504000 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total 22504000 # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47738.660907 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47738.660907 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47738.660907 # average overall mshr miss latency
+system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48604.751620 # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48604.751620 # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48604.751620 # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 48604.751620 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48604.751620 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 48604.751620 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 61 # number of replacements
-system.cpu3.dcache.tagsinuse 273.505617 # Cycle average of tags in use
-system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks.
+system.cpu3.dcache.tagsinuse 273.321403 # Cycle average of tags in use
+system.cpu3.dcache.total_refs 180257 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks.
+system.cpu3.dcache.avg_refs 389.323974 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data 273.505617 # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data 0.534191 # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total 0.534191 # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 180307 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 180307 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 180307 # number of overall hits
-system.cpu3.dcache.overall_hits::total 180307 # number of overall hits
+system.cpu3.dcache.occ_blocks::cpu3.data 273.321403 # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data 0.533831 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total 0.533831 # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits::cpu3.data 124070 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total 124070 # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data 56187 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total 56187 # number of WriteReq hits
+system.cpu3.dcache.demand_hits::cpu3.data 180257 # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total 180257 # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data 180257 # number of overall hits
+system.cpu3.dcache.overall_hits::total 180257 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
@@ -781,36 +914,44 @@ system.cpu3.dcache.demand_misses::cpu3.data 463 #
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
system.cpu3.dcache.overall_misses::total 463 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17791000 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 17791000 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7797000 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 7797000 # number of WriteReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data 25588000 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total 25588000 # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data 25588000 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total 25588000 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 124431 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 124431 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 180770 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 180770 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 180770 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 180770 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 54910.493827 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 56093.525180 # average WriteReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 55265.658747 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 55265.658747 # average overall miss latency
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17828000 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total 17828000 # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7891000 # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total 7891000 # number of WriteReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data 25719000 # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total 25719000 # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data 25719000 # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total 25719000 # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data 124394 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total 124394 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data 56326 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total 56326 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data 180720 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total 180720 # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data 180720 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total 180720 # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002605 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total 0.002605 # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002468 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total 0.002468 # miss rate for WriteReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002562 # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total 0.002562 # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002562 # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total 0.002562 # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 55024.691358 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 55024.691358 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 56769.784173 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 56769.784173 # average WriteReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 55548.596112 # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 55548.596112 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 55548.596112 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 55548.596112 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
@@ -823,48 +964,56 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 463
system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16819000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16819000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7380000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7380000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24199000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total 24199000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24199000 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total 24199000 # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51910.493827 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53093.525180 # average WriteReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52265.658747 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52265.658747 # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16856000 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16856000 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7474000 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7474000 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24330000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total 24330000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24330000 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total 24330000 # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002605 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002605 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002468 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002468 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002562 # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total 0.002562 # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002562 # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total 0.002562 # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 52024.691358 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52024.691358 # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53769.784173 # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53769.784173 # average WriteReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52548.596112 # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52548.596112 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52548.596112 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52548.596112 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
-system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use
+system.l2c.tagsinuse 1942.337189 # Cycle average of tags in use
system.l2c.total_refs 332 # Total number of references to valid blocks.
system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 17.228456 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 265.029263 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 216.501106 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 265.023656 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 216.496016 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst 265.019384 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data 216.492927 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst 265.017115 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data 216.490615 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.003304 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.029652 # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 17.198857 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 264.924767 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 216.395624 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 264.914917 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 216.387214 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst 264.906837 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data 216.380232 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst 264.874926 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data 216.353815 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.000262 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.004042 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.003302 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.004042 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.003302 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst 0.004042 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data 0.003302 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.inst 0.004042 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.data 0.003301 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.029638 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
@@ -926,38 +1075,38 @@ system.l2c.overall_misses::cpu2.data 454 # nu
system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
system.l2c.overall_misses::cpu3.data 454 # number of overall misses
system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 20968000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 16386000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 20958000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 16380000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 20961000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 16382000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst 20959000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data 16381000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 149375000 # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 7228000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 7228000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 7230000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data 7229000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 28915000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 20968000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 23614000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 20958000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 23608000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 20961000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 23612000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst 20959000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data 23610000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 178290000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 20968000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 23614000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 20958000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 23608000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 20961000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 23612000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst 20959000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data 23610000 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 178290000 # number of overall miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 21065000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 16433000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 21096000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 16411000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 21093000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 16406000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst 21265000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.data 16419000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 150188000 # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 7238000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 7280000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 7249000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data 7275000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 29042000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 21065000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 23671000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 21096000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 23691000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 21093000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 23655000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst 21265000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data 23694000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 179230000 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 21065000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 23671000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 21096000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 23691000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 21093000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 23655000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst 21265000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data 23694000 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 179230000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
@@ -1000,10 +1149,12 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
@@ -1012,6 +1163,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
@@ -1020,40 +1172,45 @@ system.l2c.overall_miss_rate::cpu2.inst 0.870410 # mi
system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52029.776675 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52019.047619 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52004.962779 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52012.406948 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 52006.349206 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52007.444169 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.data 52003.174603 # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52014.388489 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52007.194245 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52029.776675 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52013.215859 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52004.962779 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 52012.406948 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 52008.810573 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 52007.444169 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 52004.405286 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52029.776675 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52013.215859 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52004.962779 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 52012.406948 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 52008.810573 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 52007.444169 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 52004.405286 # average overall miss latency
+system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52270.471464 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52168.253968 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52347.394541 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52098.412698 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52339.950372 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 52082.539683 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52766.749380 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.data 52123.809524 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52293.871866 # average ReadReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52071.942446 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52374.100719 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52151.079137 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52338.129496 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52233.812950 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52270.471464 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52138.766520 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52347.394541 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52182.819383 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 52339.950372 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 52103.524229 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 52766.749380 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 52189.427313 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52284.130688 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52270.471464 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52138.766520 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52347.394541 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52182.819383 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 52339.950372 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 52103.524229 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 52766.749380 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 52189.427313 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52284.130688 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadReq_mshr_misses::cpu0.inst 403 # number of ReadReq MSHR misses
@@ -1088,38 +1245,38 @@ system.l2c.overall_mshr_misses::cpu2.data 454 # n
system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 16132000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12606000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 16122000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12600000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 16125000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 12602000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 16123000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.data 12601000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 114911000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5560000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5560000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5562000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5561000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 22243000 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 16132000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 18166000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 16122000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 18160000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 16125000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 18164000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst 16123000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data 18162000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 137154000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 16132000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 18166000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 16122000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 18160000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 16125000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 18164000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst 16123000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data 18162000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 137154000 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 16229000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12653000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 16260000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12631000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 16257000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 12626000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 16429000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.data 12639000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 115724000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5570000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5612000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5581000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5607000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 22370000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 16229000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 18223000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 16260000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 18243000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 16257000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 18207000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst 16429000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data 18246000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 138094000 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 16229000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 18223000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 16260000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 18243000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 16257000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 18207000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst 16429000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data 18246000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 138094000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadReq accesses
@@ -1128,10 +1285,12 @@ system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.870410
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.912325 # mshr miss rate for ReadReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
@@ -1140,6 +1299,7 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 #
system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
@@ -1148,34 +1308,39 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410
system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40029.776675 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40019.047619 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.962779 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40012.406948 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40006.349206 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40007.444169 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40003.174603 # average ReadReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40014.388489 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40007.194245 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40029.776675 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.215859 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.962779 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40012.406948 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40008.810573 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40007.444169 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40004.405286 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40029.776675 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.215859 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.962779 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40012.406948 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40008.810573 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40007.444169 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40004.405286 # average overall mshr miss latency
+system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40270.471464 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40168.253968 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40347.394541 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40098.412698 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40339.950372 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40082.539683 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40766.749380 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40123.809524 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40293.871866 # average ReadReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40071.942446 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40374.100719 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40151.079137 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40338.129496 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40233.812950 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40270.471464 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40138.766520 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40347.394541 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40182.819383 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40339.950372 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40103.524229 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40766.749380 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40189.427313 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40284.130688 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40270.471464 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40138.766520 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40347.394541 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40182.819383 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40339.950372 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40103.524229 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40766.749380 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40189.427313 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40284.130688 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------