diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/se | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/se')
49 files changed, 22196 insertions, 21856 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 6eb08a8bc..b5554ceae 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37930000 # Number of ticks simulated -final_tick 37930000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37623000 # Number of ticks simulated +final_tick 37623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161486 # Simulator instruction rate (inst/s) -host_op_rate 161429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 956403338 # Simulator tick rate (ticks/s) -host_mem_usage 294064 # Number of bytes of host memory used +host_inst_rate 152308 # Simulator instruction rate (inst/s) +host_op_rate 152258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 894784408 # Simulator tick rate (ticks/s) +host_mem_usage 293572 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 614184023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 285156868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 899340891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 614184023 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 614184023 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 614184023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 285156868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 899340891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 619195705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 287483720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 906679425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 619195705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 619195705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 619195705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 287483720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 906679425 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37824500 # Total gap between requests +system.physmem.totGap 37518500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,32 +187,32 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.714286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 247.680361 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.730884 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19 22.62% 22.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 23.81% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.494057 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.812732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20 23.81% 23.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 22.62% 46.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.57% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.38% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 7.14% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 10.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.38% 73.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5 5.95% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.57% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 7.14% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 9.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation -system.physmem.totQLat 3251500 # Total ticks spent queuing -system.physmem.totMemAccLat 13245250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3336750 # Total ticks spent queuing +system.physmem.totMemAccLat 13330500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6260.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 899.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25010.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 906.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 899.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 906.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.03 # Data bus utilization in percentage -system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.08 # Data bus utilization in percentage +system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,43 +220,43 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70965.29 # Average gap between requests +system.physmem.avgGap 70391.18 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) -system.physmem_0.averagePower 825.080242 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 372750 # Time in different power states +system.physmem_0.actBackEnergy 21178350 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 265500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25872240 # Total energy per rank (pJ) +system.physmem_0.averagePower 823.825505 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 435750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30032750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20293425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1041750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25416240 # Total energy per rank (pJ) -system.physmem_1.averagePower 809.305525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1595750 # Time in different power states +system.physmem_1.actBackEnergy 20558475 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 809250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25483875 # Total energy per rank (pJ) +system.physmem_1.averagePower 811.459163 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1209750 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29169000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1964 # Number of BP lookups -system.cpu.branchPred.condPredicted 1204 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1965 # Number of BP lookups +system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1555 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1556 # Number of BTB lookups system.cpu.branchPred.BTBHits 382 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.565916 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 24.550129 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 2255 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2269 # DTB accesses -system.cpu.itb.fetch_hits 2638 # ITB hits +system.cpu.itb.fetch_hits 2639 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2655 # ITB accesses +system.cpu.itb.fetch_accesses 2656 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75860 # number of cpu cycles simulated +system.cpu.numCycles 75246 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1115 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.853125 # CPI: cycles per instruction -system.cpu.ipc 0.084366 # IPC: instructions per cycle -system.cpu.tickCycles 12560 # Number of cycles that the object actually ticked -system.cpu.idleCycles 63300 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.757188 # CPI: cycles per instruction +system.cpu.ipc 0.085054 # IPC: instructions per cycle +system.cpu.tickCycles 12577 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62669 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.899066 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1976 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.998872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.692308 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.899066 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025366 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025366 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.998872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025390 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025390 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id @@ -321,28 +321,28 @@ system.cpu.dcache.tags.tag_accesses 4573 # Nu system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1976 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1976 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1976 # number of overall hits -system.cpu.dcache.overall_hits::total 1976 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits +system.cpu.dcache.overall_hits::total 1975 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 124 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 226 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses -system.cpu.dcache.overall_misses::total 226 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8144750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8144750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9233750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9233750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17378500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17378500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17378500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17378500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses +system.cpu.dcache.overall_misses::total 227 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8109500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8109500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9137500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9137500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17247000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17247000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17247000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17247000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -353,20 +353,20 @@ system.cpu.dcache.overall_accesses::cpu.data 2202 system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.102634 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.102634 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102634 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102634 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79850.490196 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79850.490196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74465.725806 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74465.725806 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76896.017699 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76896.017699 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.103088 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.103088 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.103088 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.103088 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79504.901961 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79504.901961 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73100 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75977.973568 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75977.973568 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,12 +377,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 51 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7564250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7564250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12928500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12928500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12928500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12928500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7616500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7616500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5372000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5372000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12988500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12988500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12988500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12988500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78794.270833 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78794.270833 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79338.541667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79338.541667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73589.041096 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73589.041096 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76855.029586 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76855.029586 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76855.029586 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76855.029586 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.739822 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2273 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.991805 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.227397 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.739822 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085810 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085810 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.991805 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085933 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5641 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5641 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2273 # number of overall hits -system.cpu.icache.overall_hits::total 2273 # number of overall hits +system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5643 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits +system.cpu.icache.overall_hits::total 2274 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28333750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28333750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28333750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28333750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28333750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2638 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2638 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2638 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2638 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2638 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2638 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138362 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138362 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138362 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138362 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138362 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138362 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77626.712329 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77626.712329 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77626.712329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77626.712329 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28165000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28165000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28165000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28165000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28165000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28165000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77164.383562 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77164.383562 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77164.383562 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77164.383562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77164.383562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77164.383562 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,103 +481,108 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27622750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27622750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27622750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138362 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138362 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138362 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75678.767123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75678.767123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27800000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27800000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27800000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27800000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27800000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27800000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76164.383562 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76164.383562 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76164.383562 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76164.383562 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76164.383562 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76164.383562 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.394654 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.662872 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.771828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.622826 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007123 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.005347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.657524 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005371 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007131 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 96 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 364 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 364 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7466750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 34713500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27246750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12757000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40003750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27246750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12757000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40003750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5261500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27241500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27241500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27241500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12732500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 39974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27241500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12732500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 39974000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997260 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997260 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997260 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997260 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74853.708791 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77778.645833 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75464.130435 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75053.939962 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75053.939962 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72075.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72075.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74839.285714 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74839.285714 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.916667 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.916667 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74839.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75340.236686 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74998.123827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74839.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75340.236686 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74998.123827 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -586,55 +591,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 364 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 364 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6260250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28947000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10638500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33325250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10638500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33325250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11042500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 34644000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11042500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 34644000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997260 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62326.236264 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65210.937500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62928.260870 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62075.342466 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62075.342466 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64839.285714 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64839.285714 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67822.916667 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67822.916667 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) @@ -655,14 +665,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 629250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 286000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 460 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 460 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 460 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) @@ -678,9 +688,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2833000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 4b8e35ff8..96f652b92 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22074000 # Number of ticks simulated -final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21947000 # Number of ticks simulated +final_tick 21947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27311 # Simulator instruction rate (inst/s) -host_op_rate 27309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 94600483 # Simulator tick rate (ticks/s) -host_mem_usage 225500 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 95577 # Simulator instruction rate (inst/s) +host_op_rate 95558 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 329070081 # Simulator tick rate (ticks/s) +host_mem_usage 294868 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 907492978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 501585576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1409078554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 907492978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 907492978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 907492978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 501585576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1409078554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 912744339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 504488085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1417232424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 912744339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 912744339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 912744339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 504488085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1417232424 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 486 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21941500 # Total gap between requests +system.physmem.totGap 21815000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,8 +188,8 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.818416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.662840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.725130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.981029 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation @@ -199,19 +199,19 @@ system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # By system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation -system.physmem.totQLat 4363750 # Total ticks spent queuing -system.physmem.totMemAccLat 13476250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4379250 # Total ticks spent queuing +system.physmem.totMemAccLat 13491750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8978.91 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9010.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27728.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1409.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27760.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1417.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1409.08 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1417.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.01 # Data bus utilization in percentage -system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.07 # Data bus utilization in percentage +system.physmem.busUtilRead 11.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -219,7 +219,7 @@ system.physmem.readRowHits 390 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45147.12 # Average gap between requests +system.physmem.avgGap 44886.83 # Average gap between requests system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) @@ -230,55 +230,55 @@ system.physmem_0.actBackEnergy 10785825 # En system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) system.physmem_0.averagePower 873.750829 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 118250 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10123200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 619500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13518075 # Total energy per rank (pJ) -system.physmem_1.averagePower 853.818096 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 963500 # Time in different power states +system.physmem_1.actBackEnergy 10129185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 614250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13534410 # Total energy per rank (pJ) +system.physmem_1.averagePower 854.849834 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 953500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14362750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14372750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2808 # Number of BP lookups -system.cpu.branchPred.condPredicted 1660 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 676 # Number of BTB hits +system.cpu.branchPred.lookups 2810 # Number of BP lookups +system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 478 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2116 # Number of BTB lookups +system.cpu.branchPred.BTBHits 679 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.007576 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 398 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 32.088847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 396 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 2105 # DTB read hits -system.cpu.dtb.read_misses 56 # DTB read misses +system.cpu.dtb.read_misses 55 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2161 # DTB read accesses +system.cpu.dtb.read_accesses 2160 # DTB read accesses system.cpu.dtb.write_hits 1074 # DTB write hits system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1104 # DTB write accesses system.cpu.dtb.data_hits 3179 # DTB hits -system.cpu.dtb.data_misses 86 # DTB misses +system.cpu.dtb.data_misses 85 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3265 # DTB accesses -system.cpu.itb.fetch_hits 2195 # ITB hits +system.cpu.dtb.data_accesses 3264 # DTB accesses +system.cpu.itb.fetch_hits 2194 # ITB hits system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2229 # ITB accesses +system.cpu.itb.fetch_accesses 2228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,131 +292,131 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 44149 # number of cpu cycles simulated +system.cpu.numCycles 43895 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8603 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16272 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4302 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 8597 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2810 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1075 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4298 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1038 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 735 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2195 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 341 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14185 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.147127 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.556854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 740 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2194 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14179 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.148036 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.557344 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11330 79.87% 79.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 287 2.02% 81.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 214 1.51% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11320 79.84% 79.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 289 2.04% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 216 1.52% 83.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 242 1.71% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 209 1.47% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 241 1.70% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 178 1.25% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1280 9.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 243 1.71% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 208 1.47% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 242 1.71% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.23% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1282 9.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14185 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.063603 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.368570 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8626 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2413 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 199 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14179 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064016 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.370840 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8623 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2500 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2414 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 442 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14877 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14886 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8799 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1077 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 424 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2422 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1020 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14259 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 442 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8796 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1074 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 427 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2425 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14276 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 32 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 922 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10782 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17904 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17895 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 33 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10794 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17927 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17918 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6212 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6224 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 534 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 538 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12940 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10742 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10735 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3553 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6595 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14185 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.757279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.490412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.757106 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.490778 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10181 71.77% 71.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1265 8.92% 80.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 910 6.42% 87.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 677 4.77% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 530 3.74% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 330 2.33% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 213 1.50% 99.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 54 0.38% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 25 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10173 71.75% 71.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1278 9.01% 80.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 898 6.33% 87.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 679 4.79% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 528 3.72% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 333 2.35% 97.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 209 1.47% 99.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.39% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14179 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29 19.86% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 74 50.68% 70.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 43 29.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 20.14% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 50.69% 70.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 42 29.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7248 67.47% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7243 67.47% 67.49% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued @@ -445,23 +445,23 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2358 21.95% 89.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1131 10.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2356 21.95% 89.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10742 # Type of FU issued -system.cpu.iq.rate 0.243312 # Inst issue rate -system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013592 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35814 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19563 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9787 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10735 # Type of FU issued +system.cpu.iq.rate 0.244561 # Inst issue rate +system.cpu.iq.fu_busy_cnt 144 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013414 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35792 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19571 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9784 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10875 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10866 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 71 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed @@ -472,57 +472,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1035 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13050 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 442 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1033 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13054 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 472 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10248 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2164 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 395 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 476 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10242 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 493 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 3270 # number of memory reference insts executed -system.cpu.iew.exec_branches 1599 # Number of branches executed +system.cpu.iew.exec_refs 3269 # number of memory reference insts executed +system.cpu.iew.exec_branches 1598 # Number of branches executed system.cpu.iew.exec_stores 1106 # Number of stores executed -system.cpu.iew.exec_rate 0.232123 # Inst execution rate -system.cpu.iew.wb_sent 9960 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9797 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5308 # num instructions producing a value -system.cpu.iew.wb_consumers 7306 # num instructions consuming a value +system.cpu.iew.exec_rate 0.233330 # Inst execution rate +system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9794 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5300 # num instructions producing a value +system.cpu.iew.wb_consumers 7297 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.221908 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.726526 # average fanout of values written-back +system.cpu.iew.wb_rate 0.223123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.726326 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6660 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6664 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12983 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492105 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404730 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.405132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10525 81.07% 81.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1166 8.98% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 505 3.89% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10520 81.06% 81.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1167 8.99% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 504 3.88% 93.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 137 1.06% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 75 0.58% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 136 1.05% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 76 0.59% 97.18% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12978 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,101 +569,101 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 25491 # The number of ROB reads -system.cpu.rob.rob_writes 27316 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25490 # The number of ROB reads +system.cpu.rob.rob_writes 27321 # The number of ROB writes +system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29716 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144329 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144329 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13019 # number of integer regfile reads -system.cpu.int_regfile_writes 7461 # number of integer regfile writes +system.cpu.cpi 6.888732 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.888732 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145165 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145165 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13013 # number of integer regfile reads +system.cpu.int_regfile_writes 7460 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.596270 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2347 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.548347 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2343 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.566474 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.543353 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.596270 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026269 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 107.548347 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026257 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026257 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5893 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5893 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2347 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2347 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2347 # number of overall hits -system.cpu.dcache.overall_hits::total 2347 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 157 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 157 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses -system.cpu.dcache.overall_misses::total 513 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12056250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12056250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24043225 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24043225 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36099475 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36099475 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36099475 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36099475 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 5891 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5891 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1835 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1835 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2343 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2343 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2343 # number of overall hits +system.cpu.dcache.overall_hits::total 2343 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 159 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 516 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 516 # number of overall misses +system.cpu.dcache.overall_misses::total 516 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11993500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11993500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24175975 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24175975 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36169475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36169475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36169475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36169475 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1994 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078697 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078697 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.179371 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.179371 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.179371 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.179371 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70369.346979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70369.346979 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2245 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2859 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2859 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2859 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2859 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079739 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079739 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.180483 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.180483 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.180483 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.180483 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75430.817610 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75430.817610 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67719.817927 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67719.817927 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70095.881783 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70095.881783 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2284 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 41 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.078947 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.707317 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 340 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 340 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 340 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 340 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 343 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 343 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 343 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses @@ -672,82 +672,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173 system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8557250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8557250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5645250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5645250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14202500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14202500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14202500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14202500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8588000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8588000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5911000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5911000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14499000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14499000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050652 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.060490 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.060490 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.060511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.060511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85029.702970 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85029.702970 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82097.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82097.222222 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.400693 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1716 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.228991 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1714 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.464968 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.458599 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.400693 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077344 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077344 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.228991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077260 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077260 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4704 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4704 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1716 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1716 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1716 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1716 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1716 # number of overall hits -system.cpu.icache.overall_hits::total 1716 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses -system.cpu.icache.overall_misses::total 479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34067500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34067500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34067500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34067500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34067500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34067500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2195 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2195 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218223 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.218223 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.218223 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.218223 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.218223 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.218223 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71122.129436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71122.129436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71122.129436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71122.129436 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4702 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4702 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1714 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1714 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1714 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1714 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1714 # number of overall hits +system.cpu.icache.overall_hits::total 1714 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses +system.cpu.icache.overall_misses::total 480 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33574500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33574500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33574500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33574500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33574500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33574500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2194 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2194 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2194 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2194 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218778 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.218778 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.218778 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.218778 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.218778 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.218778 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69946.875000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69946.875000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69946.875000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69946.875000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69946.875000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69946.875000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,115 +756,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall 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of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24276250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24276250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24276250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24276250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24276250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24276250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for 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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64002.396166 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71170.792079 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65751.207729 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64920.138889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64920.138889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) @@ -942,14 +952,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 535750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 285500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 414 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 414 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) @@ -965,9 +975,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 486 # Request fanout histogram -system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 594500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2581250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2585500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index aeda1c330..88733611d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000139 # Number of seconds simulated -sim_ticks 138637 # Number of ticks simulated -final_tick 138637 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 138724 # Number of ticks simulated +final_tick 138724 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 45640 # Simulator instruction rate (inst/s) -host_op_rate 45635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 990010 # Simulator tick rate (ticks/s) -host_mem_usage 451208 # Number of bytes of host memory used +host_inst_rate 45032 # Simulator instruction rate (inst/s) +host_op_rate 45028 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 977453 # Simulator tick rate (ticks/s) +host_mem_usage 451780 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1460 # system.mem_ctrls.num_reads::total 1460 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 673990349 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 673990349 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 127873511 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 127873511 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 801863860 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 801863860 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 673567660 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 673567660 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 127793316 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 127793316 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 801360976 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 801360976 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1460 # Number of read requests accepted system.mem_ctrls.writeReqs 277 # Number of write requests accepted system.mem_ctrls.readBursts 1460 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 74880 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 18560 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 6400 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 75008 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 18432 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 6464 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 93440 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 290 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 155 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 61 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 90 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 90 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 103 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 105 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 21 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 4 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 87 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 396 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 394 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 29 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 30 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 5 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 19 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 16 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 138534 # Total gap between requests +system.mem_ctrls.totGap 138621 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1170 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1172 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,12 +136,12 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 7 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 7 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see @@ -184,86 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 224 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 353.142857 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 223.489977 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 324.415911 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 59 26.34% 26.34% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 55 24.55% 50.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 31 13.84% 64.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 15 6.70% 71.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 13 5.80% 77.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 14 6.25% 83.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7 3.12% 86.61% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 9 4.02% 90.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 21 9.38% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 224 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 233 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 343.622318 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 215.641138 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 323.027267 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 63 27.04% 27.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 61 26.18% 53.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 29 12.45% 65.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 14 6.01% 71.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 15 6.44% 78.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14 6.01% 84.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7 3.00% 87.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 7 3.00% 90.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 23 9.87% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 233 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 178 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 127.889331 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 115.157284 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 179.333333 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 129.319022 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 112.290100 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::64-79 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::192-207 2 33.33% 66.67% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::208-223 1 16.67% 66.67% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::240-255 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::336-351 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::320-335 1 16.67% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.640671 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.032796 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 4 66.67% 66.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.833333 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.809662 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.983192 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 3 50.00% 50.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 16.67% 66.67% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::18 2 33.33% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7999 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30229 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5850 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.84 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 8028 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 30296 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5860 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 6.85 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.84 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 540.12 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 46.16 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 673.99 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 127.87 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 25.85 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 540.70 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 46.60 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 673.57 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 127.79 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.58 # Data bus utilization in percentage +system.mem_ctrls.busUtil 4.59 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 4.22 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 23.33 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 948 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 22.86 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 943 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 92 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.03 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 80.46 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 75.41 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 79.75 # Average gap between requests -system.mem_ctrls.pageHitRate 80.50 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5828160 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgGap 79.80 # Average gap between requests +system.mem_ctrls.pageHitRate 79.98 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 604800 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 336000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5840640 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 383616 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 75338496 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 13486800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 104532096 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 788.195744 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 25869 # Time in different power states +system.mem_ctrls_0.actBackEnergy 75398688 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 13434000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 104643264 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 789.033976 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 25868 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 4420 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 106214 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 106302 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 8112000 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 673920 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1118880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 621600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 8087040 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 89081424 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1431600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 109661424 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 826.872042 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1728 # Time in different power states +system.mem_ctrls_1.actBackEnergy 89353656 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1192800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 109683048 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 827.035092 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1330 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 4420 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 126488 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 126886 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -299,7 +301,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 138637 # number of cpu cycles simulated +system.cpu.numCycles 138724 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -318,7 +320,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 138637 # Number of busy cycles +system.cpu.num_busy_cycles 138724 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -361,9 +363,9 @@ system.ruby.clk_domain.clock 1 # Cl system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 9645 # delay histogram for all message -system.ruby.delayHist::mean 0.162779 # delay histogram for all message -system.ruby.delayHist::stdev 1.010338 # delay histogram for all message -system.ruby.delayHist | 9295 96.37% 96.37% | 0 0.00% 96.37% | 205 2.13% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::mean 0.162571 # delay histogram for all message +system.ruby.delayHist::stdev 1.010166 # delay histogram for all message +system.ruby.delayHist | 9296 96.38% 96.38% | 0 0.00% 96.38% | 204 2.12% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 9645 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -375,10 +377,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 15.410630 -system.ruby.latency_hist::gmean 5.220490 -system.ruby.latency_hist::stdev 29.556532 -system.ruby.latency_hist | 7278 86.15% 86.15% | 1151 13.62% 99.78% | 3 0.04% 99.81% | 2 0.02% 99.83% | 6 0.07% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 15.420928 +system.ruby.latency_hist::gmean 5.221828 +system.ruby.latency_hist::stdev 29.495379 +system.ruby.latency_hist | 7276 86.13% 86.13% | 1152 13.64% 99.76% | 4 0.05% 99.81% | 4 0.05% 99.86% | 4 0.05% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -390,10 +392,10 @@ system.ruby.hit_latency_hist::total 6958 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1490 -system.ruby.miss_latency_hist::mean 73.365772 -system.ruby.miss_latency_hist::gmean 69.377440 -system.ruby.miss_latency_hist::stdev 29.580633 -system.ruby.miss_latency_hist | 320 21.48% 21.48% | 1151 77.25% 98.72% | 3 0.20% 98.93% | 2 0.13% 99.06% | 6 0.40% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 73.424161 +system.ruby.miss_latency_hist::gmean 69.478292 +system.ruby.miss_latency_hist::stdev 29.116195 +system.ruby.miss_latency_hist | 318 21.34% 21.34% | 1152 77.32% 98.66% | 4 0.27% 98.93% | 4 0.27% 99.19% | 4 0.27% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1490 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses @@ -414,7 +416,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 30 # N system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 3.776229 +system.ruby.network.routers0.percent_links_utilized 3.773860 system.ruby.network.routers0.msg_count.Control::0 1490 system.ruby.network.routers0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.msg_count.Response_Data::1 1490 @@ -431,7 +433,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6392 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.percent_links_utilized 7.332278 +system.ruby.network.routers1.percent_links_utilized 7.327679 system.ruby.network.routers1.msg_count.Control::0 2950 system.ruby.network.routers1.msg_count.Request_Control::2 1041 system.ruby.network.routers1.msg_count.Response_Data::1 3227 @@ -448,14 +450,14 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6392 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers2.percent_links_utilized 3.556049 +system.ruby.network.routers2.percent_links_utilized 3.553819 system.ruby.network.routers2.msg_count.Control::0 1460 system.ruby.network.routers2.msg_count.Response_Data::1 1737 system.ruby.network.routers2.msg_count.Response_Control::1 2627 system.ruby.network.routers2.msg_bytes.Control::0 11680 system.ruby.network.routers2.msg_bytes.Response_Data::1 125064 system.ruby.network.routers2.msg_bytes.Response_Control::1 21016 -system.ruby.network.routers3.percent_links_utilized 4.888185 +system.ruby.network.routers3.percent_links_utilized 4.885120 system.ruby.network.routers3.msg_count.Control::0 2950 system.ruby.network.routers3.msg_count.Request_Control::2 1041 system.ruby.network.routers3.msg_count.Response_Data::1 3227 @@ -484,14 +486,14 @@ system.ruby.network.msg_byte.Response_Data 697032 system.ruby.network.msg_byte.Response_Control 114288 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 6984 -system.ruby.network.routers0.throttle0.link_utilization 5.369057 +system.ruby.network.routers0.throttle0.link_utilization 5.365690 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 436 system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107280 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers0.throttle1.link_utilization 2.183400 +system.ruby.network.routers0.throttle1.link_utilization 2.182031 system.ruby.network.routers0.throttle1.msg_count.Control::0 1490 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900 system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799 @@ -504,7 +506,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 639 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.throttle0.link_utilization 7.446064 +system.ruby.network.routers1.throttle0.link_utilization 7.441394 system.ruby.network.routers1.throttle0.msg_count.Control::0 1490 system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460 system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352 @@ -519,7 +521,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 639 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.throttle1.link_utilization 7.218491 +system.ruby.network.routers1.throttle1.link_utilization 7.213964 system.ruby.network.routers1.throttle1.msg_count.Control::0 1460 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041 system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767 @@ -528,26 +530,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888 -system.ruby.network.routers2.throttle0.link_utilization 1.849434 +system.ruby.network.routers2.throttle0.link_utilization 1.848274 system.ruby.network.routers2.throttle0.msg_count.Control::0 1460 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175 system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400 -system.ruby.network.routers2.throttle1.link_utilization 5.262664 +system.ruby.network.routers2.throttle1.link_utilization 5.259364 system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460 system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120 system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616 -system.ruby.network.routers3.throttle0.link_utilization 5.369057 +system.ruby.network.routers3.throttle0.link_utilization 5.365690 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490 system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers3.throttle1.link_utilization 7.446064 +system.ruby.network.routers3.throttle1.link_utilization 7.441394 system.ruby.network.routers3.throttle1.msg_count.Control::0 1490 system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460 system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352 @@ -562,7 +564,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 639 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers3.throttle2.link_utilization 1.849434 +system.ruby.network.routers3.throttle2.link_utilization 1.848274 system.ruby.network.routers3.throttle2.msg_count.Control::0 1460 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175 @@ -579,9 +581,9 @@ system.ruby.delayVCHist.vnet_0::total 2725 # de system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::samples 5879 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.069740 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.366932 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 5674 96.51% 96.51% | 0 0.00% 96.51% | 205 3.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.069400 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.366068 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 5675 96.53% 96.53% | 0 0.00% 96.53% | 204 3.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::total 5879 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 @@ -591,10 +593,10 @@ system.ruby.delayVCHist.vnet_2::total 1041 # de system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 35.343195 -system.ruby.LD.latency_hist::gmean 13.647233 -system.ruby.LD.latency_hist::stdev 36.940945 -system.ruby.LD.latency_hist | 797 67.37% 67.37% | 383 32.38% 99.75% | 1 0.08% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 35.984784 +system.ruby.LD.latency_hist::gmean 13.718106 +system.ruby.LD.latency_hist::stdev 39.109328 +system.ruby.LD.latency_hist | 793 67.03% 67.03% | 384 32.46% 99.49% | 1 0.08% 99.58% | 1 0.08% 99.66% | 2 0.17% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -606,18 +608,18 @@ system.ruby.LD.hit_latency_hist::total 600 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 583 -system.ruby.LD.miss_latency_hist::mean 68.629503 -system.ruby.LD.miss_latency_hist::gmean 64.886248 -system.ruby.LD.miss_latency_hist::stdev 24.148594 -system.ruby.LD.miss_latency_hist | 197 33.79% 33.79% | 383 65.69% 99.49% | 1 0.17% 99.66% | 0 0.00% 99.66% | 1 0.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 69.931389 +system.ruby.LD.miss_latency_hist::gmean 65.571846 +system.ruby.LD.miss_latency_hist::stdev 28.816437 +system.ruby.LD.miss_latency_hist | 193 33.10% 33.10% | 384 65.87% 98.97% | 1 0.17% 99.14% | 1 0.17% 99.31% | 2 0.34% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 583 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 17.890173 -system.ruby.ST.latency_hist::gmean 6.261514 -system.ruby.ST.latency_hist::stdev 30.772511 -system.ruby.ST.latency_hist | 767 88.67% 88.67% | 95 10.98% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 18.053179 +system.ruby.ST.latency_hist::gmean 6.262232 +system.ruby.ST.latency_hist::stdev 31.945584 +system.ruby.ST.latency_hist | 769 88.90% 88.90% | 92 10.64% 99.54% | 1 0.12% 99.65% | 0 0.00% 99.65% | 1 0.12% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -629,18 +631,18 @@ system.ruby.ST.hit_latency_hist::total 649 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 216 -system.ruby.ST.miss_latency_hist::mean 62.629630 -system.ruby.ST.miss_latency_hist::gmean 57.125913 -system.ruby.ST.miss_latency_hist::stdev 33.544027 -system.ruby.ST.miss_latency_hist | 118 54.63% 54.63% | 95 43.98% 98.61% | 1 0.46% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 63.282407 +system.ruby.ST.miss_latency_hist::gmean 57.152160 +system.ruby.ST.miss_latency_hist::stdev 36.903379 +system.ruby.ST.miss_latency_hist | 120 55.56% 55.56% | 92 42.59% 98.15% | 1 0.46% 98.61% | 0 0.00% 98.61% | 1 0.46% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 216 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 11.391094 -system.ruby.IFETCH.latency_hist::gmean 4.264782 -system.ruby.IFETCH.latency_hist::stdev 26.130654 -system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 673 10.52% 99.80% | 1 0.02% 99.81% | 2 0.03% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 11.264062 +system.ruby.IFETCH.latency_hist::gmean 4.262075 +system.ruby.IFETCH.latency_hist::stdev 25.133535 +system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 676 10.56% 99.84% | 2 0.03% 99.88% | 3 0.05% 99.92% | 1 0.02% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -652,10 +654,10 @@ system.ruby.IFETCH.hit_latency_hist::total 5709 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 691 -system.ruby.IFETCH.miss_latency_hist::mean 80.717800 -system.ruby.IFETCH.miss_latency_hist::gmean 78.004389 -system.ruby.IFETCH.miss_latency_hist::stdev 30.603968 -system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 673 97.40% 98.12% | 1 0.14% 98.26% | 2 0.29% 98.55% | 5 0.72% 99.28% | 5 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 79.541245 +system.ruby.IFETCH.miss_latency_hist::gmean 77.547127 +system.ruby.IFETCH.miss_latency_hist::stdev 24.993726 +system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 676 97.83% 98.55% | 2 0.29% 98.84% | 3 0.43% 99.28% | 1 0.14% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 691 system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% system.ruby.Directory_Controller.Data 277 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index d5c587675..216848fe0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000126 # Number of seconds simulated -sim_ticks 126195 # Number of ticks simulated -final_tick 126195 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 126343 # Number of ticks simulated +final_tick 126343 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 43805 # Simulator instruction rate (inst/s) -host_op_rate 43801 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 864948 # Simulator tick rate (ticks/s) -host_mem_usage 454088 # Number of bytes of host memory used +host_inst_rate 43834 # Simulator instruction rate (inst/s) +host_op_rate 43830 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 866526 # Simulator tick rate (ticks/s) +host_mem_usage 454420 # Number of bytes of host memory used host_seconds 0.15 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1182 # system.mem_ctrls.num_reads::total 1182 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 599453227 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 599453227 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 98387416 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 98387416 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 697840643 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 697840643 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 598751019 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 598751019 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 98272164 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 98272164 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 697023183 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 697023183 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1182 # Number of read requests accepted system.mem_ctrls.writeReqs 194 # Number of write requests accepted system.mem_ctrls.readBursts 1182 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64576 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 11072 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5248 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 64512 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 11136 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 75648 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 83 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 174 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 78 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 91 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 99 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 20 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 363 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 21 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 37 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 126127 # Total gap between requests +system.mem_ctrls.totGap 126275 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1009 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1008 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,8 +135,8 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see @@ -149,9 +149,9 @@ system.mem_ctrls.wrQLenPdf::25 6 # Wh system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see @@ -184,86 +184,86 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 211 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 327.582938 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 201.542711 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 321.278601 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 66 31.28% 31.28% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 57 27.01% 58.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 21 9.95% 68.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 10 4.74% 72.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 6.64% 79.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 12 5.69% 85.31% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 5 2.37% 87.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.42% 89.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 23 10.90% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 211 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 212 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 326.339623 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 200.746581 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 319.329567 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 67 31.60% 31.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 54 25.47% 57.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 23 10.85% 67.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 13 6.13% 74.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 12 5.66% 79.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 5.66% 85.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.83% 88.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 1.42% 89.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 22 10.38% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 212 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 141 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 106.525720 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 81.341871 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 136.800000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 103.930082 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 78.649221 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 1 20.00% 40.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.400000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.381380 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.894427 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 4 80.00% 80.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1 20.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.800000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.771851 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7775 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26946 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5045 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 7.71 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 7952 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 27104 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5040 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 7.89 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 26.71 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 511.72 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 41.59 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 599.45 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 98.39 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 26.89 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 510.61 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 42.55 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 598.75 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 98.27 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 4.32 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.00 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.32 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtilRead 3.99 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.33 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.42 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 799 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 76 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.19 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 68.47 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 91.66 # Average gap between requests -system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 186624 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 22.50 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 801 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 74 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.46 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 63.79 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 91.77 # Average gap between requests +system.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 567000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 315000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5116800 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 311040 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 64142784 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 18636000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 96952848 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 776.641738 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 31414 # Time in different power states +system.mem_ctrls_0.actBackEnergy 63365076 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 19318200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 97130076 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 778.061425 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 32699 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 4160 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 90106 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 88969 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 7450560 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1028160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 571200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7300800 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 559872 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 84064968 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1160400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 103087560 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 825.783908 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1262 # Time in different power states +system.mem_ctrls_1.actBackEnergy 84071808 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1154400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102823200 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 823.666250 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1294 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 119428 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 119396 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -299,7 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 126195 # number of cpu cycles simulated +system.cpu.numCycles 126343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -318,7 +318,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 126195 # Number of busy cycles +system.cpu.num_busy_cycles 126343 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -368,10 +368,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.937855 -system.ruby.latency_hist::gmean 4.957827 -system.ruby.latency_hist::stdev 28.413153 -system.ruby.latency_hist | 7438 88.04% 88.04% | 992 11.74% 99.79% | 2 0.02% 99.81% | 1 0.01% 99.82% | 11 0.13% 99.95% | 3 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 13.955374 +system.ruby.latency_hist::gmean 4.957459 +system.ruby.latency_hist::stdev 28.739433 +system.ruby.latency_hist | 7439 88.06% 88.06% | 992 11.74% 99.80% | 2 0.02% 99.82% | 0 0.00% 99.82% | 4 0.05% 99.87% | 10 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -383,10 +383,10 @@ system.ruby.hit_latency_hist::total 7027 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1421 -system.ruby.miss_latency_hist::mean 68.026742 -system.ruby.miss_latency_hist::gmean 59.451968 -system.ruby.miss_latency_hist::stdev 35.813966 -system.ruby.miss_latency_hist | 411 28.92% 28.92% | 992 69.81% 98.73% | 2 0.14% 98.87% | 1 0.07% 98.94% | 11 0.77% 99.72% | 3 0.21% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 68.130894 +system.ruby.miss_latency_hist::gmean 59.425748 +system.ruby.miss_latency_hist::stdev 37.179084 +system.ruby.miss_latency_hist | 412 28.99% 28.99% | 992 69.81% 98.80% | 2 0.14% 98.94% | 0 0.00% 98.94% | 4 0.28% 99.23% | 10 0.70% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1421 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 775 # Number of cache demand misses @@ -398,7 +398,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 239 # N system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 5.974286 +system.ruby.network.routers0.percent_links_utilized 5.967287 system.ruby.network.routers0.msg_count.Request_Control::0 1421 system.ruby.network.routers0.msg_count.Response_Data::2 1182 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239 @@ -411,7 +411,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers1.percent_links_utilized 8.972820 +system.ruby.network.routers1.percent_links_utilized 8.962309 system.ruby.network.routers1.msg_count.Request_Control::0 1421 system.ruby.network.routers1.msg_count.Request_Control::1 1182 system.ruby.network.routers1.msg_count.Response_Data::2 2364 @@ -428,7 +428,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108144 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21192 -system.ruby.network.routers2.percent_links_utilized 2.998534 +system.ruby.network.routers2.percent_links_utilized 2.995021 system.ruby.network.routers2.msg_count.Request_Control::1 1182 system.ruby.network.routers2.msg_count.Response_Data::2 1182 system.ruby.network.routers2.msg_count.Writeback_Data::2 194 @@ -439,7 +439,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 85104 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9456 -system.ruby.network.routers3.percent_links_utilized 5.981880 +system.ruby.network.routers3.percent_links_utilized 5.974873 system.ruby.network.routers3.msg_count.Request_Control::0 1421 system.ruby.network.routers3.msg_count.Request_Control::1 1182 system.ruby.network.routers3.msg_count.Response_Data::2 2364 @@ -468,14 +468,14 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624 system.ruby.network.msg_byte.Writeback_Data 324432 system.ruby.network.msg_byte.Writeback_Control 74304 system.ruby.network.msg_byte.Unblock_Control 63576 -system.ruby.network.routers0.throttle0.link_utilization 5.603629 +system.ruby.network.routers0.throttle0.link_utilization 5.597065 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1354 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85104 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10832 -system.ruby.network.routers0.throttle1.link_utilization 6.344942 +system.ruby.network.routers0.throttle1.link_utilization 6.337510 system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1421 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1308 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1354 @@ -484,7 +484,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11368 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10832 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers1.throttle0.link_utilization 10.636713 +system.ruby.network.routers1.throttle0.link_utilization 10.624253 system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1421 system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1308 @@ -497,7 +497,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10832 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers1.throttle1.link_utilization 7.308927 +system.ruby.network.routers1.throttle1.link_utilization 7.300365 system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1182 system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1182 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239 @@ -512,7 +512,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10832 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9456 -system.ruby.network.routers2.throttle0.link_utilization 1.705297 +system.ruby.network.routers2.throttle0.link_utilization 1.703300 system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1182 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194 @@ -521,19 +521,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9456 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9456 -system.ruby.network.routers2.throttle1.link_utilization 4.291771 +system.ruby.network.routers2.throttle1.link_utilization 4.286743 system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1182 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85104 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers3.throttle0.link_utilization 5.603629 +system.ruby.network.routers3.throttle0.link_utilization 5.597065 system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1354 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85104 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10832 -system.ruby.network.routers3.throttle1.link_utilization 10.636713 +system.ruby.network.routers3.throttle1.link_utilization 10.624253 system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1421 system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1182 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1308 @@ -546,7 +546,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10832 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers3.throttle2.link_utilization 1.705297 +system.ruby.network.routers3.throttle2.link_utilization 1.703300 system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1182 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194 @@ -558,10 +558,10 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456 system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 29.370245 -system.ruby.LD.latency_hist::gmean 10.775321 -system.ruby.LD.latency_hist::stdev 36.738545 -system.ruby.LD.latency_hist | 860 72.70% 72.70% | 320 27.05% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 29.639053 +system.ruby.LD.latency_hist::gmean 10.782209 +system.ruby.LD.latency_hist::stdev 38.418359 +system.ruby.LD.latency_hist | 863 72.95% 72.95% | 315 26.63% 99.58% | 1 0.08% 99.66% | 0 0.00% 99.66% | 1 0.08% 99.75% | 3 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -573,18 +573,18 @@ system.ruby.LD.hit_latency_hist::total 658 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 525 -system.ruby.LD.miss_latency_hist::mean 62.420952 -system.ruby.LD.miss_latency_hist::gmean 53.507846 -system.ruby.LD.miss_latency_hist::stdev 32.816863 -system.ruby.LD.miss_latency_hist | 202 38.48% 38.48% | 320 60.95% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 63.026667 +system.ruby.LD.miss_latency_hist::gmean 53.584951 +system.ruby.LD.miss_latency_hist::stdev 36.351224 +system.ruby.LD.miss_latency_hist | 205 39.05% 39.05% | 315 60.00% 99.05% | 1 0.19% 99.24% | 0 0.00% 99.24% | 1 0.19% 99.43% | 3 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 525 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 19.187283 -system.ruby.ST.latency_hist::gmean 6.808148 -system.ruby.ST.latency_hist::stdev 31.171451 -system.ruby.ST.latency_hist | 753 87.05% 87.05% | 108 12.49% 99.54% | 2 0.23% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 18.927168 +system.ruby.ST.latency_hist::gmean 6.798661 +system.ruby.ST.latency_hist::stdev 29.816693 +system.ruby.ST.latency_hist | 751 86.82% 86.82% | 112 12.95% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -596,18 +596,18 @@ system.ruby.ST.hit_latency_hist::total 615 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 250 -system.ruby.ST.miss_latency_hist::mean 59.008000 -system.ruby.ST.miss_latency_hist::gmean 51.116604 -system.ruby.ST.miss_latency_hist::stdev 33.649742 -system.ruby.ST.miss_latency_hist | 138 55.20% 55.20% | 108 43.20% 98.40% | 2 0.80% 99.20% | 0 0.00% 99.20% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 58.108000 +system.ruby.ST.miss_latency_hist::gmean 50.870585 +system.ruby.ST.miss_latency_hist::stdev 30.281947 +system.ruby.ST.miss_latency_hist | 136 54.40% 54.40% | 112 44.80% 99.20% | 1 0.40% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 250 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 10.375781 -system.ruby.IFETCH.latency_hist::gmean 4.114880 -system.ruby.IFETCH.latency_hist::stdev 24.994631 -system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 564 8.81% 99.83% | 0 0.00% 99.83% | 1 0.02% 99.84% | 8 0.12% 99.97% | 1 0.02% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 10.384375 +system.ruby.IFETCH.latency_hist::gmean 4.114767 +system.ruby.IFETCH.latency_hist::stdev 25.220182 +system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 565 8.83% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 3 0.05% 99.89% | 6 0.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -619,10 +619,10 @@ system.ruby.IFETCH.hit_latency_hist::total 5754 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 646 -system.ruby.IFETCH.miss_latency_hist::mean 76.072755 -system.ruby.IFETCH.miss_latency_hist::gmean 68.664868 -system.ruby.IFETCH.miss_latency_hist::stdev 37.280241 -system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 564 87.31% 98.30% | 0 0.00% 98.30% | 1 0.15% 98.45% | 8 1.24% 99.69% | 1 0.15% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 76.157895 +system.ruby.IFETCH.miss_latency_hist::gmean 68.646090 +system.ruby.IFETCH.miss_latency_hist::stdev 38.613086 +system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 565 87.46% 98.45% | 0 0.00% 98.45% | 0 0.00% 98.45% | 3 0.46% 98.92% | 6 0.93% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 646 system.ruby.Directory_Controller.GETX 198 0.00% 0.00% system.ruby.Directory_Controller.GETS 984 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 23f7e060f..ca7e00529 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000117 # Number of seconds simulated -sim_ticks 116770 # Number of ticks simulated -final_tick 116770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000116 # Number of seconds simulated +sim_ticks 116369 # Number of ticks simulated +final_tick 116369 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 63656 # Simulator instruction rate (inst/s) -host_op_rate 63646 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1162909 # Simulator tick rate (ticks/s) -host_mem_usage 451252 # Number of bytes of host memory used +host_inst_rate 61340 # Simulator instruction rate (inst/s) +host_op_rate 61332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1116785 # Simulator tick rate (ticks/s) +host_mem_usage 453376 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,35 +21,35 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1176 # system.mem_ctrls.num_reads::total 1176 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 228 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 228 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 644549114 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 644549114 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 124963604 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 124963604 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 769512717 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 769512717 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 646770188 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 646770188 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 125394220 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 125394220 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 772164408 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 772164408 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1176 # Number of read requests accepted system.mem_ctrls.writeReqs 228 # Number of write requests accepted system.mem_ctrls.readBursts 1176 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 228 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64960 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 6144 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 64320 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 10944 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5120 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 75264 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 14592 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 171 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 116 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 92 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 87 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 53 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 361 # Per bank write bursts @@ -59,21 +59,21 @@ system.mem_ctrls.perBankWrBursts::0 0 # Pe system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 26 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 5 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 44 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 116679 # Total gap between requests +system.mem_ctrls.totGap 116278 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 228 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1015 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1005 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -137,12 +137,12 @@ system.mem_ctrls.wrQLenPdf::13 1 # Wh system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see @@ -152,7 +152,7 @@ system.mem_ctrls.wrQLenPdf::28 6 # Wh system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -184,85 +184,84 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 202 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 339.643564 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 206.317034 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 334.142270 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 63 31.19% 31.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 47 23.27% 54.46% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 25 12.38% 66.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 13 6.44% 73.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 6.93% 80.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 7 3.47% 83.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 1.49% 85.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 2.48% 87.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 12.38% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 202 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 155.833333 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 115.513983 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 90.977836 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-95 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::160-175 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-223 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::256-271 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads +system.mem_ctrls.bytesPerActivate::samples 201 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 334.328358 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 202.953148 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 329.613215 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 65 32.34% 32.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 44 21.89% 54.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 26 12.94% 67.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 14 6.97% 74.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 13 6.47% 80.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 3.48% 84.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 1.99% 86.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 2.49% 88.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 23 11.44% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 201 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 135 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 98.212508 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 84.208076 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::160-167 1 20.00% 60.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7533 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26818 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5075 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 7.42 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::16 5 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 7422 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 26517 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5025 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 7.39 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 26.42 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 556.31 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 52.62 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 644.55 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 124.96 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 26.39 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 552.72 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 44.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 646.77 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 125.39 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.35 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.41 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.66 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.32 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.34 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.40 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 810 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 92 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.80 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 77.31 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 83.10 # Average gap between requests -system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.mem_ctrls.avgWrQLen 22.99 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 804 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 74 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.00 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 66.07 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 82.82 # Average gap between requests +system.mem_ctrls.pageHitRate 78.60 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 285600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5041920 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 269568 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 165888 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) system.mem_ctrls_0.actBackEnergy 60923196 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 12117000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 86271204 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 789.566591 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 22175 # Time in different power states +system.mem_ctrls_0.totalEnergy 86117604 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 788.160821 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 25118 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT 85821 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 937440 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 520800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 725760 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6776640 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 72391140 # Energy for active background per rank (pJ) +system.mem_ctrls_1.actBackEnergy 72408924 # Energy for active background per rank (pJ) system.mem_ctrls_1.preBackEnergy 2062800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 90521940 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 828.401709 # Core power per rank (mW) +system.mem_ctrls_1.totalEnergy 90489996 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 827.912387 # Core power per rank (mW) system.mem_ctrls_1.memoryStateTime::IDLE 2878 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 102769 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 102795 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -298,7 +297,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 116770 # number of cpu cycles simulated +system.cpu.numCycles 116369 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -317,7 +316,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 116770 # Number of busy cycles +system.cpu.num_busy_cycles 116369 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -367,10 +366,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 12.822206 -system.ruby.latency_hist::gmean 3.506830 -system.ruby.latency_hist::stdev 27.805292 -system.ruby.latency_hist | 7433 87.99% 87.99% | 995 11.78% 99.76% | 6 0.07% 99.83% | 2 0.02% 99.86% | 8 0.09% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 12.774740 +system.ruby.latency_hist::gmean 3.504112 +system.ruby.latency_hist::stdev 27.744497 +system.ruby.latency_hist | 7443 88.10% 88.10% | 986 11.67% 99.78% | 5 0.06% 99.83% | 2 0.02% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 4 system.ruby.hit_latency_hist::max_bucket 39 @@ -383,10 +382,10 @@ system.ruby.hit_latency_hist::total 7272 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1176 -system.ruby.miss_latency_hist::mean 75.774660 -system.ruby.miss_latency_hist::gmean 72.686009 -system.ruby.miss_latency_hist::stdev 29.375504 -system.ruby.miss_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 75.433673 +system.ruby.miss_latency_hist::gmean 72.282303 +system.ruby.miss_latency_hist::stdev 29.690242 +system.ruby.miss_latency_hist | 171 14.54% 14.54% | 986 83.84% 98.38% | 5 0.43% 98.81% | 2 0.17% 98.98% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1176 system.ruby.Directory.incomplete_times 1175 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1311 # Number of cache demand hits @@ -399,7 +398,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 189 # N system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 5.578702 +system.ruby.network.routers0.percent_links_utilized 5.597926 system.ruby.network.routers0.msg_count.Request_Control::1 1383 system.ruby.network.routers0.msg_count.Response_Data::4 1176 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 207 @@ -412,7 +411,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 320 -system.ruby.network.routers1.percent_links_utilized 4.210200 +system.ruby.network.routers1.percent_links_utilized 4.224708 system.ruby.network.routers1.msg_count.Request_Control::1 1383 system.ruby.network.routers1.msg_count.Request_Control::2 1194 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 207 @@ -427,7 +426,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 113904 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7728 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers2.percent_links_utilized 3.172048 +system.ruby.network.routers2.percent_links_utilized 3.182978 system.ruby.network.routers2.msg_count.Request_Control::2 1194 system.ruby.network.routers2.msg_count.Response_Data::4 1176 system.ruby.network.routers2.msg_count.Writeback_Data::4 228 @@ -438,7 +437,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 84672 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16416 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7728 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers3.percent_links_utilized 4.320316 +system.ruby.network.routers3.percent_links_utilized 4.335204 system.ruby.network.routers3.msg_count.Request_Control::1 1383 system.ruby.network.routers3.msg_count.Request_Control::2 1194 system.ruby.network.routers3.msg_count.Response_Data::4 1176 @@ -469,7 +468,7 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 341712 system.ruby.network.msg_byte.Writeback_Control 23184 system.ruby.network.msg_byte.Persistent_Control 960 -system.ruby.network.routers0.throttle0.link_utilization 5.338700 +system.ruby.network.routers0.throttle0.link_utilization 5.357097 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1176 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 207 system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 @@ -478,21 +477,21 @@ system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84672 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers0.throttle1.link_utilization 5.818703 +system.ruby.network.routers0.throttle1.link_utilization 5.838754 system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1383 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1354 system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 20 system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11064 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers1.throttle0.link_utilization 5.818703 +system.ruby.network.routers1.throttle0.link_utilization 5.838754 system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1383 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1354 system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 20 system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11064 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers1.throttle1.link_utilization 2.601696 +system.ruby.network.routers1.throttle1.link_utilization 2.610661 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1194 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 207 system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 @@ -503,7 +502,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 14 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 16416 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7728 -system.ruby.network.routers2.throttle0.link_utilization 1.812109 +system.ruby.network.routers2.throttle0.link_utilization 1.818354 system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1194 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 228 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 966 @@ -512,24 +511,24 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9552 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 16416 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7728 system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers2.throttle1.link_utilization 4.531986 +system.ruby.network.routers2.throttle1.link_utilization 4.547603 system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1176 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84672 -system.ruby.network.routers3.throttle0.link_utilization 5.330136 +system.ruby.network.routers3.throttle0.link_utilization 5.348503 system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1176 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 207 system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84672 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle1.link_utilization 5.818703 +system.ruby.network.routers3.throttle1.link_utilization 5.838754 system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1383 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1354 system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 20 system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11064 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers3.throttle2.link_utilization 1.812109 +system.ruby.network.routers3.throttle2.link_utilization 1.818354 system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1194 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 228 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 966 @@ -541,10 +540,10 @@ system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 29.646661 -system.ruby.LD.latency_hist::gmean 8.889029 -system.ruby.LD.latency_hist::stdev 37.195991 -system.ruby.LD.latency_hist | 844 71.34% 71.34% | 335 28.32% 99.66% | 0 0.00% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 29.333897 +system.ruby.LD.latency_hist::gmean 8.854915 +system.ruby.LD.latency_hist::stdev 36.549796 +system.ruby.LD.latency_hist | 850 71.85% 71.85% | 330 27.90% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 4 system.ruby.LD.hit_latency_hist::max_bucket 39 @@ -557,18 +556,18 @@ system.ruby.LD.hit_latency_hist::total 760 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 423 -system.ruby.LD.miss_latency_hist::mean 73.808511 -system.ruby.LD.miss_latency_hist::gmean 70.625115 -system.ruby.LD.miss_latency_hist::stdev 26.886169 -system.ruby.LD.miss_latency_hist | 84 19.86% 19.86% | 335 79.20% 99.05% | 0 0.00% 99.05% | 2 0.47% 99.53% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 72.933806 +system.ruby.LD.miss_latency_hist::gmean 69.869692 +system.ruby.LD.miss_latency_hist::stdev 25.813501 +system.ruby.LD.miss_latency_hist | 90 21.28% 21.28% | 330 78.01% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.53% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 423 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 15.620809 -system.ruby.ST.latency_hist::gmean 4.414027 -system.ruby.ST.latency_hist::stdev 30.143438 -system.ruby.ST.latency_hist | 774 89.48% 89.48% | 87 10.06% 99.54% | 2 0.23% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 15.470520 +system.ruby.ST.latency_hist::gmean 4.402566 +system.ruby.ST.latency_hist::stdev 29.923272 +system.ruby.ST.latency_hist | 778 89.94% 89.94% | 83 9.60% 99.54% | 2 0.23% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 4 system.ruby.ST.hit_latency_hist::max_bucket 39 @@ -581,18 +580,18 @@ system.ruby.ST.hit_latency_hist::total 697 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 168 -system.ruby.ST.miss_latency_hist::mean 66.535714 -system.ruby.ST.miss_latency_hist::gmean 61.950283 -system.ruby.ST.miss_latency_hist::stdev 36.753409 -system.ruby.ST.miss_latency_hist | 77 45.83% 45.83% | 87 51.79% 97.62% | 2 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 65.761905 +system.ruby.ST.miss_latency_hist::gmean 61.126570 +system.ruby.ST.miss_latency_hist::stdev 36.894126 +system.ruby.ST.miss_latency_hist | 81 48.21% 48.21% | 83 49.40% 97.62% | 2 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 168 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 9.334062 -system.ruby.IFETCH.latency_hist::gmean 2.862491 -system.ruby.IFETCH.latency_hist::stdev 24.016058 -system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 573 8.95% 99.81% | 4 0.06% 99.87% | 0 0.00% 99.87% | 7 0.11% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.349531 +system.ruby.IFETCH.latency_hist::gmean 2.862602 +system.ruby.IFETCH.latency_hist::stdev 24.187807 +system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 573 8.95% 99.81% | 3 0.05% 99.86% | 1 0.02% 99.87% | 6 0.09% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 4 system.ruby.IFETCH.hit_latency_hist::max_bucket 39 @@ -605,10 +604,10 @@ system.ruby.IFETCH.hit_latency_hist::total 5815 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 585 -system.ruby.IFETCH.miss_latency_hist::mean 79.849573 -system.ruby.IFETCH.miss_latency_hist::gmean 77.699044 -system.ruby.IFETCH.miss_latency_hist::stdev 27.992378 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 80.018803 +system.ruby.IFETCH.miss_latency_hist::gmean 77.731964 +system.ruby.IFETCH.miss_latency_hist::stdev 29.160832 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 3 0.51% 98.46% | 1 0.17% 98.63% | 6 1.03% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 585 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 @@ -628,10 +627,10 @@ system.ruby.L2Cache.hit_mach_latency_hist::total 207 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1176 -system.ruby.Directory.miss_mach_latency_hist::mean 75.774660 -system.ruby.Directory.miss_mach_latency_hist::gmean 72.686009 -system.ruby.Directory.miss_mach_latency_hist::stdev 29.375504 -system.ruby.Directory.miss_mach_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 75.433673 +system.ruby.Directory.miss_mach_latency_hist::gmean 72.282303 +system.ruby.Directory.miss_mach_latency_hist::stdev 29.690242 +system.ruby.Directory.miss_mach_latency_hist | 171 14.54% 14.54% | 986 83.84% 98.38% | 5 0.43% 98.81% | 2 0.17% 98.98% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1176 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -677,10 +676,10 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 102 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 423 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 73.808511 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 70.625115 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 26.886169 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 84 19.86% 19.86% | 335 79.20% 99.05% | 0 0.00% 99.05% | 2 0.47% 99.53% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 72.933806 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 69.869692 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 25.813501 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 90 21.28% 21.28% | 330 78.01% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.53% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 423 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 @@ -700,10 +699,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 44 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 168 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 66.535714 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 61.950283 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 36.753409 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 77 45.83% 45.83% | 87 51.79% 97.62% | 2 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.761905 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 61.126570 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 36.894126 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 81 48.21% 48.21% | 83 49.40% 97.62% | 2 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 168 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 @@ -723,10 +722,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 61 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 585 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 79.849573 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699044 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.992378 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 80.018803 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.731964 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 29.160832 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 3 0.51% 98.46% | 1 0.17% 98.63% | 6 1.03% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 585 system.ruby.Directory_Controller.GETX 209 0.00% 0.00% system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% @@ -773,7 +772,7 @@ system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00% system.ruby.L1Cache_Controller.S.Store 21 0.00% 0.00% system.ruby.L1Cache_Controller.S.L1_Replacement 142 0.00% 0.00% system.ruby.L1Cache_Controller.M.Load 184 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 3298 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 3297 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 32 0.00% 0.00% system.ruby.L1Cache_Controller.M.L1_Replacement 944 0.00% 0.00% system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 9 0.00% 0.00% @@ -782,7 +781,7 @@ system.ruby.L1Cache_Controller.MM.Store 330 0.00% 0.00% system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock 1 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Load 80 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 2125 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Ifetch 2126 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.L1_Replacement 6 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 982 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 4d5f2d93a..3b710633b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000096 # Number of seconds simulated -sim_ticks 96381 # Number of ticks simulated -final_tick 96381 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 96151 # Number of ticks simulated +final_tick 96151 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 66831 # Simulator instruction rate (inst/s) -host_op_rate 66821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1007748 # Simulator tick rate (ticks/s) -host_mem_usage 449612 # Number of bytes of host memory used +host_inst_rate 62758 # Simulator instruction rate (inst/s) +host_op_rate 62749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 944082 # Simulator tick rate (ticks/s) +host_mem_usage 451988 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1159 # system.mem_ctrls.num_reads::total 1159 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 769612268 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 769612268 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 146086884 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 146086884 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 915699152 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 915699152 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 771453235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 771453235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 146436335 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 146436335 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 917889570 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 917889570 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1159 # Number of read requests accepted system.mem_ctrls.writeReqs 220 # Number of write requests accepted system.mem_ctrls.readBursts 1159 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64192 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 9984 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5568 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 63936 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 10240 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 74176 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 156 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 96 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 98 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 54 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 21 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 2 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 5 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 17 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 96301 # Total gap between requests +system.mem_ctrls.totGap 96071 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1003 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 999 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,7 +136,7 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see @@ -149,7 +149,7 @@ system.mem_ctrls.wrQLenPdf::25 6 # Wh system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see @@ -184,87 +184,86 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 194 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 352.659794 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 217.534506 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 333.874690 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 55 28.35% 28.35% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 50 25.77% 54.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 18 9.28% 63.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 17 8.76% 72.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12 6.19% 78.35% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 7 3.61% 81.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7 3.61% 85.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 2.58% 88.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 23 11.86% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 194 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 191 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 356.858639 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 222.990773 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 333.933268 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 49 25.65% 25.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 54 28.27% 53.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 20 10.47% 64.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 14 7.33% 71.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 12 6.28% 78.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 3.66% 81.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 4.19% 85.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 2.09% 87.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 23 12.04% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 191 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 140 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 105.715654 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 81.473922 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 140.600000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 106.599883 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 79.767161 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 80.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.400000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.358321 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.341641 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 40.00% 80.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 20.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6850 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25907 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5015 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.83 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 6736 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 25717 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4995 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 6.74 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.83 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 666.02 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 57.77 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 769.61 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 146.09 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 25.74 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 664.95 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 57.24 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 771.45 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 146.44 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.65 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 5.20 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtil 5.64 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.19 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.24 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 21.88 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 80.56 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 80.68 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 69.83 # Average gap between requests -system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgGap 69.67 # Average gap between requests +system.mem_ctrls.pageHitRate 79.64 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 483840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 268800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5129280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 290304 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 54887580 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 8068200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 75142164 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 802.012594 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 14237 # Time in different power states +system.mem_ctrls_0.actBackEnergy 54680328 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8250000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 75205272 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 802.686163 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 14296 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 77447 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 77144 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 7063680 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7026240 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 601344 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 61908840 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1909200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 79165032 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 844.949750 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 2762 # Time in different power states +system.mem_ctrls_1.actBackEnergy 61762464 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2037600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 79000368 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 843.192247 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2976 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 87824 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 87610 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -300,7 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 96381 # number of cpu cycles simulated +system.cpu.numCycles 96151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -319,7 +318,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 96381 # Number of busy cycles +system.cpu.num_busy_cycles 96151 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -369,10 +368,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 10.408736 -system.ruby.latency_hist::gmean 3.320047 -system.ruby.latency_hist::stdev 22.995606 -system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 10.381510 +system.ruby.latency_hist::gmean 3.318518 +system.ruby.latency_hist::stdev 22.902466 +system.ruby.latency_hist | 8210 97.18% 97.18% | 226 2.68% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 2 system.ruby.hit_latency_hist::max_bucket 19 @@ -385,10 +384,10 @@ system.ruby.hit_latency_hist::total 7289 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1159 -system.ruby.miss_latency_hist::mean 61.364970 -system.ruby.miss_latency_hist::gmean 57.952099 -system.ruby.miss_latency_hist::stdev 28.717200 -system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 61.166523 +system.ruby.miss_latency_hist::gmean 57.757809 +system.ruby.miss_latency_hist::stdev 28.525461 +system.ruby.miss_latency_hist | 921 79.47% 79.47% | 226 19.50% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1159 system.ruby.Directory.incomplete_times 1158 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits @@ -404,7 +403,7 @@ system.ruby.l1_cntrl0.L2cache.demand_hits 203 # N system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 4.652888 +system.ruby.network.routers0.percent_links_utilized 4.664018 system.ruby.network.routers0.msg_count.Request_Control::2 1159 system.ruby.network.routers0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.msg_count.Writeback_Data::5 220 @@ -419,7 +418,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers1.percent_links_utilized 4.652888 +system.ruby.network.routers1.percent_links_utilized 4.664018 system.ruby.network.routers1.msg_count.Request_Control::2 1159 system.ruby.network.routers1.msg_count.Response_Data::4 1159 system.ruby.network.routers1.msg_count.Writeback_Data::5 220 @@ -434,7 +433,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers2.percent_links_utilized 4.652888 +system.ruby.network.routers2.percent_links_utilized 4.664018 system.ruby.network.routers2.msg_count.Request_Control::2 1159 system.ruby.network.routers2.msg_count.Response_Data::4 1159 system.ruby.network.routers2.msg_count.Writeback_Data::5 220 @@ -459,12 +458,12 @@ system.ruby.network.msg_byte.Response_Data 250344 system.ruby.network.msg_byte.Writeback_Data 47520 system.ruby.network.msg_byte.Writeback_Control 77016 system.ruby.network.msg_byte.Unblock_Control 27816 -system.ruby.network.routers0.throttle0.link_utilization 6.004295 +system.ruby.network.routers0.throttle0.link_utilization 6.018658 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83448 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers0.throttle1.link_utilization 3.301481 +system.ruby.network.routers0.throttle1.link_utilization 3.309378 system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1159 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1143 @@ -475,7 +474,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers1.throttle0.link_utilization 3.301481 +system.ruby.network.routers1.throttle0.link_utilization 3.309378 system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1159 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220 system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1143 @@ -486,17 +485,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers1.throttle1.link_utilization 6.004295 +system.ruby.network.routers1.throttle1.link_utilization 6.018658 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1159 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1143 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83448 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers2.throttle0.link_utilization 6.004295 +system.ruby.network.routers2.throttle0.link_utilization 6.018658 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1143 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83448 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers2.throttle1.link_utilization 3.301481 +system.ruby.network.routers2.throttle1.link_utilization 3.309378 system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1159 system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1143 @@ -507,13 +506,13 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9272 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 22.819949 -system.ruby.LD.latency_hist::gmean 7.633765 -system.ruby.LD.latency_hist::stdev 29.454181 -system.ruby.LD.latency_hist | 845 71.43% 71.43% | 248 20.96% 92.39% | 86 7.27% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 22.845309 +system.ruby.LD.latency_hist::gmean 7.610394 +system.ruby.LD.latency_hist::stdev 30.590449 +system.ruby.LD.latency_hist | 1093 92.39% 92.39% | 87 7.35% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 2 system.ruby.LD.hit_latency_hist::max_bucket 19 @@ -523,21 +522,21 @@ system.ruby.LD.hit_latency_hist::gmean 2.587610 system.ruby.LD.hit_latency_hist::stdev 3.791932 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 763 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 +system.ruby.LD.miss_latency_hist::bucket_size 64 +system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 420 -system.ruby.LD.miss_latency_hist::mean 57.892857 -system.ruby.LD.miss_latency_hist::gmean 54.485563 -system.ruby.LD.miss_latency_hist::stdev 22.570398 -system.ruby.LD.miss_latency_hist | 82 19.52% 19.52% | 248 59.05% 78.57% | 86 20.48% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 57.964286 +system.ruby.LD.miss_latency_hist::gmean 54.017024 +system.ruby.LD.miss_latency_hist::stdev 26.398202 +system.ruby.LD.miss_latency_hist | 330 78.57% 78.57% | 87 20.71% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 2 0.48% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 420 system.ruby.ST.latency_hist::bucket_size 16 system.ruby.ST.latency_hist::max_bucket 159 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 11.716763 -system.ruby.ST.latency_hist::gmean 3.868197 -system.ruby.ST.latency_hist::stdev 20.732802 -system.ruby.ST.latency_hist | 707 81.73% 81.73% | 44 5.09% 86.82% | 0 0.00% 86.82% | 74 8.55% 95.38% | 36 4.16% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 11.801156 +system.ruby.ST.latency_hist::gmean 3.876538 +system.ruby.ST.latency_hist::stdev 20.845047 +system.ruby.ST.latency_hist | 707 81.73% 81.73% | 41 4.74% 86.47% | 0 0.00% 86.47% | 78 9.02% 95.49% | 35 4.05% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 2 system.ruby.ST.hit_latency_hist::max_bucket 19 @@ -550,18 +549,18 @@ system.ruby.ST.hit_latency_hist::total 707 system.ruby.ST.miss_latency_hist::bucket_size 16 system.ruby.ST.miss_latency_hist::max_bucket 159 system.ruby.ST.miss_latency_hist::samples 158 -system.ruby.ST.miss_latency_hist::mean 52.898734 -system.ruby.ST.miss_latency_hist::gmean 50.075344 -system.ruby.ST.miss_latency_hist::stdev 15.909453 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 74 46.84% 74.68% | 36 22.78% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 53.360759 +system.ruby.ST.miss_latency_hist::gmean 50.669354 +system.ruby.ST.miss_latency_hist::stdev 15.502298 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 41 25.95% 25.95% | 0 0.00% 25.95% | 78 49.37% 75.32% | 35 22.15% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 158 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 7.937812 -system.ruby.IFETCH.latency_hist::gmean 2.788278 -system.ruby.IFETCH.latency_hist::stdev 21.093490 -system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 7.885781 +system.ruby.IFETCH.latency_hist::gmean 2.787351 +system.ruby.IFETCH.latency_hist::stdev 20.631367 +system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 100 1.56% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 5 0.08% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 2 system.ruby.IFETCH.hit_latency_hist::max_bucket 19 @@ -574,10 +573,10 @@ system.ruby.IFETCH.hit_latency_hist::total 5819 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 581 -system.ruby.IFETCH.miss_latency_hist::mean 66.177281 -system.ruby.IFETCH.miss_latency_hist::gmean 63.050334 -system.ruby.IFETCH.miss_latency_hist::stdev 34.037169 -system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 65.604131 +system.ruby.IFETCH.miss_latency_hist::gmean 62.819819 +system.ruby.IFETCH.miss_latency_hist::stdev 31.817772 +system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 100 17.21% 98.45% | 0 0.00% 98.45% | 0 0.00% 98.45% | 5 0.86% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 581 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 @@ -596,10 +595,10 @@ system.ruby.L2Cache.hit_mach_latency_hist::total 203 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1159 -system.ruby.Directory.miss_mach_latency_hist::mean 61.364970 -system.ruby.Directory.miss_mach_latency_hist::gmean 57.952099 -system.ruby.Directory.miss_mach_latency_hist::stdev 28.717200 -system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 61.166523 +system.ruby.Directory.miss_mach_latency_hist::gmean 57.757809 +system.ruby.Directory.miss_mach_latency_hist::stdev 28.525461 +system.ruby.Directory.miss_mach_latency_hist | 921 79.47% 79.47% | 226 19.50% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1159 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -641,13 +640,13 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 13 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 13.000000 system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 105 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 420 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 57.892857 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 54.485563 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 22.570398 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 82 19.52% 19.52% | 248 59.05% 78.57% | 86 20.48% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 57.964286 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 54.017024 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 26.398202 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 330 78.57% 78.57% | 87 20.71% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 2 0.48% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 420 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 @@ -666,10 +665,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 33 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 158 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.898734 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 50.075344 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.909453 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 74 46.84% 74.68% | 36 22.78% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 53.360759 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 50.669354 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.502298 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 41 25.95% 25.95% | 0 0.00% 25.95% | 78 49.37% 75.32% | 35 22.15% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 158 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 @@ -688,10 +687,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 65 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.177281 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.050334 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.037169 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.604131 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.819819 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 31.817772 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 100 17.21% 98.45% | 0 0.00% 98.45% | 0 0.00% 98.45% | 5 0.86% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581 system.ruby.Directory_Controller.GETX 185 0.00% 0.00% system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index e18c35fff..8d98e090f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000124 # Number of seconds simulated -sim_ticks 123564 # Number of ticks simulated -final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 123531 # Number of ticks simulated +final_tick 123531 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 69668 # Simulator instruction rate (inst/s) -host_op_rate 69633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1346306 # Simulator tick rate (ticks/s) -host_mem_usage 450680 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 63521 # Simulator instruction rate (inst/s) +host_op_rate 63513 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1227662 # Simulator tick rate (ticks/s) +host_mem_usage 451804 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 896053867 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 896053867 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 893982066 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 893982066 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790035933 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1790035933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 896293238 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 896293238 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 894220884 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 894220884 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790514122 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1790514122 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1730 # Number of read requests accepted system.mem_ctrls.writeReqs 1726 # Number of write requests accepted system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54016 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 57536 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 56832 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 53888 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 56512 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 844 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 842 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 814 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 44 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 65 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 82 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 25 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 20 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 80 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 84 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 130 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 23 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 264 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 20 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 81 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 85 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 127 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 25 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 53 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 48 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 32 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 277 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 260 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 74 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 123476 # Total gap between requests +system.mem_ctrls.totGap 123443 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 888 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 9 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 54 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -184,87 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 258 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 429.147287 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 269.046347 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 361.589640 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 63 24.42% 24.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 19.77% 44.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 24 9.30% 53.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 27 10.47% 63.95% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 5.43% 69.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 11 4.26% 73.64% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 4.65% 78.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 14 5.43% 83.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 42 16.28% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 258 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.927273 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.760356 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.949291 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 29 52.73% 52.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 1.82% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.345455 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.329469 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.750757 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 44 80.00% 80.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 4 7.27% 87.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 6 10.91% 98.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 10464 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 27298 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11.81 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 268 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 416.477612 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 263.436899 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 359.508293 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 60 22.39% 22.39% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 57 21.27% 43.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 40 14.93% 58.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 20 7.46% 66.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10 3.73% 69.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14 5.22% 75.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 11 4.10% 79.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 12 4.48% 83.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 44 16.42% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 268 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 54 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.203704 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.997541 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.176444 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 3.70% 3.70% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 22 40.74% 44.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 22 40.74% 85.19% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 6 11.11% 96.30% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::22-23 1 1.85% 98.15% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 1.85% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 54 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 54 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.351852 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.333537 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.804642 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 45 83.33% 83.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 8 14.81% 98.15% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 1 1.85% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 54 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 10373 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 27245 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4440 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 11.68 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 30.81 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 458.90 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 465.64 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 896.05 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 893.98 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 30.68 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 460.06 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 457.47 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 896.29 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 894.22 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.22 # Data bus utilization in percentage +system.mem_ctrls.busUtil 7.17 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 3.59 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.64 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtilWrite 3.57 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.06 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 665 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 854 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 75.06 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 35.73 # Average gap between requests -system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 771120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 428400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4879680 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 4281984 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 25.91 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 672 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 824 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 75.68 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.35 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 35.72 # Average gap between requests +system.mem_ctrls.pageHitRate 83.11 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 824040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 457800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4520448 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 69480720 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 9282000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 96752304 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 826.589526 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 15125 # Time in different power states +system.mem_ctrls_0.actBackEnergy 66802176 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 11631600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 97093584 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 829.505203 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 19845 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 98100 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 94170 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1081080 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 600600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 5466240 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 4323456 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1118880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 621600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 5191680 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 4136832 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 69027912 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 9680400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 97808088 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 835.595188 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 15368 # Time in different power states +system.mem_ctrls_1.actBackEnergy 69356232 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 9391800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 97445424 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 832.503985 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 15122 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 97798 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 98043 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -300,7 +301,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 123564 # number of cpu cycles simulated +system.cpu.numCycles 123531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -319,7 +320,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 123564 # Number of busy cycles +system.cpu.num_busy_cycles 123531 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -374,10 +375,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.626420 -system.ruby.latency_hist::gmean 5.329740 -system.ruby.latency_hist::stdev 25.242996 -system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 13.622514 +system.ruby.latency_hist::gmean 5.329433 +system.ruby.latency_hist::stdev 25.311843 +system.ruby.latency_hist | 8197 97.03% 97.03% | 202 2.39% 99.42% | 36 0.43% 99.85% | 3 0.04% 99.88% | 8 0.09% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -389,17 +390,17 @@ system.ruby.hit_latency_hist::total 6718 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1730 -system.ruby.miss_latency_hist::mean 54.891329 -system.ruby.miss_latency_hist::gmean 49.648144 -system.ruby.miss_latency_hist::stdev 31.153546 -system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 54.872254 +system.ruby.miss_latency_hist::gmean 49.634160 +system.ruby.miss_latency_hist::stdev 31.450318 +system.ruby.miss_latency_hist | 1479 85.49% 85.49% | 202 11.68% 97.17% | 36 2.08% 99.25% | 3 0.17% 99.42% | 8 0.46% 99.88% | 1 0.06% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1730 system.ruby.Directory.incomplete_times 1729 system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.992328 +system.ruby.network.routers0.percent_links_utilized 6.994196 system.ruby.network.routers0.msg_count.Control::2 1730 system.ruby.network.routers0.msg_count.Data::2 1726 system.ruby.network.routers0.msg_count.Response_Data::4 1730 @@ -408,7 +409,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 13840 system.ruby.network.routers0.msg_bytes.Data::2 124272 system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers1.percent_links_utilized 6.992328 +system.ruby.network.routers1.percent_links_utilized 6.994196 system.ruby.network.routers1.msg_count.Control::2 1730 system.ruby.network.routers1.msg_count.Data::2 1726 system.ruby.network.routers1.msg_count.Response_Data::4 1730 @@ -417,7 +418,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 13840 system.ruby.network.routers1.msg_bytes.Data::2 124272 system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.percent_links_utilized 6.992328 +system.ruby.network.routers2.percent_links_utilized 6.994196 system.ruby.network.routers2.msg_count.Control::2 1730 system.ruby.network.routers2.msg_count.Data::2 1726 system.ruby.network.routers2.msg_count.Response_Data::4 1730 @@ -434,32 +435,32 @@ system.ruby.network.msg_byte.Control 41520 system.ruby.network.msg_byte.Data 372816 system.ruby.network.msg_byte.Response_Data 373680 system.ruby.network.msg_byte.Writeback_Control 41424 -system.ruby.network.routers0.throttle0.link_utilization 6.998802 +system.ruby.network.routers0.throttle0.link_utilization 7.000672 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers0.throttle1.link_utilization 6.985853 +system.ruby.network.routers0.throttle1.link_utilization 6.987720 system.ruby.network.routers0.throttle1.msg_count.Control::2 1730 system.ruby.network.routers0.throttle1.msg_count.Data::2 1726 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272 -system.ruby.network.routers1.throttle0.link_utilization 6.985853 +system.ruby.network.routers1.throttle0.link_utilization 6.987720 system.ruby.network.routers1.throttle0.msg_count.Control::2 1730 system.ruby.network.routers1.throttle0.msg_count.Data::2 1726 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272 -system.ruby.network.routers1.throttle1.link_utilization 6.998802 +system.ruby.network.routers1.throttle1.link_utilization 7.000672 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.throttle0.link_utilization 6.998802 +system.ruby.network.routers2.throttle0.link_utilization 7.000672 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.throttle1.link_utilization 6.985853 +system.ruby.network.routers2.throttle1.link_utilization 6.987720 system.ruby.network.routers2.throttle1.msg_count.Control::2 1730 system.ruby.network.routers2.throttle1.msg_count.Data::2 1726 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840 @@ -477,10 +478,10 @@ system.ruby.delayVCHist.vnet_2::total 1726 # de system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 33.711750 -system.ruby.LD.latency_hist::gmean 16.462445 -system.ruby.LD.latency_hist::stdev 33.973523 -system.ruby.LD.latency_hist | 1077 91.04% 91.04% | 86 7.27% 98.31% | 15 1.27% 99.58% | 2 0.17% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 32.793745 +system.ruby.LD.latency_hist::gmean 16.273400 +system.ruby.LD.latency_hist::stdev 32.397171 +system.ruby.LD.latency_hist | 1086 91.80% 91.80% | 85 7.19% 98.99% | 8 0.68% 99.66% | 1 0.08% 99.75% | 2 0.17% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -492,18 +493,18 @@ system.ruby.LD.hit_latency_hist::total 456 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 727 -system.ruby.LD.miss_latency_hist::mean 52.975241 -system.ruby.LD.miss_latency_hist::gmean 47.891138 -system.ruby.LD.miss_latency_hist::stdev 30.251097 -system.ruby.LD.miss_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 51.481431 +system.ruby.LD.miss_latency_hist::gmean 46.999464 +system.ruby.LD.miss_latency_hist::stdev 28.311858 +system.ruby.LD.miss_latency_hist | 630 86.66% 86.66% | 85 11.69% 98.35% | 8 1.10% 99.45% | 1 0.14% 99.59% | 2 0.28% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 727 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 18.557225 -system.ruby.ST.latency_hist::gmean 7.162336 -system.ruby.ST.latency_hist::stdev 28.547301 -system.ruby.ST.latency_hist | 834 96.42% 96.42% | 21 2.43% 98.84% | 9 1.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 18.649711 +system.ruby.ST.latency_hist::gmean 7.153271 +system.ruby.ST.latency_hist::stdev 30.101235 +system.ruby.ST.latency_hist | 832 96.18% 96.18% | 24 2.77% 98.96% | 6 0.69% 99.65% | 1 0.12% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -515,18 +516,18 @@ system.ruby.ST.hit_latency_hist::total 592 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 273 -system.ruby.ST.miss_latency_hist::mean 52.293040 -system.ruby.ST.miss_latency_hist::gmean 47.271858 -system.ruby.ST.miss_latency_hist::stdev 30.324989 -system.ruby.ST.miss_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 52.586081 +system.ruby.ST.miss_latency_hist::gmean 47.082552 +system.ruby.ST.miss_latency_hist::stdev 34.484663 +system.ruby.ST.miss_latency_hist | 240 87.91% 87.91% | 24 8.79% 96.70% | 6 2.20% 98.90% | 1 0.37% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 273 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::bucket_size 32 +system.ruby.IFETCH.latency_hist::max_bucket 319 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 9.247344 -system.ruby.IFETCH.latency_hist::gmean 4.157427 -system.ruby.IFETCH.latency_hist::stdev 20.515003 -system.ruby.IFETCH.latency_hist | 6284 98.19% 98.19% | 92 1.44% 99.63% | 19 0.30% 99.92% | 0 0.00% 99.92% | 3 0.05% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.399375 +system.ruby.IFETCH.latency_hist::gmean 4.166708 +system.ruby.IFETCH.latency_hist::stdev 20.983950 +system.ruby.IFETCH.latency_hist | 5670 88.59% 88.59% | 609 9.52% 98.11% | 88 1.38% 99.48% | 5 0.08% 99.56% | 5 0.08% 99.64% | 17 0.27% 99.91% | 1 0.02% 99.92% | 0 0.00% 99.92% | 1 0.02% 99.94% | 4 0.06% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -535,21 +536,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 5670 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist::max_bucket 319 system.ruby.IFETCH.miss_latency_hist::samples 730 -system.ruby.IFETCH.miss_latency_hist::mean 57.771233 -system.ruby.IFETCH.miss_latency_hist::gmean 52.414605 -system.ruby.IFETCH.miss_latency_hist::stdev 32.138819 -system.ruby.IFETCH.miss_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 59.104110 +system.ruby.IFETCH.miss_latency_hist::gmean 53.449398 +system.ruby.IFETCH.miss_latency_hist::stdev 32.750880 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 609 83.42% 83.42% | 88 12.05% 95.48% | 5 0.68% 96.16% | 5 0.68% 96.85% | 17 2.33% 99.18% | 1 0.14% 99.32% | 0 0.00% 99.32% | 1 0.14% 99.45% | 4 0.55% 100.00% system.ruby.IFETCH.miss_latency_hist::total 730 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1730 -system.ruby.Directory.miss_mach_latency_hist::mean 54.891329 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.648144 -system.ruby.Directory.miss_mach_latency_hist::stdev 31.153546 -system.ruby.Directory.miss_mach_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 54.872254 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.634160 +system.ruby.Directory.miss_mach_latency_hist::stdev 31.450318 +system.ruby.Directory.miss_mach_latency_hist | 1479 85.49% 85.49% | 202 11.68% 97.17% | 36 2.08% 99.25% | 3 0.17% 99.42% | 8 0.46% 99.88% | 1 0.06% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1730 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -580,26 +581,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.975241 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.891138 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.251097 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.481431 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 46.999464 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 28.311858 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 630 86.66% 86.66% | 85 11.69% 98.35% | 8 1.10% 99.45% | 1 0.14% 99.59% | 2 0.28% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.293040 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.271858 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 30.324989 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.586081 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.082552 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 34.484663 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 240 87.91% 87.91% | 24 8.79% 96.70% | 6 2.20% 98.90% | 1 0.37% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.771233 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 59.104110 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 53.449398 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.750880 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 609 83.42% 83.42% | 88 12.05% 95.48% | 5 0.68% 96.16% | 5 0.68% 96.85% | 17 2.33% 99.18% | 1 0.14% 99.32% | 0 0.00% 99.32% | 1 0.14% 99.45% | 4 0.55% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 95d6f5391..2c1174c59 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000033 # Nu sim_ticks 32544500 # Number of ticks simulated final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 643051 # Simulator instruction rate (inst/s) -host_op_rate 642147 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3266208350 # Simulator tick rate (ticks/s) -host_mem_usage 291356 # Number of bytes of host memory used +host_inst_rate 619666 # Simulator instruction rate (inst/s) +host_op_rate 618826 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3148046044 # Simulator tick rate (ticks/s) +host_mem_usage 291528 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.755352 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.755352 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id @@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5130000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3942000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3942000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9072000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9072000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9072000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9072000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -216,24 +216,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.988451 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.988451 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062494 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062494 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -290,97 +290,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15024500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15024500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15024500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15024500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15024500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15024500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.465722 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.994443 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.471279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005629 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 95 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4987500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4987500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 95 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency @@ -395,55 +400,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3102500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3102500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4037500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4037500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7140000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18955500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7140000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18955500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) @@ -468,10 +478,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 373 # Transaction distribution system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 7408970f9..7c57b2554 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20287000 # Number of ticks simulated -final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20091000 # Number of ticks simulated +final_tick 20091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140405 # Simulator instruction rate (inst/s) -host_op_rate 140306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1100341704 # Simulator tick rate (ticks/s) -host_mem_usage 292772 # Number of bytes of host memory used +host_inst_rate 125803 # Simulator instruction rate (inst/s) +host_op_rate 125723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 976523768 # Simulator tick rate (ticks/s) +host_mem_usage 293292 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 703504707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 268152019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 971656726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 703504707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 703504707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 703504707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 268152019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 971656726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 710367826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 270768006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 981135832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 710367826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 710367826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 710367826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 270768006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 981135832 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20198000 # Total gap between requests +system.physmem.totGap 20003000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,77 +187,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 427.707317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.056415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.596590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 430.829268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 282.802413 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.088769 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 14.63% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 9.76% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1763250 # Total ticks spent queuing -system.physmem.totMemAccLat 7538250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1567250 # Total ticks spent queuing +system.physmem.totMemAccLat 7342250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5724.84 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5088.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24474.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 971.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23838.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 981.14 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 971.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 981.14 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.59 # Data bus utilization in percentage -system.physmem.busUtilRead 7.59 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.67 # Data bus utilization in percentage +system.physmem.busUtilRead 7.67 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 258 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65577.92 # Average gap between requests +system.physmem.avgGap 64944.81 # Average gap between requests system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10555830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12721485 # Total energy per rank (pJ) -system.physmem_0.averagePower 803.504500 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 765250 # Time in different power states +system.physmem_0.actBackEnergy 10605420 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ) +system.physmem_0.averagePower 803.889152 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 536250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14968250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10492560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 300000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13287405 # Total energy per rank (pJ) -system.physmem_1.averagePower 838.851326 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 458000 # Time in different power states +system.physmem_1.actBackEnergy 10489995 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13299690 # Total energy per rank (pJ) +system.physmem_1.averagePower 839.892011 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14875250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14871250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 791 # Number of BP lookups +system.cpu.branchPred.lookups 793 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups system.cpu.branchPred.BTBHits 58 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 136 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 816 # DT system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 829 # DTB accesses -system.cpu.itb.fetch_hits 969 # ITB hits +system.cpu.itb.fetch_hits 971 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 982 # ITB accesses +system.cpu.itb.fetch_accesses 984 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 40574 # number of cpu cycles simulated +system.cpu.numCycles 40182 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed system.cpu.discardedOps 594 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.695938 # CPI: cycles per instruction -system.cpu.ipc 0.063711 # IPC: instructions per cycle -system.cpu.tickCycles 5391 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35183 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.544294 # CPI: cycles per instruction +system.cpu.ipc 0.064332 # IPC: instructions per cycle +system.cpu.tickCycles 5392 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34790 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.329975 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.342007 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.329975 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011799 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id @@ -335,14 +335,14 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4962000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4962000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3282500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3282500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8244500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8244500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8244500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8244500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4723000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3258500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7981500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -359,14 +359,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81344.262295 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 81344.262295 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76337.209302 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76337.209302 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79274.038462 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 79274.038462 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75779.069767 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76745.192308 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76745.192308 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4628250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4628250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6637250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6637250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6637250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6637250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4442000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4442000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6459500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6459500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6459500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6459500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79797.413793 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79797.413793 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74407.407407 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74407.407407 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.949271 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 746 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 117.935175 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 748 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.345291 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.354260 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.949271 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057592 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057592 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.935175 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057586 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057586 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2161 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2161 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 746 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 746 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 746 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 746 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 746 # number of overall hits -system.cpu.icache.overall_hits::total 746 # number of overall hits +system.cpu.icache.tags.tag_accesses 2165 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2165 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 748 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 748 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 748 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 748 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 748 # number of overall hits +system.cpu.icache.overall_hits::total 748 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17117250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17117250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17117250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17117250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17117250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17117250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 969 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 969 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 969 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230134 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.230134 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.230134 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.230134 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.230134 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.230134 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76758.968610 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76758.968610 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76758.968610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76758.968610 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16978500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16978500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16978500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16978500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16978500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16978500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229660 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229660 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229660 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229660 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229660 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229660 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76136.771300 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76136.771300 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76136.771300 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76136.771300 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76136.771300 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76136.771300 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,97 +481,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16684250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16684250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16684250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16684250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16684250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16684250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230134 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.230134 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.230134 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74817.264574 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74817.264574 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16755500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16755500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16755500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16755500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229660 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.229660 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.229660 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75136.771300 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75136.771300 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75136.771300 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75136.771300 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75136.771300 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75136.771300 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 145.900805 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 145.853573 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.086871 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.813934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003604 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000849 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004453 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.051720 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.801853 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004451 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 58 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 281 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 223 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 223 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 58 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 58 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16461250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4569250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21030500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1982000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1982000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16461250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6551250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23012500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16461250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6551250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23012500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 223 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 58 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16421000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16421000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16421000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6331000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16421000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6331000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 223 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 223 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 223 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 223 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73817.264574 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78780.172414 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74841.637011 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.407407 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.407407 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74715.909091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74715.909091 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73636.771300 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73636.771300 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73870.129870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73870.129870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,55 +585,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 223 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 223 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 58 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 58 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13669750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3841250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17511000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1642000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1642000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13669750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5483250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19153000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13669750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5483250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19153000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14191000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14191000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14191000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19672000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14191000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19672000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61299.327354 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66228.448276 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62316.725979 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60814.814815 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60814.814815 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63636.771300 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63636.771300 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 223 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes) @@ -649,14 +659,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 383750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 143250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 281 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.trans_dist::ReadResp 281 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 281 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) @@ -672,9 +682,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 308 # Request fanout histogram -system.membus.reqLayer0.occupancy 360000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 359500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1638500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1638750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 493ed4968..ee80959b5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12774000 # Number of ticks simulated -final_tick 12774000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12591500 # Number of ticks simulated +final_tick 12591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38054 # Simulator instruction rate (inst/s) -host_op_rate 38045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 203548685 # Simulator tick rate (ticks/s) -host_mem_usage 224448 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 74456 # Simulator instruction rate (inst/s) +host_op_rate 74426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 392441951 # Simulator tick rate (ticks/s) +host_mem_usage 293552 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 936903084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 425865038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1362768123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 936903084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 936903084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 936903084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 425865038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1362768123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 950482468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 432037486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1382519954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950482468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950482468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950482468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 432037486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1382519954 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12677500 # Total gap between requests +system.physmem.totGap 12495000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,9 +187,9 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.222222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 237.741650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.174986 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation @@ -200,37 +200,37 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1960500 # Total ticks spent queuing -system.physmem.totMemAccLat 7060500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1676750 # Total ticks spent queuing +system.physmem.totMemAccLat 6776750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7207.72 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6164.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25957.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1362.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24914.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1382.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1362.77 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1382.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.65 # Data bus utilization in percentage -system.physmem.busUtilRead 10.65 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.80 # Data bus utilization in percentage +system.physmem.busUtilRead 10.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46608.46 # Average gap between requests +system.physmem.avgGap 45937.50 # Average gap between requests system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 592800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) -system.physmem_0.averagePower 832.600901 # Core power per rank (mW) +system.physmem_0.totalEnergy 6707115 # Total energy per rank (pJ) +system.physmem_0.averagePower 833.570297 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -238,48 +238,48 @@ system.physmem_0.memoryStateTime::ACT 7777500 # Ti system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 6961470 # Total energy per rank (pJ) -system.physmem_1.averagePower 865.181917 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 428500 # Time in different power states +system.physmem_1.totalEnergy 6969270 # Total energy per rank (pJ) +system.physmem_1.averagePower 866.151313 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 708000 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1106 # Number of BP lookups -system.cpu.branchPred.condPredicted 562 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 228 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 735 # Number of BTB lookups -system.cpu.branchPred.BTBHits 214 # Number of BTB hits +system.cpu.branchPred.lookups 1086 # Number of BP lookups +system.cpu.branchPred.condPredicted 546 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 723 # Number of BTB lookups +system.cpu.branchPred.BTBHits 206 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.115646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 201 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 28.492393 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 197 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 705 # DTB read hits -system.cpu.dtb.read_misses 25 # DTB read misses +system.cpu.dtb.read_hits 688 # DTB read hits +system.cpu.dtb.read_misses 18 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 730 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.dtb.read_accesses 706 # DTB read accesses +system.cpu.dtb.write_hits 353 # DTB write hits +system.cpu.dtb.write_misses 17 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 386 # DTB write accesses -system.cpu.dtb.data_hits 1072 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 370 # DTB write accesses +system.cpu.dtb.data_hits 1041 # DTB hits +system.cpu.dtb.data_misses 35 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1116 # DTB accesses -system.cpu.itb.fetch_hits 947 # ITB hits +system.cpu.dtb.data_accesses 1076 # DTB accesses +system.cpu.itb.fetch_hits 931 # ITB hits system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 973 # ITB accesses +system.cpu.itb.fetch_accesses 957 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 25549 # number of cpu cycles simulated +system.cpu.numCycles 25184 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4412 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6683 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 415 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1538 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4404 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6508 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 403 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1405 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1107 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1109 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 152 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.910863 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.331734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 931 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 153 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.904014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.325149 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6194 84.42% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 50 0.68% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 1.72% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 86 1.17% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 137 1.87% 89.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 59 0.80% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 69 0.94% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 62 0.85% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 554 7.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6086 84.54% 84.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 49 0.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 124 1.72% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 82 1.14% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 134 1.86% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 58 0.81% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 0.92% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 57 0.79% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 543 7.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.043289 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.261576 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5200 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 911 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 995 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 177 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 159 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.043123 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.258418 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5197 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 794 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 178 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5779 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 271 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 177 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5279 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 611 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 960 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5531 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 5639 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 178 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5280 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 486 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 942 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5401 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3966 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6270 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3881 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6086 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2198 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2113 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4768 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 109 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4674 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3966 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1238 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3880 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2292 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1214 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7337 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.540548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.288327 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.538964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.280196 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5813 79.23% 79.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 503 6.86% 86.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 359 4.89% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 255 3.48% 94.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 198 2.70% 97.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 113 1.54% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 62 0.85% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 21 0.29% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5699 79.16% 79.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 500 6.95% 86.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 351 4.88% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 251 3.49% 94.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 194 2.69% 97.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 116 1.61% 98.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 57 0.79% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.29% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7337 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7199 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 18.97% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 37.93% 56.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 25 43.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2817 71.03% 71.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 757 19.09% 90.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 391 9.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2765 71.26% 71.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 738 19.02% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 376 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3966 # Type of FU issued -system.cpu.iq.rate 0.155231 # Inst issue rate -system.cpu.iq.fu_busy_cnt 58 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014624 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15337 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3670 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3880 # Type of FU issued +system.cpu.iq.rate 0.154066 # Inst issue rate +system.cpu.iq.fu_busy_cnt 51 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15012 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6969 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3584 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4017 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3924 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 480 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 177 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 538 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5114 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 178 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5018 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 188 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3845 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 731 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 121 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 168 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3751 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 707 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 129 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 340 # number of nop insts executed -system.cpu.iew.exec_refs 1117 # number of memory reference insts executed -system.cpu.iew.exec_branches 655 # Number of branches executed -system.cpu.iew.exec_stores 386 # Number of stores executed -system.cpu.iew.exec_rate 0.150495 # Inst execution rate -system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3676 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1745 # num instructions producing a value -system.cpu.iew.wb_consumers 2262 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1077 # number of memory reference insts executed +system.cpu.iew.exec_branches 639 # Number of branches executed +system.cpu.iew.exec_stores 370 # Number of stores executed +system.cpu.iew.exec_rate 0.148944 # Inst execution rate +system.cpu.iew.wb_sent 3648 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3590 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1708 # num instructions producing a value +system.cpu.iew.wb_consumers 2182 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.143880 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.771441 # average fanout of values written-back +system.cpu.iew.wb_rate 0.142551 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.782768 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2526 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2428 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 154 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.374800 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.238011 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 155 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.381743 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.245988 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6022 87.62% 87.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192 2.79% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 299 4.35% 94.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 111 1.62% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.05% 97.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 55 0.80% 98.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.48% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5894 87.34% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193 2.86% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 303 4.49% 94.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 109 1.62% 96.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.07% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 56 0.83% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.49% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.30% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6748 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,101 +568,101 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 11659 # The number of ROB reads -system.cpu.rob.rob_writes 10686 # The number of ROB writes +system.cpu.commit.bw_lim_events 68 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 11437 # The number of ROB reads +system.cpu.rob.rob_writes 10476 # The number of ROB writes system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18212 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17985 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.703393 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.703393 # CPI: Total CPI of All Threads -system.cpu.ipc 0.093428 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.093428 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4655 # number of integer regfile reads -system.cpu.int_regfile_writes 2832 # number of integer regfile writes +system.cpu.cpi 10.550482 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.550482 # CPI: Total CPI of All Threads +system.cpu.ipc 0.094782 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.094782 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4532 # number of integer regfile reads +system.cpu.int_regfile_writes 2777 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.039302 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 45.864197 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 731 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.600000 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.039302 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011240 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011240 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.864197 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011197 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011197 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1969 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1969 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 525 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 525 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 218 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 218 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits -system.cpu.dcache.overall_hits::total 743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses -system.cpu.dcache.overall_misses::total 199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8172750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8172750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5678000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5678000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13850750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13850750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13850750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13850750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1937 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1937 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 731 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 731 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 731 # number of overall hits +system.cpu.dcache.overall_hits::total 731 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 195 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 195 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 195 # number of overall misses +system.cpu.dcache.overall_misses::total 195 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7589500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7589500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5666500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5666500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13256000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13256000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13256000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13256000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 632 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 632 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 942 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 942 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 942 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 942 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.189815 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.189815 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.258503 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.258503 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.211253 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.211253 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.211253 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.211253 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66445.121951 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66445.121951 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74710.526316 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74710.526316 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69601.758794 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69601.758794 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 926 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 926 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.210583 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.210583 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.210583 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.210583 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66574.561404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66574.561404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69956.790123 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69956.790123 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67979.487179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67979.487179 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 139 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 110 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 110 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 110 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -671,193 +671,198 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1841500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1841500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6635000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6635000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094136 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6660500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096519 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096519 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090234 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090234 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78581.967213 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78581.967213 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091793 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091793 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78844.262295 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78844.262295 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.893913 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 694 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 91.507771 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 679 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.711230 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.631016 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.893913 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.507771 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044682 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044682 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2081 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2081 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 694 # number of overall hits -system.cpu.icache.overall_hits::total 694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses -system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18914999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18914999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18914999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18914999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18914999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18914999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 947 # number of 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74288.770053 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75086.397059 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -866,55 +871,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 187 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11881250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3969500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15850750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11881250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5489500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17370750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11881250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5489500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17370750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12022000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12022000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12022000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5681500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17703500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12022000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5681500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17703500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63536.096257 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65073.770492 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63914.314516 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64288.770053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64288.770053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67344.262295 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67344.262295 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) @@ -935,14 +945,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 318750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 139500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 248 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) @@ -958,9 +968,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 341000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1440250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1441250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 19e3fb417..7e5bf1bcb 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000048 # Number of seconds simulated -sim_ticks 47840 # Number of ticks simulated -final_tick 47840 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000047 # Number of seconds simulated +sim_ticks 47487 # Number of ticks simulated +final_tick 47487 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 35814 # Simulator instruction rate (inst/s) -host_op_rate 35808 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 664620 # Simulator tick rate (ticks/s) -host_mem_usage 449364 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 68488 # Simulator instruction rate (inst/s) +host_op_rate 68466 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1261208 # Simulator tick rate (ticks/s) +host_mem_usage 449476 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,36 +21,36 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 # system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 837458194 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 837458194 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 832107023 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 832107023 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1669565217 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1669565217 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 843683534 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 843683534 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 838292585 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 838292585 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1681976120 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1681976120 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 626 # Number of read requests accepted system.mem_ctrls.writeReqs 622 # Number of write requests accepted system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24704 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 15360 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 23360 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 24640 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 15424 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 23424 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 240 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 225 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 227 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 24 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 53 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 26 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 31 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts @@ -58,22 +58,22 @@ system.mem_ctrls.perBankRdBursts::15 1 # Pe system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 29 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 24 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 30 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 51 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 46 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 73 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 20 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 14 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 33 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 58 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 52 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 16 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 32 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 61 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 47801 # Total gap between requests +system.mem_ctrls.totGap 47448 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 386 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 385 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,11 +135,11 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 21 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 24 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 25 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 25 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 25 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 23 # What write queue length does an incoming req see @@ -149,11 +149,11 @@ system.mem_ctrls.wrQLenPdf::25 23 # Wh system.mem_ctrls.wrQLenPdf::26 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 22 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -184,87 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 109 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 438.605505 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 303.845174 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 335.937991 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 14 12.84% 12.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 30 27.52% 40.37% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 12 11.01% 51.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 11 10.09% 61.47% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6 5.50% 66.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 8.26% 75.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 9 8.26% 83.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 3.67% 87.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 14 12.84% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 109 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 113 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 424.212389 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 291.141419 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 329.481775 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 17 15.04% 15.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 29 25.66% 40.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 14 12.39% 53.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 9 7.96% 61.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 9 7.96% 69.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 8.85% 77.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 7.08% 84.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 3.54% 88.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 13 11.50% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 113 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.863636 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.473921 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 4.443245 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 13.64% 13.64% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 5 22.73% 36.36% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 9 40.91% 77.27% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 18.18% 95.45% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.622974 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 4.396969 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 9.09% 9.09% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 7 31.82% 40.91% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 7 31.82% 72.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 22.73% 95.45% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.590909 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.555699 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.140555 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.636364 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.592012 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.292670 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 9.09% 86.36% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 13.64% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 4.55% 81.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 13.64% 95.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 4.55% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4080 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11414 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1930 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10.57 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 3756 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 11071 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1925 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 9.76 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29.57 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 516.39 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 488.29 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 837.46 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 832.11 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 28.76 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 518.88 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 493.27 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 843.68 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 838.29 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.85 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.81 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 7.91 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.05 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.85 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.93 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 289 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 349 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 74.87 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 87.91 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 38.30 # Average gap between requests -system.mem_ctrls.pageHitRate 81.48 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 249480 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 138600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 2009280 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1575936 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 24.54 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 294 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 342 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 76.36 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 86.58 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 38.02 # Average gap between requests +system.mem_ctrls.pageHitRate 81.54 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 257040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 142800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2046720 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1638144 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 30369600 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 1545600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 38939856 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 828.930858 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 2928 # Time in different power states +system.mem_ctrls_0.actBackEnergy 30869604 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1107000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 39112668 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 832.609588 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1942 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 43008 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 43739 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 319200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2758080 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2208384 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 597240 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 331800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2733120 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2156544 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 31087116 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 916200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 40914900 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 870.974540 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1359 # Time in different power states +system.mem_ctrls_1.actBackEnergy 31287528 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 740400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 40897992 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 870.614612 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1080 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 44071 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44350 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -300,7 +301,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 47840 # number of cpu cycles simulated +system.cpu.numCycles 47487 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -319,7 +320,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 47840 # Number of busy cycles +system.cpu.num_busy_cycles 47487 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -374,10 +375,10 @@ system.ruby.outstanding_req_hist::total 3295 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 13.523376 -system.ruby.latency_hist::gmean 5.183572 -system.ruby.latency_hist::stdev 25.409311 -system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 13.416211 +system.ruby.latency_hist::gmean 5.177559 +system.ruby.latency_hist::stdev 25.037672 +system.ruby.latency_hist | 3186 96.72% 96.72% | 90 2.73% 99.45% | 15 0.46% 99.91% | 0 0.00% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 3294 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -389,17 +390,17 @@ system.ruby.hit_latency_hist::total 2668 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 626 -system.ruby.miss_latency_hist::mean 58.373802 -system.ruby.miss_latency_hist::gmean 53.319163 -system.ruby.miss_latency_hist::stdev 30.235728 -system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 57.809904 +system.ruby.miss_latency_hist::gmean 52.994493 +system.ruby.miss_latency_hist::stdev 29.424898 +system.ruby.miss_latency_hist | 518 82.75% 82.75% | 90 14.38% 97.12% | 15 2.40% 99.52% | 0 0.00% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 626 system.ruby.Directory.incomplete_times 625 system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.521739 +system.ruby.network.routers0.percent_links_utilized 6.570219 system.ruby.network.routers0.msg_count.Control::2 626 system.ruby.network.routers0.msg_count.Data::2 622 system.ruby.network.routers0.msg_count.Response_Data::4 626 @@ -408,7 +409,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 5008 system.ruby.network.routers0.msg_bytes.Data::2 44784 system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.percent_links_utilized 6.521739 +system.ruby.network.routers1.percent_links_utilized 6.570219 system.ruby.network.routers1.msg_count.Control::2 626 system.ruby.network.routers1.msg_count.Data::2 622 system.ruby.network.routers1.msg_count.Response_Data::4 626 @@ -417,7 +418,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 5008 system.ruby.network.routers1.msg_bytes.Data::2 44784 system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.percent_links_utilized 6.521739 +system.ruby.network.routers2.percent_links_utilized 6.570219 system.ruby.network.routers2.msg_count.Control::2 626 system.ruby.network.routers2.msg_count.Data::2 622 system.ruby.network.routers2.msg_count.Response_Data::4 626 @@ -434,32 +435,32 @@ system.ruby.network.msg_byte.Control 15024 system.ruby.network.msg_byte.Data 134352 system.ruby.network.msg_byte.Response_Data 135216 system.ruby.network.msg_byte.Writeback_Control 14928 -system.ruby.network.routers0.throttle0.link_utilization 6.538462 +system.ruby.network.routers0.throttle0.link_utilization 6.587066 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers0.throttle1.link_utilization 6.505017 +system.ruby.network.routers0.throttle1.link_utilization 6.553373 system.ruby.network.routers0.throttle1.msg_count.Control::2 626 system.ruby.network.routers0.throttle1.msg_count.Data::2 622 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle0.link_utilization 6.505017 +system.ruby.network.routers1.throttle0.link_utilization 6.553373 system.ruby.network.routers1.throttle0.msg_count.Control::2 626 system.ruby.network.routers1.throttle0.msg_count.Data::2 622 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle1.link_utilization 6.538462 +system.ruby.network.routers1.throttle1.link_utilization 6.587066 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle0.link_utilization 6.538462 +system.ruby.network.routers2.throttle0.link_utilization 6.587066 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle1.link_utilization 6.505017 +system.ruby.network.routers2.throttle1.link_utilization 6.553373 system.ruby.network.routers2.throttle1.msg_count.Control::2 626 system.ruby.network.routers2.throttle1.msg_count.Data::2 622 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008 @@ -477,10 +478,10 @@ system.ruby.delayVCHist.vnet_2::total 622 # de system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 415 -system.ruby.LD.latency_hist::mean 33.055422 -system.ruby.LD.latency_hist::gmean 15.599823 -system.ruby.LD.latency_hist::stdev 34.047272 -system.ruby.LD.latency_hist | 375 90.36% 90.36% | 33 7.95% 98.31% | 6 1.45% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 33.036145 +system.ruby.LD.latency_hist::gmean 15.653569 +system.ruby.LD.latency_hist::stdev 33.343638 +system.ruby.LD.latency_hist | 375 90.36% 90.36% | 35 8.43% 98.80% | 4 0.96% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 415 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -492,18 +493,18 @@ system.ruby.LD.hit_latency_hist::total 170 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 245 -system.ruby.LD.miss_latency_hist::mean 53.910204 -system.ruby.LD.miss_latency_hist::gmean 48.970543 -system.ruby.LD.miss_latency_hist::stdev 30.013250 -system.ruby.LD.miss_latency_hist | 205 83.67% 83.67% | 33 13.47% 97.14% | 6 2.45% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 53.877551 +system.ruby.LD.miss_latency_hist::gmean 49.256670 +system.ruby.LD.miss_latency_hist::stdev 28.665419 +system.ruby.LD.miss_latency_hist | 205 83.67% 83.67% | 35 14.29% 97.96% | 4 1.63% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 245 system.ruby.ST.latency_hist::bucket_size 32 system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 294 -system.ruby.ST.latency_hist::mean 17.248299 -system.ruby.ST.latency_hist::gmean 6.615603 -system.ruby.ST.latency_hist::stdev 28.817235 -system.ruby.ST.latency_hist | 210 71.43% 71.43% | 74 25.17% 96.60% | 8 2.72% 99.32% | 0 0.00% 99.32% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.ST.latency_hist::mean 17.955782 +system.ruby.ST.latency_hist::gmean 6.677068 +system.ruby.ST.latency_hist::stdev 30.544793 +system.ruby.ST.latency_hist | 210 71.43% 71.43% | 73 24.83% 96.26% | 7 2.38% 98.64% | 0 0.00% 98.64% | 3 1.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.ST.latency_hist::total 294 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -515,18 +516,18 @@ system.ruby.ST.hit_latency_hist::total 210 system.ruby.ST.miss_latency_hist::bucket_size 32 system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 84 -system.ruby.ST.miss_latency_hist::mean 52.869048 -system.ruby.ST.miss_latency_hist::gmean 47.773810 -system.ruby.ST.miss_latency_hist::stdev 33.671260 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 74 88.10% 88.10% | 8 9.52% 97.62% | 0 0.00% 97.62% | 1 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% +system.ruby.ST.miss_latency_hist::mean 55.345238 +system.ruby.ST.miss_latency_hist::gmean 49.345449 +system.ruby.ST.miss_latency_hist::stdev 36.232680 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 73 86.90% 86.90% | 7 8.33% 95.24% | 0 0.00% 95.24% | 3 3.57% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% system.ruby.ST.miss_latency_hist::total 84 system.ruby.IFETCH.latency_hist::bucket_size 32 system.ruby.IFETCH.latency_hist::max_bucket 319 system.ruby.IFETCH.latency_hist::samples 2585 -system.ruby.IFETCH.latency_hist::mean 9.964023 -system.ruby.IFETCH.latency_hist::gmean 4.224377 -system.ruby.IFETCH.latency_hist::stdev 21.618756 -system.ruby.IFETCH.latency_hist | 2288 88.51% 88.51% | 234 9.05% 97.56% | 49 1.90% 99.46% | 3 0.12% 99.57% | 2 0.08% 99.65% | 7 0.27% 99.92% | 1 0.04% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.750097 +system.ruby.IFETCH.latency_hist::gmean 4.211373 +system.ruby.IFETCH.latency_hist::stdev 20.913083 +system.ruby.IFETCH.latency_hist | 2288 88.51% 88.51% | 240 9.28% 97.79% | 46 1.78% 99.57% | 2 0.08% 99.65% | 2 0.08% 99.73% | 6 0.23% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00% system.ruby.IFETCH.latency_hist::total 2585 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -538,18 +539,18 @@ system.ruby.IFETCH.hit_latency_hist::total 2288 system.ruby.IFETCH.miss_latency_hist::bucket_size 32 system.ruby.IFETCH.miss_latency_hist::max_bucket 319 system.ruby.IFETCH.miss_latency_hist::samples 297 -system.ruby.IFETCH.miss_latency_hist::mean 63.612795 -system.ruby.IFETCH.miss_latency_hist::gmean 58.999958 -system.ruby.IFETCH.miss_latency_hist::stdev 28.587258 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 61.750842 +system.ruby.IFETCH.miss_latency_hist::gmean 57.437802 +system.ruby.IFETCH.miss_latency_hist::stdev 27.433554 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 240 80.81% 80.81% | 46 15.49% 96.30% | 2 0.67% 96.97% | 2 0.67% 97.64% | 6 2.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.IFETCH.miss_latency_hist::total 297 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 626 -system.ruby.Directory.miss_mach_latency_hist::mean 58.373802 -system.ruby.Directory.miss_mach_latency_hist::gmean 53.319163 -system.ruby.Directory.miss_mach_latency_hist::stdev 30.235728 -system.ruby.Directory.miss_mach_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 57.809904 +system.ruby.Directory.miss_mach_latency_hist::gmean 52.994493 +system.ruby.Directory.miss_mach_latency_hist::stdev 29.424898 +system.ruby.Directory.miss_mach_latency_hist | 518 82.75% 82.75% | 90 14.38% 97.12% | 15 2.40% 99.52% | 0 0.00% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 626 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -580,26 +581,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 245 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.910204 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 48.970543 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.013250 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 205 83.67% 83.67% | 33 13.47% 97.14% | 6 2.45% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.877551 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 49.256670 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 28.665419 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 205 83.67% 83.67% | 35 14.29% 97.96% | 4 1.63% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 245 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 84 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.869048 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.773810 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.671260 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 74 88.10% 88.10% | 8 9.52% 97.62% | 0 0.00% 97.62% | 1 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.345238 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.345449 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 36.232680 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 73 86.90% 86.90% | 7 8.33% 95.24% | 0 0.00% 95.24% | 3 3.57% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 84 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 63.612795 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.999958 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.587258 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.750842 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 57.437802 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.433554 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 240 80.81% 80.81% | 46 15.49% 96.30% | 2 0.67% 96.97% | 2 0.67% 97.64% | 6 2.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297 system.ruby.Directory_Controller.GETX 626 0.00% 0.00% system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 364bc6f05..7411927e4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu sim_ticks 16524500 # Number of ticks simulated final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 396950 # Simulator instruction rate (inst/s) -host_op_rate 396157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2535599202 # Simulator tick rate (ticks/s) -host_mem_usage 290048 # Number of bytes of host memory used +host_inst_rate 374183 # Simulator instruction rate (inst/s) +host_op_rate 373424 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2390351512 # Simulator tick rate (ticks/s) +host_mem_usage 291260 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.433873 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 47.431392 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.433873 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 47.431392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011580 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82 system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4387000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4387000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4387000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1458000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4428000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4428000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -216,24 +216,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.042941 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 80.038009 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.042941 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039083 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039083 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 80.038009 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039081 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039081 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id @@ -290,91 +290,96 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8721000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 8721000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8721000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 8721000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8721000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 8721000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8802500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 8802500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8802500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 8802500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8802500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 8802500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54003.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54003.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.153052 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 107.126637 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.161341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.991711 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.141583 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.985054 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003269 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 163 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8558000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11445500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8558000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 8558000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 163 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency @@ -389,55 +394,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6601500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8829000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6601500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3321000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9922500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6601500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3321000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9922500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6928000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6928000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6928000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3485000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10413000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6928000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3485000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10413000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) @@ -462,10 +472,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 218 # Transaction distribution system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 218 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index b37232811..e5ff065c1 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30323500 # Number of ticks simulated -final_tick 30323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29934500 # Number of ticks simulated +final_tick 29934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117134 # Simulator instruction rate (inst/s) -host_op_rate 137081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 770805796 # Simulator tick rate (ticks/s) -host_mem_usage 310084 # Number of bytes of host memory used +host_inst_rate 115469 # Simulator instruction rate (inst/s) +host_op_rate 135130 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 750106498 # Simulator tick rate (ticks/s) +host_mem_usage 310152 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 643725164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 244826620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 888551783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 643725164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 643725164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 643725164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 244826620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 888551783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 652090397 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 248008151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 900098548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 652090397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 652090397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 652090397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 248008151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 900098548 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 30232000 # Total gap between requests +system.physmem.totGap 29844000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,51 +186,51 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 286.758489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.986232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 7.94% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2542750 # Total ticks spent queuing -system.physmem.totMemAccLat 10436500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 2214000 # Total ticks spent queuing +system.physmem.totMemAccLat 10107750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6039.79 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5258.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24789.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 888.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24008.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 900.10 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 888.55 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 900.10 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.94 # Data bus utilization in percentage -system.physmem.busUtilRead 6.94 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.03 # Data bus utilization in percentage +system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 349 # Number of row buffer hits during reads +system.physmem.readRowHits 350 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 71809.98 # Average gap between requests -system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined +system.physmem.avgGap 70888.36 # Average gap between requests +system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ) -system.physmem_0.averagePower 848.348875 # Core power per rank (mW) +system.physmem_0.totalEnergy 20068140 # Total energy per rank (pJ) +system.physmem_0.averagePower 849.669860 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -241,14 +241,14 @@ system.physmem_1.preEnergy 70125 # En system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) -system.physmem_1.averagePower 782.664197 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2433750 # Time in different power states +system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ) +system.physmem_1.averagePower 784.282403 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1918 # Number of BP lookups system.cpu.branchPred.condPredicted 1150 # Number of conditional branches predicted @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 60647 # number of cpu cycles simulated +system.cpu.numCycles 59869 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.169815 # CPI: cycles per instruction -system.cpu.ipc 0.075931 # IPC: instructions per cycle -system.cpu.tickCycles 10567 # Number of cycles that the object actually ticked -system.cpu.idleCycles 50080 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.000869 # CPI: cycles per instruction +system.cpu.ipc 0.076918 # IPC: instructions per cycle +system.cpu.tickCycles 10574 # Number of cycles that the object actually ticked +system.cpu.idleCycles 49295 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.373507 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.493580 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.373507 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021087 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021087 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.493580 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id @@ -423,14 +423,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7248241 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7248241 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12301741 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12301741 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12301741 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12301741 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6956000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 11975500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11975500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11975500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11975500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -451,14 +451,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.182609 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.182609 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67591.983516 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67591.983516 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60486.956522 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60486.956522 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65799.450549 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65799.450549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65799.450549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65799.450549 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,14 +483,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6562258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6562258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9741508 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9741508 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9741508 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9741508 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9551000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9551000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088412 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088412 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -499,27 +499,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070260 system.cpu.dcache.demand_mshr_miss_rate::total 0.070260 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070260 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63711.242718 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63711.242718 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61679.611650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61679.611650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65417.808219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65417.808219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65417.808219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65417.808219 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.448164 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.765243 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.448164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078832 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078832 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.765243 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078987 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078987 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses system.cpu.icache.tags.data_accesses 4784 # Number of data accesses @@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23879500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23879500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23879500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23879500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23879500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23879500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23594000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23594000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23594000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23594000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23594000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23594000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2231 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2231 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses @@ -553,12 +553,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.144330 system.cpu.icache.demand_miss_rate::total 0.144330 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.144330 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.144330 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74159.937888 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74159.937888 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74159.937888 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74159.937888 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73273.291925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73273.291925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73273.291925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73273.291925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73273.291925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73273.291925 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,106 +573,112 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23261500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23261500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23261500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23261500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23261500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23261500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23272000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23272000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23272000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23272000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23272000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23272000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.144330 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.144330 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.144330 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72240.683230 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72240.683230 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72273.291925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72273.291925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.068888 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 195.411120 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.992766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.076122 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004699 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001254 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005953 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.281002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.130118 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005963 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 81 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22761000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6225250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28986250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22761000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9361500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32122500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22761000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9361500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32122500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22610500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22610500 # number of ReadCleanReq miss cycles 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+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.786408 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.908235 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74626.229508 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76854.938272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75093.911917 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74877.622378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74877.622378 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74132.786885 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74132.786885 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73586.419753 # average ReadSharedReq miss latency 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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 378 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18938500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4780750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23719250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18938500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18938500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26318000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19560500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19560500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4700500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4700500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19560500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26964500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19560500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26964500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62093.442623 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65489.726027 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62749.338624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64132.786885 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64132.786885 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64390.410959 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64390.410959 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 378 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 378 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) @@ -779,9 +791,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2238000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 725976bdf..80e232875 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17398000 # Number of ticks simulated -final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17226500 # Number of ticks simulated +final_tick 17226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57922 # Simulator instruction rate (inst/s) -host_op_rate 67825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 219380871 # Simulator tick rate (ticks/s) -host_mem_usage 310080 # Number of bytes of host memory used +host_inst_rate 55427 # Simulator instruction rate (inst/s) +host_op_rate 64904 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 207866253 # Simulator tick rate (ticks/s) +host_mem_usage 311436 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 120 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1015289114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 441430049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1456719163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1015289114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1015289114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1015289114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 441430049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1456719163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1021681711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 449539953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1471221664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1021681711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1021681711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1021681711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 449539953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1471221664 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17318000 # Total gap between requests +system.physmem.totGap 17159000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 410.033898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 279.539573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.305882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9 15.25% 15.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 27.12% 42.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 13.56% 55.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 15.25% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.39% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.39% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3886750 # Total ticks spent queuing -system.physmem.totMemAccLat 11311750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 395.354839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 263.720067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.958245 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.65% 48.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 9.68% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 12.90% 70.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.84% 75.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.23% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.23% 82.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.23% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 3039250 # Total ticks spent queuing +system.physmem.totMemAccLat 10464250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9815.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7674.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28565.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1456.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26424.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1471.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1456.72 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1471.22 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.38 # Data bus utilization in percentage -system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.49 # Data bus utilization in percentage +system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43732.32 # Average gap between requests +system.physmem.avgGap 43330.81 # Average gap between requests system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10748205 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 71250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14332005 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.226907 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 62750 # Time in different power states +system.physmem_0.actBackEnergy 10797795 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14404965 # Total energy per rank (pJ) +system.physmem_0.averagePower 909.404356 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15263500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16109250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 741000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 465000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12744465 # Total energy per rank (pJ) -system.physmem_1.averagePower 804.955945 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 732000 # Time in different power states +system.physmem_1.actBackEnergy 10359180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 412500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12771300 # Total energy per rank (pJ) +system.physmem_1.averagePower 806.650876 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 820250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14594250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14680750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2567 # Number of BP lookups -system.cpu.branchPred.condPredicted 1598 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2576 # Number of BP lookups +system.cpu.branchPred.condPredicted 1602 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2080 # Number of BTB lookups -system.cpu.branchPred.BTBHits 778 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2087 # Number of BTB lookups +system.cpu.branchPred.BTBHits 781 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.403846 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 334 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 37.422137 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 336 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -496,178 +496,178 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34797 # number of cpu cycles simulated +system.cpu.numCycles 34454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7703 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12168 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2567 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1112 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4777 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 7709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12205 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2576 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1117 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2007 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13242 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.084202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.460827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2016 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.088585 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.463952 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10620 80.20% 80.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.07% 82.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 209 1.58% 83.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.68% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 233 1.76% 87.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 323 2.44% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 137 1.03% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 162 1.22% 91.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1062 8.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10589 80.10% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.07% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 212 1.60% 83.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 221 1.67% 85.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 236 1.79% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 324 2.45% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 161 1.22% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1063 8.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13242 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073771 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4330 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2103 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.074766 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.354240 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6369 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2102 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11850 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11852 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6554 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 6584 # Number of cycles rename is idle system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2396 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2012 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11194 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 171 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1066 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11323 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51655 # Number of register rename lookups that rename has made +system.cpu.rename.serializeStallCycles 2356 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2013 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1236 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11200 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1064 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11331 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51672 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5829 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 42 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 409 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2284 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 5837 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10118 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10125 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8189 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4786 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12366 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4793 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12371 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13242 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.618411 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365218 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.620471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365465 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10034 75.77% 75.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1166 8.81% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 746 5.63% 90.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 448 3.38% 93.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 359 2.71% 96.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 279 2.11% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10002 75.66% 75.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1166 8.82% 84.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 755 5.71% 90.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 451 3.41% 93.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.70% 96.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.10% 98.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 62 0.47% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 63 0.48% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 16 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13242 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13219 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.20% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 84 48.55% 53.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 80 46.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.26% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 84 49.12% 54.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 45.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4931 60.21% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1952 23.84% 84.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1297 15.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4937 60.19% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1959 23.88% 84.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1297 15.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8189 # Type of FU issued -system.cpu.iq.rate 0.235336 # Inst issue rate -system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021126 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29748 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14841 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7422 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8202 # Type of FU issued +system.cpu.iq.rate 0.238057 # Inst issue rate +system.cpu.iq.fu_busy_cnt 171 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020849 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29750 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14855 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7430 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8319 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8330 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1257 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1260 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed @@ -677,56 +677,56 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 32 # system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 662 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10173 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2284 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 660 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10180 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 233 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 344 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7858 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1841 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 331 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 234 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7868 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1843 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 334 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 3070 # number of memory reference insts executed -system.cpu.iew.exec_branches 1431 # Number of branches executed +system.cpu.iew.exec_refs 3072 # number of memory reference insts executed +system.cpu.iew.exec_branches 1434 # Number of branches executed system.cpu.iew.exec_stores 1229 # Number of stores executed -system.cpu.iew.exec_rate 0.225824 # Inst execution rate -system.cpu.iew.wb_sent 7567 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7454 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3520 # num instructions producing a value -system.cpu.iew.wb_consumers 6887 # num instructions consuming a value +system.cpu.iew.exec_rate 0.228362 # Inst execution rate +system.cpu.iew.wb_sent 7574 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7462 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3524 # num instructions producing a value +system.cpu.iew.wb_consumers 6897 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.214214 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511108 # average fanout of values written-back +system.cpu.iew.wb_rate 0.216579 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510947 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4794 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4801 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.280415 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12382 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.434340 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.281233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10350 83.44% 83.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 890 7.18% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.39% 94.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 213 1.72% 95.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 118 0.95% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 211 1.70% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10327 83.40% 83.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 891 7.20% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 421 3.40% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 214 1.73% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 114 0.92% 96.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 212 1.71% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12382 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -772,121 +772,121 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22302 # The number of ROB reads -system.cpu.rob.rob_writes 21197 # The number of ROB writes -system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22289 # The number of ROB reads +system.cpu.rob.rob_writes 21210 # The number of ROB writes +system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21235 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.577744 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.577744 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131965 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131965 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7744 # number of integer regfile reads -system.cpu.int_regfile_writes 4257 # number of integer regfile writes +system.cpu.cpi 7.503049 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.503049 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133279 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133279 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7752 # number of integer regfile reads +system.cpu.int_regfile_writes 4259 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28092 # number of cc regfile reads -system.cpu.cc_regfile_writes 3277 # number of cc regfile writes -system.cpu.misc_regfile_reads 3176 # number of misc regfile reads +system.cpu.cc_regfile_reads 28119 # number of cc regfile reads +system.cpu.cc_regfile_writes 3280 # number of cc regfile writes +system.cpu.misc_regfile_reads 3175 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.050512 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2159 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.687075 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.080084 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2156 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.767123 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.050512 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021253 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021253 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 87.080084 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021260 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021260 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5463 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5463 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1539 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1539 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5466 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5466 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1537 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1537 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits -system.cpu.dcache.overall_hits::total 2137 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 182 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 182 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2134 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2134 # number of overall hits +system.cpu.dcache.overall_hits::total 2134 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10876493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10876493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22731000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22731000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33607493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33607493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33607493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33607493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10668000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10668000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22567500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22567500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33235500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33235500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33235500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33235500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1723 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2634 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2634 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.105752 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.105752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107951 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.107951 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.188686 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.188686 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.188686 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.188686 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67620.710262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67620.710262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.190440 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.190440 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190440 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.190440 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57354.838710 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57354.838710 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71416.139241 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71416.139241 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66206.175299 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66206.175299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66206.175299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66206.175299 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,82 +895,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6879255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6879255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10269755 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10269755 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10269755 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10269755 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.061011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6685000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6685000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10091500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10091500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060940 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060940 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055809 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055809 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055766 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055766 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63666.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63666.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81107.142857 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68649.659864 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68649.659864 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68649.659864 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68649.659864 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.166565 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.175552 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1623 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.505119 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.539249 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.166565 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072835 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072835 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.175552 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072840 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072840 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4307 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4307 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits -system.cpu.icache.overall_hits::total 1613 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses -system.cpu.icache.overall_misses::total 394 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28003250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28003250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28003250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28003250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28003250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28003250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2007 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2007 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2007 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2007 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2007 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2007 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196313 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196313 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196313 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196313 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196313 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196313 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71074.238579 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71074.238579 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4325 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4325 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1623 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1623 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1623 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1623 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1623 # number of overall hits +system.cpu.icache.overall_hits::total 1623 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 393 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 393 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 393 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 393 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 393 # number of overall misses +system.cpu.icache.overall_misses::total 393 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27030000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27030000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27030000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27030000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27030000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27030000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2016 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2016 # number of demand (read+write) accesses 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+system.cpu.icache.demand_avg_miss_latency::total 68778.625954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68778.625954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68778.625954 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -979,118 +979,124 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 100 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 100 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 100 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 293 # number of 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accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941980 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.850340 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79086 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78782.418953 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79086 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78782.418953 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76154.545455 # average ReadCleanReq miss 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blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1099,89 +1105,94 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR 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+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 120 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18264000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5236000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23500000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18264000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8060500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26324500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18264000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8060500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26324500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.742857 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18192500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18192500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5250500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5250500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18192500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8173000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26365500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18192500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8173000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26365500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67250 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67250 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69583.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69583.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66154.545455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66154.545455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66462.025316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66462.025316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66154.545455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67545.454545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66579.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66154.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67545.454545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66579.545455 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 879 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 493000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239245 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 354 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) @@ -1197,9 +1208,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 396 # Request fanout histogram -system.membus.reqLayer0.occupancy 497000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2092000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.0 # Layer utilization (%) +system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2095750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 835d1798d..65214b87e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17788000 # Number of ticks simulated -final_tick 17788000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17777000 # Number of ticks simulated +final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23007 # Simulator instruction rate (inst/s) -host_op_rate 26942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89104120 # Simulator tick rate (ticks/s) -host_mem_usage 300104 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 63568 # Simulator instruction rate (inst/s) +host_op_rate 74435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 246000775 # Simulator tick rate (ticks/s) +host_mem_usage 307848 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975039352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 388576568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 97144142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1460760063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975039352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975039352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975039352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 388576568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 97144142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1460760063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue @@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17774500 # Total gap between requests +system.physmem.totGap 17763500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -94,8 +94,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -204,65 +204,65 @@ system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # By system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3111242 # Total ticks spent queuing -system.physmem.totMemAccLat 10742492 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3256492 # Total ticks spent queuing +system.physmem.totMemAccLat 10887742 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7644.33 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8001.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26394.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1464.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26751.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1464.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.44 # Data bus utilization in percentage -system.physmem.busUtilRead 11.44 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.45 # Data bus utilization in percentage +system.physmem.busUtilRead 11.45 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 340 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43671.99 # Average gap between requests +system.physmem.avgGap 43644.96 # Average gap between requests system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10829430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14375115 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.162692 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 243500 # Time in different power states +system.physmem_0.actBackEnergy 10756755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14336940 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.538607 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 334000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15368000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15275500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10100115 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 639750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12751230 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.383231 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1024000 # Time in different power states +system.physmem_1.actBackEnergy 10156545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 590250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12758160 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.820938 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 942000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14302250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14384250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2340 # Number of BP lookups -system.cpu.branchPred.condPredicted 1388 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 507 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups +system.cpu.branchPred.lookups 2336 # Number of BP lookups +system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 837 # Number of BTB lookups system.cpu.branchPred.BTBHits 442 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.744630 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.807646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 289 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35577 # number of cpu cycles simulated +system.cpu.numCycles 35555 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6129 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11284 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2340 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 732 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1057 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 6172 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3831 # Number of cache lines fetched +system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14930 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.882251 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.211921 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.878021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.210560 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8724 58.43% 58.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2462 16.49% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 522 3.50% 78.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3222 21.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8782 58.63% 58.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2458 16.41% 75.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.48% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3217 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14930 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065773 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.317171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5843 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3543 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5049 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5039 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9870 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1626 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 964 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 605 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8889 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 403 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.decode.DecodedInsts 9859 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1620 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 960 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4095 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 601 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8880 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 409 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40319 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9768 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 527 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9231 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40283 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9759 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3746 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3737 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 1806 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1281 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8360 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8347 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7147 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3021 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7902 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7144 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3008 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7841 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14930 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.478701 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.863585 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.476966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.861224 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10739 71.93% 71.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1936 12.97% 84.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1601 10.72% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 4.07% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 47 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10780 71.97% 71.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1947 13.00% 84.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1601 10.69% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 605 4.04% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14930 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14978 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 420 29.23% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 467 32.50% 61.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 550 38.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 411 28.90% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 464 32.63% 61.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 547 38.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4466 62.49% 62.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1084 15.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4467 62.53% 62.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1588 22.23% 84.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7147 # Type of FU issued -system.cpu.iq.rate 0.200888 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1437 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.201063 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30806 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11411 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6546 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7144 # Type of FU issued +system.cpu.iq.rate 0.200928 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1422 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199048 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30828 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11385 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8556 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8538 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 779 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 343 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 358 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8413 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 356 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8400 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 1806 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1281 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6739 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1406 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6741 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2430 # number of memory reference insts executed -system.cpu.iew.exec_branches 1270 # Number of branches executed -system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.189420 # Inst execution rate -system.cpu.iew.wb_sent 6605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6562 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2976 # num instructions producing a value -system.cpu.iew.wb_consumers 5371 # num instructions consuming a value +system.cpu.iew.exec_refs 2427 # number of memory reference insts executed +system.cpu.iew.exec_branches 1272 # Number of branches executed +system.cpu.iew.exec_stores 1023 # Number of stores executed +system.cpu.iew.exec_rate 0.189594 # Inst execution rate +system.cpu.iew.wb_sent 6608 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2973 # num instructions producing a value +system.cpu.iew.wb_consumers 5368 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184445 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554087 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184672 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553838 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2578 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2565 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14390 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.373732 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.023936 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.372515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.021269 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11747 81.63% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1377 9.57% 91.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 605 4.20% 95.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 294 2.04% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.17% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 77 0.54% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 32 0.22% 99.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 44 0.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11787 81.64% 81.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1388 9.61% 91.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 602 4.17% 95.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 293 2.03% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.16% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.54% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 45 0.31% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14437 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,121 +654,121 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22145 # The number of ROB reads -system.cpu.rob.rob_writes 16457 # The number of ROB writes -system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20647 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22180 # The number of ROB reads +system.cpu.rob.rob_writes 16432 # The number of ROB writes +system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20577 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.747605 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.747605 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129072 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129072 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6713 # number of integer regfile reads +system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6717 # number of integer regfile reads system.cpu.int_regfile_writes 3745 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23953 # number of cc regfile reads -system.cpu.cc_regfile_writes 2889 # number of cc regfile writes -system.cpu.misc_regfile_reads 2609 # number of misc regfile reads +system.cpu.cc_regfile_reads 23956 # number of cc regfile reads +system.cpu.cc_regfile_writes 2895 # number of cc regfile writes +system.cpu.misc_regfile_reads 2607 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.188922 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.382295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.507042 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.188922 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164431 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164431 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.382295 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164809 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4696 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4696 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1176 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1176 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4692 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4692 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1173 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1173 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1898 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1898 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1898 # number of overall hits -system.cpu.dcache.overall_hits::total 1898 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits +system.cpu.dcache.overall_hits::total 1895 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses -system.cpu.dcache.overall_misses::total 357 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9257492 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9257492 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16534742 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16534742 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16534742 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16534742 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses +system.cpu.dcache.overall_misses::total 358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7245500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7245500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16445000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16445000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16445000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16445000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2255 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2255 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2255 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2255 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123696 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123696 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2253 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2253 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2253 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2253 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124627 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158315 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158315 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158315 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158315 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55768.024096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55768.024096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46315.803922 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46315.803922 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46315.803922 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46315.803922 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37934.554974 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37934.554974 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45935.754190 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45935.754190 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 731 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 40.611111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -777,120 +777,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8163505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8163505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8163505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8163505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2385500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2385500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8215000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8215000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8215000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8215000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063415 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063415 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063415 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063415 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56821.127451 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56821.127451 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57087.447552 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57087.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57087.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57087.447552 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58182.926829 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58182.926829 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.057531 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3467 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.424572 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.752542 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.057531 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.265737 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.265737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.424572 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.266454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.266454 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7955 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7955 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3467 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3467 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3467 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3467 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3467 # number of overall hits -system.cpu.icache.overall_hits::total 3467 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21749991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21749991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21749991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21749991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21749991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21749991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3830 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3830 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3830 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3830 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3830 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3830 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094778 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094778 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094778 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094778 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094778 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094778 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59917.330579 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59917.330579 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59917.330579 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59917.330579 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59917.330579 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59917.330579 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8313 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7941 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits +system.cpu.icache.overall_hits::total 3459 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21691493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21691493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21691493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21691493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21691493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21691493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59592.013736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59592.013736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59592.013736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59592.013736 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8521 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 90 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.366667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 95.741573 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18653743 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18653743 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18653743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18653743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18653743 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18653743 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077285 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077285 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077285 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63019.402027 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63019.402027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63019.402027 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 63019.402027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63019.402027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 63019.402027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18899993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18899993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18899993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18899993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18899993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18899993 # number of overall MSHR miss cycles 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latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,94 +899,100 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 192.560599 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 193.028614 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.115385 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.350778 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.044062 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.165759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002749 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000559 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011753 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.716720 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.124038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.187855 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002754 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011782 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7429 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7429 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 7941 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7941 # Number of data accesses system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 23 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 19 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 19 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 30 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 53 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits system.cpu.l2cache.overall_hits::total 53 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 273 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 273 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 83 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 386 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses system.cpu.l2cache.overall_misses::total 386 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18354000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5568750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23922750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2253750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18354000 # number of demand (read+write) miss cycles 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18451000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18451000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18451000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7800000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26251000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18451000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7800000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26251000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq 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system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922297 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.894472 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.922297 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.922297 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.813725 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.813725 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67230.769231 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67093.373494 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67198.735955 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67230.769231 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69225.663717 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67814.766839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67230.769231 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69225.663717 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67814.766839 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75033.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75033.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67586.080586 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67586.080586 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68007.772021 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68007.772021 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -995,22 +1001,24 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # 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(read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6620500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22614500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6620500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24256417 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1697924 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16769500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16769500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16769500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6859500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23629000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16769500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6859500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25326924 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.918919 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.764706 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses @@ -1046,54 +1056,57 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58801.470588 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59201.923077 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58890.714286 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58801.470588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61300.925926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59511.842105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58801.470588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61300.925926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56673.871495 # average overall mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35373.416667 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69033.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69033.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61652.573529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61652.573529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62181.578947 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59175.056075 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 623 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 64 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.127237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 439 87.28% 87.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64 12.72% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 496999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 377 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 442999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 215495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 375 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) @@ -1109,9 +1122,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 508443 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 510442 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2142008 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2136258 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index eccfa92c7..85d747802 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25816500 # Number of ticks simulated final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77759 # Simulator instruction rate (inst/s) -host_op_rate 90742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 439383785 # Simulator tick rate (ticks/s) -host_mem_usage 301384 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 428411 # Simulator instruction rate (inst/s) +host_op_rate 499438 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2416370273 # Simulator tick rate (ticks/s) +host_mem_usage 308620 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -384,100 +384,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits system.cpu.l2cache.overall_hits::total 32 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11818000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 11818000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4305000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4305000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency @@ -492,55 +498,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3485000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3485000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14880500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14880500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) @@ -548,27 +559,27 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 307 # Transaction distribution system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 8ffb75804..5213b7cc0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22762000 # Number of ticks simulated -final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22403000 # Number of ticks simulated +final_tick 22403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3472 # Simulator instruction rate (inst/s) -host_op_rate 3472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15849922 # Simulator tick rate (ticks/s) -host_mem_usage 223436 # Number of bytes of host memory used -host_seconds 1.44 # Real time elapsed on the host +host_inst_rate 79030 # Simulator instruction rate (inst/s) +host_op_rate 79012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 354943993 # Simulator tick rate (ticks/s) +host_mem_usage 292784 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21120 # Nu system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 471 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 927862227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 396450224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1324312451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 927862227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 927862227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 927862227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 396450224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1324312451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 942730884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 402803196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1345534080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 942730884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 942730884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 942730884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 402803196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1345534080 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 471 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22674500 # Total gap between requests +system.physmem.totGap 22316000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,9 +92,9 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.184943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.583818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28 26.92% 26.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 35 33.65% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 18 17.31% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 9.62% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 2.88% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation -system.physmem.totQLat 5218000 # Total ticks spent queuing -system.physmem.totMemAccLat 14049250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 260.876190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.828028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.099908 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.52% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 2.86% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 0.95% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.95% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation +system.physmem.totQLat 4348750 # Total ticks spent queuing +system.physmem.totMemAccLat 13180000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11078.56 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9233.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29828.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1324.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27983.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1345.53 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1324.31 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1345.53 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.35 # Data bus utilization in percentage -system.physmem.busUtilRead 10.35 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.51 # Data bus utilization in percentage +system.physmem.busUtilRead 10.51 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48141.19 # Average gap between requests +system.physmem.avgGap 47380.04 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 491400 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9465705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1196250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12369120 # Total energy per rank (pJ) -system.physmem_0.averagePower 781.248697 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1950500 # Time in different power states +system.physmem_0.actBackEnergy 9525555 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1143750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12423270 # Total energy per rank (pJ) +system.physmem_0.averagePower 784.668877 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2113750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13375750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13462250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2191800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14812845 # Total energy per rank (pJ) -system.physmem_1.averagePower 935.597347 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 284750 # Time in different power states +system.physmem_1.actBackEnergy 10738800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14840985 # Total energy per rank (pJ) +system.physmem_1.averagePower 936.635216 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15222250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15234500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2110 # Number of BP lookups -system.cpu.branchPred.condPredicted 1371 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 423 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1629 # Number of BTB lookups -system.cpu.branchPred.BTBHits 525 # Number of BTB hits +system.cpu.branchPred.lookups 2126 # Number of BP lookups +system.cpu.branchPred.condPredicted 1379 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups +system.cpu.branchPred.BTBHits 514 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.228361 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.322364 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 281 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -279,236 +279,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 45525 # number of cpu cycles simulated +system.cpu.numCycles 44807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8934 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12895 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2110 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 805 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing -system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14478 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.890662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.186824 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8961 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12993 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2126 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 795 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4908 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 876 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 194 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2040 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.896007 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.195594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11164 77.11% 77.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1470 10.15% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 124 0.86% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 160 1.11% 89.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 1.95% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 94 0.65% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 128 0.88% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 113 0.78% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 942 6.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11177 77.08% 77.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1470 10.14% 87.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 121 0.83% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 160 1.10% 89.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 1.95% 91.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 95 0.66% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 127 0.88% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 112 0.77% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 956 6.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14478 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.046348 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.283251 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2706 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2773 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 391 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.047448 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.289977 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2687 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2777 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 172 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11880 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 391 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8645 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1002 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2724 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1214 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11398 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 12008 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 170 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8669 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 506 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2735 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1198 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11509 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 231 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 967 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13412 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13162 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 229 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6966 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13566 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13315 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3597 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 13 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 290 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2474 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1168 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3684 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 296 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8940 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9007 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3964 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8237 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4031 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1845 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.566653 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.310295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.568030 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.308332 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11167 77.13% 77.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1314 9.08% 86.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 734 5.07% 91.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 423 2.92% 94.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 344 2.38% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 310 2.14% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 102 0.70% 99.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 57 0.39% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 27 0.19% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11165 76.99% 76.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1330 9.17% 86.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 739 5.10% 91.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 423 2.92% 94.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 353 2.43% 96.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 304 2.10% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 105 0.72% 99.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 58 0.40% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 24 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14478 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14501 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 4.59% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 129 65.82% 70.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 131 66.84% 70.41% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4822 58.78% 58.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2303 28.07% 86.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1072 13.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4840 58.76% 58.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2319 28.15% 87.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1071 13.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8204 # Type of FU issued -system.cpu.iq.rate 0.180209 # Inst issue rate +system.cpu.iq.FU_type_0::total 8237 # Type of FU issued +system.cpu.iq.rate 0.183833 # Inst issue rate system.cpu.iq.fu_busy_cnt 196 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12922 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.023795 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31205 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13056 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7426 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8398 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8431 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1342 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 267 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 391 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 464 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10483 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2474 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1168 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 472 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 155 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 348 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 444 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7875 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7898 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2175 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 339 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1532 # number of nop insts executed -system.cpu.iew.exec_refs 3217 # number of memory reference insts executed -system.cpu.iew.exec_branches 1365 # Number of branches executed -system.cpu.iew.exec_stores 1057 # Number of stores executed -system.cpu.iew.exec_rate 0.172982 # Inst execution rate -system.cpu.iew.wb_sent 7509 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7410 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2869 # num instructions producing a value -system.cpu.iew.wb_consumers 4254 # num instructions consuming a value +system.cpu.iew.exec_nop 1543 # number of nop insts executed +system.cpu.iew.exec_refs 3228 # number of memory reference insts executed +system.cpu.iew.exec_branches 1368 # Number of branches executed +system.cpu.iew.exec_stores 1053 # Number of stores executed +system.cpu.iew.exec_rate 0.176267 # Inst execution rate +system.cpu.iew.wb_sent 7529 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7428 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2859 # num instructions producing a value +system.cpu.iew.wb_consumers 4251 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.162768 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.674424 # average fanout of values written-back +system.cpu.iew.wb_rate 0.165778 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672548 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4860 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4937 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.412758 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.228786 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 388 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13632 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.412485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.223639 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11456 84.09% 84.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 871 6.39% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 510 3.74% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 252 1.85% 96.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.09% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 178 1.31% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.48% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.29% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103 0.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11448 83.98% 83.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 886 6.50% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 511 3.75% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 255 1.87% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 161 1.18% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 164 1.20% 98.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.48% 98.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13632 # Number of insts commited each cycle system.cpu.commit.committedInsts 5623 # Number of instructions committed system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,101 +554,101 @@ system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5623 # Class of committed instruction -system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23990 # The number of ROB reads -system.cpu.rob.rob_writes 21831 # The number of ROB writes -system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 24077 # The number of ROB reads +system.cpu.rob.rob_writes 22001 # The number of ROB writes +system.cpu.timesIdled 266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30306 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads -system.cpu.ipc 0.109522 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.109522 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10639 # number of integer regfile reads -system.cpu.int_regfile_writes 5201 # number of integer regfile writes +system.cpu.cpi 8.986562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.986562 # CPI: Total CPI of All Threads +system.cpu.ipc 0.111277 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.111277 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10682 # number of integer regfile reads +system.cpu.int_regfile_writes 5223 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 165 # number of misc regfile reads +system.cpu.misc_regfile_reads 167 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.212769 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2418 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.242537 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2427 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.148936 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.212766 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.212769 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022269 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.242537 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022276 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022276 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5997 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5997 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1862 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1862 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 6025 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6025 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1871 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1871 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits -system.cpu.dcache.overall_hits::total 2418 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2427 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2427 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2427 # number of overall hits +system.cpu.dcache.overall_hits::total 2427 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses -system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12038750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12038750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24387249 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24387249 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36425999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36425999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36425999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36425999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2027 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2027 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses +system.cpu.dcache.overall_misses::total 515 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11738500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11738500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24073999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24073999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35812499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35812499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35812499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35812499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2041 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2041 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081401 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083293 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083293 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174180 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174180 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174180 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174180 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71423.527451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71423.527451 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.175051 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175051 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175051 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175051 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69050 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69050 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69779.707246 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69779.707246 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69538.833010 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69538.833010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69538.833010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69538.833010 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 615 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.909091 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -657,82 +657,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7833500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7833500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4084749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4084749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11918249 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11918249 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11918249 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11918249 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044894 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044894 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4094999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4094999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11681499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11681499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11681499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11681499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044586 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044586 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048156 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048156 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047927 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047927 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83368.131868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83368.131868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81899.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81899.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82847.510638 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82847.510638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82847.510638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82847.510638 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.205778 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.208729 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1588 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.735736 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.768769 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.205778 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077249 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077249 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.208729 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4385 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4385 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits -system.cpu.icache.overall_hits::total 1577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 449 # number of overall misses -system.cpu.icache.overall_misses::total 449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34003000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34003000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34003000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34003000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34003000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34003000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses 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-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75730.512249 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75730.512249 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4413 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4413 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1588 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1588 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1588 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1588 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1588 # number of overall hits +system.cpu.icache.overall_hits::total 1588 # number of overall hits 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of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2040 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2040 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2040 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2040 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221569 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.221569 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.221569 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.221569 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.221569 # miss rate for overall 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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25884000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25884000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25884000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25884000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25884000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25884000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163235 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.163235 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.163235 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77729.729730 # average ReadReq mshr miss latency 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system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.047506 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.168468 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.981967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004888 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006657 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.142310 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 58.097265 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004887 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses 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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990991 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990991 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990991 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.993671 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80680 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80680 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80380 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80380 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76827.272727 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76827.272727 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81829.670330 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81829.670330 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76827.272727 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81315.602837 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78170.912951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76827.272727 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81315.602837 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78170.912951 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -858,83 +863,89 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 330 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 330 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 91 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 471 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21894000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6598000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28492000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3411000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3411000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21894000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10009000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31903000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21894000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10009000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31903000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22053000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22053000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6536500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6536500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22053000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10055500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32108500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22053000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10055500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32108500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68220 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68220 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70380 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70380 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66827.272727 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66827.272727 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71829.670330 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71829.670330 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66827.272727 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71315.602837 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68170.912951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66827.272727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71315.602837 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68170.912951 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 965 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 569000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 421 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 499500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.membus.trans_dist::ReadResp 421 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 421 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) @@ -950,9 +961,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 598000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2506000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2503500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 8476aa73a..c6923a4b0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000115 # Number of seconds simulated -sim_ticks 115467 # Number of ticks simulated -final_tick 115467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 115089 # Number of ticks simulated +final_tick 115089 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 66709 # Simulator instruction rate (inst/s) -host_op_rate 66698 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1369179 # Simulator tick rate (ticks/s) -host_mem_usage 449556 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 64252 # Simulator instruction rate (inst/s) +host_op_rate 64242 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1314462 # Simulator tick rate (ticks/s) +host_mem_usage 449728 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 814778248 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 814778248 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 812561165 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 812561165 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1627339413 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1627339413 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 817454318 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 817454318 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 815229952 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 815229952 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1632684270 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1632684270 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1470 # Number of read requests accepted system.mem_ctrls.writeReqs 1466 # Number of write requests accepted system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 59456 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 34624 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 60800 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 58496 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 35584 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 59392 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 491 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 556 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 513 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 88 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 248 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 103 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 158 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 36 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 78 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 115 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 165 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 33 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 249 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 114 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 182 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 16 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 245 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 98 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 186 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 115396 # Total gap between requests +system.mem_ctrls.totGap 115018 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 914 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,26 +135,26 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 13 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 62 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 11 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 61 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -184,89 +184,89 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 362 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 330.077348 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 218.964738 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 303.831296 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 84 23.20% 23.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 104 28.73% 51.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 58 16.02% 67.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 36 9.94% 77.90% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 19 5.25% 83.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 2.76% 85.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 9 2.49% 88.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 1.38% 89.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 37 10.22% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 362 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.105263 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.953786 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.697116 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 1.75% 1.75% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 45.61% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.637263 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.023533 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 37 64.91% 64.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 6 10.53% 75.44% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 11 19.30% 94.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 3.51% 98.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12340 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 29991 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4645 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.28 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 343 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 339.965015 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 217.922152 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 320.777927 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 88 25.66% 25.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 98 28.57% 54.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 42 12.24% 66.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 32 9.33% 75.80% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 4.66% 80.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 13 3.79% 84.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 2.33% 86.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.46% 88.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 41 11.95% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 343 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 56 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.125000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.967614 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.737368 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 3.57% 3.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 19 33.93% 37.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 27 48.21% 85.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 7 12.50% 98.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 1.79% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 56 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 56 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.571429 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.541189 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.041976 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 41 73.21% 73.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 3 5.36% 78.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 8 14.29% 92.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 5.36% 98.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 1.79% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 56 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 12397 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 29763 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4570 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.56 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.28 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 514.92 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 526.56 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 814.78 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 812.56 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.56 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 508.27 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 516.05 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 817.45 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 815.23 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.14 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.02 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.00 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.03 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.24 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 618 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 892 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 66.52 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.49 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 39.30 # Average gap between requests -system.mem_ctrls.pageHitRate 79.31 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1684800 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1327104 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 25.10 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 631 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 861 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 69.04 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.35 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 39.18 # Average gap between requests +system.mem_ctrls.pageHitRate 79.91 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 544320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 302400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1522560 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1202688 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 54116712 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 18087600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 83206296 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 761.516108 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 29701 # Time in different power states +system.mem_ctrls_0.actBackEnergy 49529808 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 22111200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 82332816 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 753.521892 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 36376 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 76066 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 69262 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 2079000 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 1155000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 9372480 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1988280 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1104600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 9397440 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 8076672 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 74259144 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 418800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 102397992 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 937.161297 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 278 # Time in different power states +system.mem_ctrls_1.actBackEnergy 74119608 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 541200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102347640 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 936.700469 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1449 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 105360 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 105142 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -288,7 +288,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 115467 # number of cpu cycles simulated +system.cpu.numCycles 115089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -307,7 +307,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 115467 # Number of busy cycles +system.cpu.num_busy_cycles 115089 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -362,10 +362,10 @@ system.ruby.outstanding_req_hist::total 7659 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 14.077958 -system.ruby.latency_hist::gmean 5.242569 -system.ruby.latency_hist::stdev 26.858459 -system.ruby.latency_hist | 7322 95.61% 95.61% | 283 3.70% 99.31% | 37 0.48% 99.79% | 6 0.08% 99.87% | 9 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 14.028598 +system.ruby.latency_hist::gmean 5.234161 +system.ruby.latency_hist::stdev 27.167008 +system.ruby.latency_hist | 7344 95.90% 95.90% | 261 3.41% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 9 0.12% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 7658 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -377,17 +377,17 @@ system.ruby.hit_latency_hist::total 6188 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 60.710884 -system.ruby.miss_latency_hist::gmean 54.957755 -system.ruby.miss_latency_hist::stdev 32.665540 -system.ruby.miss_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 60.453741 +system.ruby.miss_latency_hist::gmean 54.500138 +system.ruby.miss_latency_hist::stdev 34.320124 +system.ruby.miss_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1470 system.ruby.Directory.incomplete_times 1469 system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.356795 +system.ruby.network.routers0.percent_links_utilized 6.377673 system.ruby.network.routers0.msg_count.Control::2 1470 system.ruby.network.routers0.msg_count.Data::2 1466 system.ruby.network.routers0.msg_count.Response_Data::4 1470 @@ -396,7 +396,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11760 system.ruby.network.routers0.msg_bytes.Data::2 105552 system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers1.percent_links_utilized 6.356795 +system.ruby.network.routers1.percent_links_utilized 6.377673 system.ruby.network.routers1.msg_count.Control::2 1470 system.ruby.network.routers1.msg_count.Data::2 1466 system.ruby.network.routers1.msg_count.Response_Data::4 1470 @@ -405,7 +405,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11760 system.ruby.network.routers1.msg_bytes.Data::2 105552 system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 6.356795 +system.ruby.network.routers2.percent_links_utilized 6.377673 system.ruby.network.routers2.msg_count.Control::2 1470 system.ruby.network.routers2.msg_count.Data::2 1466 system.ruby.network.routers2.msg_count.Response_Data::4 1470 @@ -422,32 +422,32 @@ system.ruby.network.msg_byte.Control 35280 system.ruby.network.msg_byte.Data 316656 system.ruby.network.msg_byte.Response_Data 317520 system.ruby.network.msg_byte.Writeback_Control 35184 -system.ruby.network.routers0.throttle0.link_utilization 6.363723 +system.ruby.network.routers0.throttle0.link_utilization 6.384624 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 6.349866 +system.ruby.network.routers0.throttle1.link_utilization 6.370722 system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 6.349866 +system.ruby.network.routers1.throttle0.link_utilization 6.370722 system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 6.363723 +system.ruby.network.routers1.throttle1.link_utilization 6.384624 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 6.363723 +system.ruby.network.routers2.throttle0.link_utilization 6.384624 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 6.349866 +system.ruby.network.routers2.throttle1.link_utilization 6.370722 system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 @@ -462,13 +462,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 35.492049 -system.ruby.LD.latency_hist::gmean 16.147834 -system.ruby.LD.latency_hist::stdev 37.303839 -system.ruby.LD.latency_hist | 465 41.08% 41.08% | 518 45.76% 86.84% | 124 10.95% 97.79% | 3 0.27% 98.06% | 3 0.27% 98.32% | 12 1.06% 99.38% | 2 0.18% 99.56% | 0 0.00% 99.56% | 3 0.27% 99.82% | 2 0.18% 100.00% +system.ruby.LD.latency_hist::mean 35.838339 +system.ruby.LD.latency_hist::gmean 16.062923 +system.ruby.LD.latency_hist::stdev 41.117345 +system.ruby.LD.latency_hist | 998 88.16% 88.16% | 109 9.63% 97.79% | 13 1.15% 98.94% | 2 0.18% 99.12% | 7 0.62% 99.73% | 3 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -477,21 +477,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 +system.ruby.LD.miss_latency_hist::bucket_size 64 +system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 58.143928 -system.ruby.LD.miss_latency_hist::gmean 52.206801 -system.ruby.LD.miss_latency_hist::stdev 33.349415 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% +system.ruby.LD.miss_latency_hist::mean 58.731634 +system.ruby.LD.miss_latency_hist::gmean 51.741753 +system.ruby.LD.miss_latency_hist::stdev 39.915394 +system.ruby.LD.miss_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 667 system.ruby.ST.latency_hist::bucket_size 32 system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 14.748058 -system.ruby.ST.latency_hist::gmean 5.824702 -system.ruby.ST.latency_hist::stdev 24.783906 -system.ruby.ST.latency_hist | 684 75.92% 75.92% | 183 20.31% 96.23% | 29 3.22% 99.45% | 0 0.00% 99.45% | 2 0.22% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 14.653718 +system.ruby.ST.latency_hist::gmean 5.820052 +system.ruby.ST.latency_hist::stdev 24.674998 +system.ruby.ST.latency_hist | 684 75.92% 75.92% | 188 20.87% 96.78% | 26 2.89% 99.67% | 0 0.00% 99.67% | 0 0.00% 99.67% | 1 0.11% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -503,18 +503,18 @@ system.ruby.ST.hit_latency_hist::total 684 system.ruby.ST.miss_latency_hist::bucket_size 32 system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 51.778802 -system.ruby.ST.miss_latency_hist::gmean 47.157588 -system.ruby.ST.miss_latency_hist::stdev 27.288529 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 51.387097 +system.ruby.ST.miss_latency_hist::gmean 47.001474 +system.ruby.ST.miss_latency_hist::stdev 27.408897 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% system.ruby.ST.miss_latency_hist::total 217 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::bucket_size 32 +system.ruby.IFETCH.latency_hist::max_bucket 319 system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 9.661156 -system.ruby.IFETCH.latency_hist::gmean 4.110524 -system.ruby.IFETCH.latency_hist::stdev 22.183687 -system.ruby.IFETCH.latency_hist | 5472 97.28% 97.28% | 127 2.26% 99.54% | 18 0.32% 99.86% | 4 0.07% 99.93% | 3 0.05% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.539378 +system.ruby.IFETCH.latency_hist::gmean 4.106431 +system.ruby.IFETCH.latency_hist::stdev 21.247440 +system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 435 7.73% 97.32% | 121 2.15% 99.47% | 5 0.09% 99.56% | 8 0.14% 99.70% | 15 0.27% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -523,21 +523,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 5039 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist::max_bucket 319 system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 66.940273 -system.ruby.IFETCH.miss_latency_hist::gmean 61.663848 -system.ruby.IFETCH.miss_latency_hist::stdev 32.593558 -system.ruby.IFETCH.miss_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 65.771331 +system.ruby.IFETCH.miss_latency_hist::gmean 61.076979 +system.ruby.IFETCH.miss_latency_hist::stdev 28.360902 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.miss_latency_hist::total 586 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 60.710884 -system.ruby.Directory.miss_mach_latency_hist::gmean 54.957755 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.665540 -system.ruby.Directory.miss_mach_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 60.453741 +system.ruby.Directory.miss_mach_latency_hist::gmean 54.500138 +system.ruby.Directory.miss_mach_latency_hist::stdev 34.320124 +system.ruby.Directory.miss_mach_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -565,29 +565,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.143928 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.206801 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.349415 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.731634 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 51.741753 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 39.915394 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.778802 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.157588 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.288529 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.387097 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.001474 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.408897 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.940273 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.663848 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.593558 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.771331 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.076979 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.360902 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 4f23a8939..7140a68cc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30902500 # Number of ticks simulated final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 544856 # Simulator instruction rate (inst/s) -host_op_rate 544118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2985748792 # Simulator tick rate (ticks/s) -host_mem_usage 288768 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 339265 # Simulator instruction rate (inst/s) +host_op_rate 338999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1861147916 # Simulator tick rate (ticks/s) +host_mem_usage 289452 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -108,14 +108,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.152837 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.152837 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021033 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021033 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id @@ -186,14 +186,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4698000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4698000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7398000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7398000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7398000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7398000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -202,24 +202,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 129.096971 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 129.096971 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063036 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063036 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -276,97 +276,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 295 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15846500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15846500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15846500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15846500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15846500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15846500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53716.949153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53716.949153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 183.690355 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.238740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.451615 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005606 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3886 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3886 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 293 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 380 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 293 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 293 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15383000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 15383000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4567500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4567500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 432 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.994764 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993220 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency @@ -381,83 +386,89 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 380 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2125000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2125000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12453000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12453000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3697500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3697500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12453000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5822500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18275500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12453000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5822500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18275500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 432 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 445 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 216000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 380 # Transaction distribution system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index dd15d3497..8f334ebb7 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20101000 # Number of ticks simulated -final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19998000 # Number of ticks simulated +final_tick 19998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29548 # Simulator instruction rate (inst/s) -host_op_rate 29545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 102528509 # Simulator tick rate (ticks/s) -host_mem_usage 221532 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 99740 # Simulator instruction rate (inst/s) +host_op_rate 99716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 344211505 # Simulator tick rate (ticks/s) +host_mem_usage 290580 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1092084971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 321576041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1413661012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1092084971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1092084971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1092084971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 321576041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1413661012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1097709771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 323232323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1420942094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1097709771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1097709771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1097709771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 323232323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1420942094 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19960500 # Total gap between requests +system.physmem.totGap 19858500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -188,31 +188,31 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.606609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.258819 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.430832 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.544877 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.28% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 5.13% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.56% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.85% 88.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 3861750 # Total ticks spent queuing -system.physmem.totMemAccLat 12186750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3950250 # Total ticks spent queuing +system.physmem.totMemAccLat 12275250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8697.64 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8896.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27447.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1413.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27646.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1420.94 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1413.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1420.94 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.04 # Data bus utilization in percentage -system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.10 # Data bus utilization in percentage +system.physmem.busUtilRead 11.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,44 +220,44 @@ system.physmem.readRowHits 357 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44956.08 # Average gap between requests +system.physmem.avgGap 44726.35 # Average gap between requests system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2519400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15068130 # Total energy per rank (pJ) -system.physmem_0.averagePower 951.571203 # Core power per rank (mW) +system.physmem_0.totalEnergy 15077640 # Total energy per rank (pJ) +system.physmem_0.averagePower 952.021468 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15316250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15318750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7470990 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2946000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11827875 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.063003 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6720750 # Time in different power states +system.physmem_1.actBackEnergy 7492365 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2927250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11830500 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.228802 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6597250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 10486250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10517250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2330 # Number of BP lookups -system.cpu.branchPred.condPredicted 1881 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2331 # Number of BP lookups +system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1929 # Number of BTB lookups -system.cpu.branchPred.BTBHits 660 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups +system.cpu.branchPred.BTBHits 661 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.214619 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -279,178 +279,178 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 40203 # number of cpu cycles simulated +system.cpu.numCycles 39997 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7819 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13492 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2330 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 7837 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13501 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2331 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 4391 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.061192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.469867 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 12836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.051807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.461524 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10352 81.42% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.49% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 216 1.70% 84.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 152 1.20% 85.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 1.94% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 139 1.09% 88.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 253 1.99% 90.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 114 0.90% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1052 8.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10473 81.59% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 190 1.48% 83.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 215 1.67% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 153 1.19% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 248 1.93% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 135 1.05% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.97% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 115 0.90% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1054 8.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.057956 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.335597 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7212 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3139 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1951 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 12836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058279 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.337550 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7233 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1952 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 335 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7370 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 627 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 7391 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 953 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 624 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11201 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 1670 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11195 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9631 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18130 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18104 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1610 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9626 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18124 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18098 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4633 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4628 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 361 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 362 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2015 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued +system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 4591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 3358 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.716140 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.547958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.709022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.537942 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9591 75.44% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 944 7.42% 82.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 633 4.98% 87.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 463 3.64% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 426 3.35% 94.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 301 2.37% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 240 1.89% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 71 0.56% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 45 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9696 75.54% 75.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 959 7.47% 83.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 638 4.97% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 461 3.59% 91.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 440 3.43% 95.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 291 2.27% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 236 1.84% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 68 0.53% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 47 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 4.37% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 122 48.41% 52.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 119 47.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 4.38% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 121 48.21% 52.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5535 60.79% 60.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1910 20.98% 81.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1658 18.21% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5531 60.77% 60.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1910 20.99% 81.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1658 18.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9105 # Type of FU issued -system.cpu.iq.rate 0.226476 # Inst issue rate -system.cpu.iq.fu_busy_cnt 252 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads +system.cpu.iq.FU_type_0::total 9101 # Type of FU issued +system.cpu.iq.rate 0.227542 # Inst issue rate +system.cpu.iq.fu_busy_cnt 251 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027579 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31302 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14945 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8267 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9318 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1054 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed @@ -460,56 +460,56 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 1 # system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 870 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu.iew.iewBlockCycles 869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2015 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 62 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8701 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8700 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3330 # number of memory reference insts executed system.cpu.iew.exec_branches 1363 # Number of branches executed system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.216427 # Inst execution rate -system.cpu.iew.wb_sent 8428 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8298 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4465 # num instructions producing a value -system.cpu.iew.wb_consumers 7078 # num instructions consuming a value +system.cpu.iew.exec_rate 0.217516 # Inst execution rate +system.cpu.iew.wb_sent 8425 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8294 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4459 # num instructions producing a value +system.cpu.iew.wb_consumers 7044 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.206403 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.630828 # average fanout of values written-back +system.cpu.iew.wb_rate 0.207366 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.633021 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12003 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.482546 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.346027 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12125 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.477691 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.335541 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9841 81.99% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 848 7.06% 89.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 522 4.35% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 225 1.87% 95.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.40% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 120 1.00% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 110 0.92% 98.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 59 0.49% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 110 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9949 82.05% 82.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 859 7.08% 89.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 524 4.32% 93.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 226 1.86% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.50% 96.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.89% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 109 0.90% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 59 0.49% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 109 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12003 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12125 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,60 +555,60 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22278 # The number of ROB reads +system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22401 # The number of ROB reads system.cpu.rob.rob_writes 21482 # The number of ROB writes system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27161 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144069 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144069 # IPC: Total IPC of All Threads +system.cpu.cpi 6.905559 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.905559 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144811 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144811 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13740 # number of integer regfile reads -system.cpu.int_regfile_writes 7173 # number of integer regfile writes +system.cpu.int_regfile_writes 7170 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.843132 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.810933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2272 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.313725 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.274510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.843132 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015587 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.810933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015579 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015579 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1556 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1556 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 720 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 720 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits -system.cpu.dcache.overall_hits::total 2276 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 326 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 326 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8814500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8814500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30924496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30924496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39738996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39738996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39738996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39738996 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 1553 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1553 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2272 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2272 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2272 # number of overall hits +system.cpu.dcache.overall_hits::total 2272 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 441 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 441 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 441 # number of overall misses +system.cpu.dcache.overall_misses::total 441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32490996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32490996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41268496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41268496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41268496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41268496 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -617,38 +617,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2713 # system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066587 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066587 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.311663 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.311663 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.161076 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.161076 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.161076 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.161076 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 90935.917620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 90935.917620 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068386 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.068386 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.162551 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162551 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.162551 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.162551 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76995.614035 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76995.614035 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99360.844037 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 99360.844037 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 93579.356009 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 93579.356009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 93579.356009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 93579.356009 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 627 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 335 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 335 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4529750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4529750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4417498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4417498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947248 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8947248 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8947248 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8947248 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4551498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4551498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9103498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9103498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9103498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9103498 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -673,27 +673,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82763.636364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82763.636364 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96840.382979 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96840.382979 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89249.980392 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89249.980392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89249.980392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89249.980392 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.362964 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.178952 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.362964 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082697 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082697 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.178952 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082607 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082607 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses system.cpu.icache.tags.data_accesses 4005 # Number of data accesses @@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 439 # n system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses system.cpu.icache.overall_misses::total 439 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31975250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31975250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31975250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31975250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31975250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31975250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31700000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31700000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31700000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31700000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31700000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31700000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses @@ -727,17 +727,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72836.560364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72836.560364 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72209.567198 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72209.567198 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72209.567198 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72209.567198 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72209.567198 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72209.567198 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 97.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -753,106 +753,112 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350 system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26127750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26127750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26127750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26127750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26127750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26127750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26208500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26208500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26208500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26208500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26208500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26208500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74881.428571 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74881.428571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74881.428571 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74881.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74881.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74881.428571 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.954316 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.713481 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.205981 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.748335 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006102 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.994608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.718873 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000968 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006095 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 7 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 344 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 344 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 54 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 54 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 445 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25715250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4463750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30179000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4367500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4367500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25715250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8831250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34546500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25715250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8831250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34546500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4478000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4478000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4458500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4458500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8936500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25621500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8936500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34558000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.982716 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.982857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981818 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981818 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95276.595745 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95276.595745 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74481.104651 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74481.104651 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82564.814815 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82564.814815 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77658.426966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77658.426966 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -861,55 +867,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 54 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 54 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21441250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25233500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3785500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3785500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21441250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7577750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29019000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21441250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7577750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29019000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4008000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4008000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22191500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22191500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22191500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7926500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30118000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22191500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7926500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30118000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981818 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85276.595745 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85276.595745 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64510.174419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64510.174419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72564.814815 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72564.814815 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) @@ -930,14 +941,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 589250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 165750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) @@ -953,9 +964,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 550500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2341000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2342500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 51b100b5f..3da0fac46 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000096 # Number of seconds simulated -sim_ticks 95989 # Number of ticks simulated -final_tick 95989 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000095 # Number of seconds simulated +sim_ticks 95241 # Number of ticks simulated +final_tick 95241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 73101 # Simulator instruction rate (inst/s) -host_op_rate 73087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1316740 # Simulator tick rate (ticks/s) -host_mem_usage 448980 # Number of bytes of host memory used +host_inst_rate 71470 # Simulator instruction rate (inst/s) +host_op_rate 71456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1277340 # Simulator tick rate (ticks/s) +host_mem_usage 449880 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 859431810 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 859431810 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 856764838 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 856764838 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716196648 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1716196648 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 866181581 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 866181581 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 863493663 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 863493663 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1729675245 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1729675245 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1289 # Number of read requests accepted system.mem_ctrls.writeReqs 1285 # Number of write requests accepted system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 44736 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 37760 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 45312 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 43328 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 39168 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 43904 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 590 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 557 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 612 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 580 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 16 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 111 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 113 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 123 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 59 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 34 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 59 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 63 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 15 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 11 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 16 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 111 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 120 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 148 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 37 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 12 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 59 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 58 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 113 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 127 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 35 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 56 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 14 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 9 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 95925 # Total gap between requests +system.mem_ctrls.totGap 95177 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 699 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 677 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 36 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 47 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 42 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -184,92 +184,92 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 230 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 387.339130 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 262.668395 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 318.441590 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 45 19.57% 19.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 22.17% 41.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 39 16.96% 58.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 22 9.57% 68.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 23 10.00% 78.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 2.17% 80.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 5.22% 85.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 9 3.91% 89.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 24 10.43% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 230 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 43 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.186047 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.978763 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.231215 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 22 51.16% 51.16% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 14 32.56% 83.72% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 5 11.63% 95.35% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.33% 97.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.33% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 43 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 43 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.465116 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.435760 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.031615 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 35 81.40% 81.40% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8743 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22024 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 241 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 353.991701 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 236.521382 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 306.711183 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 49 20.33% 20.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 67 27.80% 48.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 30 12.45% 60.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 30 12.45% 73.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 18 7.47% 80.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 2.90% 83.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 3.73% 87.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 14 5.81% 92.95% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 17 7.05% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 241 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 42 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.047619 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.828866 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.297837 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 2.38% 2.38% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 18 42.86% 45.24% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 17 40.48% 85.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 11.90% 97.62% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 2.38% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 42 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 42 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.313589 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.845841 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 35 83.33% 83.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 3 7.14% 90.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1 2.38% 92.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 7.14% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 42 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 8633 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 21496 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3385 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 12.75 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 466.05 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 472.05 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 859.43 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 856.76 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.75 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 454.93 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 460.98 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 866.18 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 863.49 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.69 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 7.16 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.55 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.60 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.98 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.53 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 496 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 676 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 70.96 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 37.27 # Average gap between requests -system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 4271616 # Energy for write commands per rank (pJ) +system.mem_ctrls.writeRowHits 621 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 73.26 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 36.98 # Average gap between requests +system.mem_ctrls.pageHitRate 80.82 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1141560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 634200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5079360 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4178304 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 59194044 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 4292400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 80701020 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 861.316185 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 6799 # Time in different power states +system.mem_ctrls_0.actBackEnergy 60945084 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 2754600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 80835828 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 862.782607 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 4199 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 83841 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 86387 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 672840 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 373800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 3257280 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2716416 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 680400 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 378000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 3194880 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2768256 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 56250108 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 6873000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 76246164 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 813.795884 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 11133 # Time in different power states +system.mem_ctrls_1.actBackEnergy 57004560 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 6211200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 76340016 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 814.797592 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 10140 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 79453 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 80556 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 95989 # number of cpu cycles simulated +system.cpu.numCycles 95241 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -288,7 +288,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.999990 # Number of idle cycles -system.cpu.num_busy_cycles 95988.000010 # Number of busy cycles +system.cpu.num_busy_cycles 95240.000010 # Number of busy cycles system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000010 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -343,10 +343,10 @@ system.ruby.outstanding_req_hist::total 6759 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 6758 -system.ruby.latency_hist::mean 13.203759 -system.ruby.latency_hist::gmean 5.149407 -system.ruby.latency_hist::stdev 25.345890 -system.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 13.093075 +system.ruby.latency_hist::gmean 5.137326 +system.ruby.latency_hist::stdev 25.295268 +system.ruby.latency_hist | 6551 96.94% 96.94% | 168 2.49% 99.42% | 27 0.40% 99.82% | 4 0.06% 99.88% | 3 0.04% 99.93% | 5 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 6758 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -358,17 +358,17 @@ system.ruby.hit_latency_hist::total 5469 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1289 -system.ruby.miss_latency_hist::mean 56.496509 -system.ruby.miss_latency_hist::gmean 50.965481 -system.ruby.miss_latency_hist::stdev 32.440273 -system.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 55.916214 +system.ruby.miss_latency_hist::gmean 50.341721 +system.ruby.miss_latency_hist::stdev 32.999000 +system.ruby.miss_latency_hist | 1082 83.94% 83.94% | 168 13.03% 96.97% | 27 2.09% 99.07% | 4 0.31% 99.38% | 3 0.23% 99.61% | 5 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1289 system.ruby.Directory.incomplete_times 1288 system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.703893 +system.ruby.network.routers0.percent_links_utilized 6.756544 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 system.ruby.network.routers0.msg_count.Response_Data::4 1289 @@ -377,7 +377,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.percent_links_utilized 6.703893 +system.ruby.network.routers1.percent_links_utilized 6.756544 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 system.ruby.network.routers1.msg_count.Response_Data::4 1289 @@ -386,7 +386,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.percent_links_utilized 6.703893 +system.ruby.network.routers2.percent_links_utilized 6.756544 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 system.ruby.network.routers2.msg_count.Response_Data::4 1289 @@ -403,32 +403,32 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.ruby.network.routers0.throttle0.link_utilization 6.712227 +system.ruby.network.routers0.throttle0.link_utilization 6.764944 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers0.throttle1.link_utilization 6.695559 +system.ruby.network.routers0.throttle1.link_utilization 6.748144 system.ruby.network.routers0.throttle1.msg_count.Control::2 1289 system.ruby.network.routers0.throttle1.msg_count.Data::2 1285 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle0.link_utilization 6.695559 +system.ruby.network.routers1.throttle0.link_utilization 6.748144 system.ruby.network.routers1.throttle0.msg_count.Control::2 1289 system.ruby.network.routers1.throttle0.msg_count.Data::2 1285 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle1.link_utilization 6.712227 +system.ruby.network.routers1.throttle1.link_utilization 6.764944 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle0.link_utilization 6.712227 +system.ruby.network.routers2.throttle0.link_utilization 6.764944 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle1.link_utilization 6.695559 +system.ruby.network.routers2.throttle1.link_utilization 6.748144 system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 @@ -446,10 +446,10 @@ system.ruby.delayVCHist.vnet_2::total 1285 # de system.ruby.LD.latency_hist::bucket_size 32 system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 715 -system.ruby.LD.latency_hist::mean 30.924476 -system.ruby.LD.latency_hist::gmean 13.876278 -system.ruby.LD.latency_hist::stdev 34.776798 -system.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00% +system.ruby.LD.latency_hist::mean 29.991608 +system.ruby.LD.latency_hist::gmean 13.799155 +system.ruby.LD.latency_hist::stdev 30.436552 +system.ruby.LD.latency_hist | 320 44.76% 44.76% | 332 46.43% 91.19% | 50 6.99% 98.18% | 5 0.70% 98.88% | 4 0.56% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 715 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -461,18 +461,18 @@ system.ruby.LD.hit_latency_hist::total 320 system.ruby.LD.miss_latency_hist::bucket_size 32 system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 395 -system.ruby.LD.miss_latency_hist::mean 53.546835 -system.ruby.LD.miss_latency_hist::gmean 47.987716 -system.ruby.LD.miss_latency_hist::stdev 32.331244 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% +system.ruby.LD.miss_latency_hist::mean 51.858228 +system.ruby.LD.miss_latency_hist::gmean 47.506026 +system.ruby.LD.miss_latency_hist::stdev 24.651585 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 332 84.05% 84.05% | 50 12.66% 96.71% | 5 1.27% 97.97% | 4 1.01% 98.99% | 4 1.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 395 -system.ruby.ST.latency_hist::bucket_size 32 -system.ruby.ST.latency_hist::max_bucket 319 +system.ruby.ST.latency_hist::bucket_size 64 +system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 673 -system.ruby.ST.latency_hist::mean 17.843982 -system.ruby.ST.latency_hist::gmean 6.493774 -system.ruby.ST.latency_hist::stdev 27.592771 -system.ruby.ST.latency_hist | 494 73.40% 73.40% | 145 21.55% 94.95% | 28 4.16% 99.11% | 1 0.15% 99.26% | 2 0.30% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 18.735513 +system.ruby.ST.latency_hist::gmean 6.548753 +system.ruby.ST.latency_hist::stdev 31.370836 +system.ruby.ST.latency_hist | 639 94.95% 94.95% | 25 3.71% 98.66% | 8 1.19% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 673 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -481,21 +481,21 @@ system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 494 -system.ruby.ST.miss_latency_hist::bucket_size 32 -system.ruby.ST.miss_latency_hist::max_bucket 319 +system.ruby.ST.miss_latency_hist::bucket_size 64 +system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 179 -system.ruby.ST.miss_latency_hist::mean 58.810056 -system.ruby.ST.miss_latency_hist::gmean 54.709109 -system.ruby.ST.miss_latency_hist::stdev 23.983086 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 62.162011 +system.ruby.ST.miss_latency_hist::gmean 56.471067 +system.ruby.ST.miss_latency_hist::stdev 33.641225 +system.ruby.ST.miss_latency_hist | 145 81.01% 81.01% | 25 13.97% 94.97% | 8 4.47% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 179 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 5370 -system.ruby.IFETCH.latency_hist::mean 10.262756 -system.ruby.IFETCH.latency_hist::gmean 4.383388 -system.ruby.IFETCH.latency_hist::stdev 22.342607 -system.ruby.IFETCH.latency_hist | 5246 97.69% 97.69% | 101 1.88% 99.57% | 16 0.30% 99.87% | 1 0.02% 99.89% | 5 0.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 10.135940 +system.ruby.IFETCH.latency_hist::gmean 4.369076 +system.ruby.IFETCH.latency_hist::stdev 22.541685 +system.ruby.IFETCH.latency_hist | 5260 97.95% 97.95% | 88 1.64% 99.59% | 11 0.20% 99.80% | 4 0.07% 99.87% | 3 0.06% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 5370 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -507,18 +507,18 @@ system.ruby.IFETCH.hit_latency_hist::total 4655 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 715 -system.ruby.IFETCH.miss_latency_hist::mean 57.546853 -system.ruby.IFETCH.miss_latency_hist::gmean 51.762329 -system.ruby.IFETCH.miss_latency_hist::stdev 34.218674 -system.ruby.IFETCH.miss_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 56.594406 +system.ruby.IFETCH.miss_latency_hist::gmean 50.506398 +system.ruby.IFETCH.miss_latency_hist::stdev 36.435131 +system.ruby.IFETCH.miss_latency_hist | 605 84.62% 84.62% | 88 12.31% 96.92% | 11 1.54% 98.46% | 4 0.56% 99.02% | 3 0.42% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 715 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1289 -system.ruby.Directory.miss_mach_latency_hist::mean 56.496509 -system.ruby.Directory.miss_mach_latency_hist::gmean 50.965481 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.440273 -system.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 55.916214 +system.ruby.Directory.miss_mach_latency_hist::gmean 50.341721 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.999000 +system.ruby.Directory.miss_mach_latency_hist | 1082 83.94% 83.94% | 168 13.03% 96.97% | 27 2.09% 99.07% | 4 0.31% 99.38% | 3 0.23% 99.61% | 5 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1289 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -549,26 +549,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.546835 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.987716 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.331244 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.858228 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.506026 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 24.651585 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 332 84.05% 84.05% | 50 12.66% 96.71% | 5 1.27% 97.97% | 4 1.01% 98.99% | 4 1.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 58.810056 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 54.709109 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 23.983086 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 62.162011 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 56.471067 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.641225 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 145 81.01% 81.01% | 25 13.97% 94.97% | 8 4.47% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 179 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.546853 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.594406 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.506398 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 36.435131 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 605 84.62% 84.62% | 88 12.31% 96.92% | 11 1.54% 98.46% | 4 0.56% 99.02% | 3 0.42% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index f6a7e842c..fd8319ed7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 27800500 # Number of ticks simulated final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 510787 # Simulator instruction rate (inst/s) -host_op_rate 510102 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2658808340 # Simulator tick rate (ticks/s) -host_mem_usage 289420 # Number of bytes of host memory used +host_inst_rate 428112 # Simulator instruction rate (inst/s) +host_op_rate 427631 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2229390537 # Simulator tick rate (ticks/s) +host_mem_usage 290104 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id @@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -184,24 +184,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -258,100 +258,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 255 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 255 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13388000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13388000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 257 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 54 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 54 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992218 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency @@ -366,55 +372,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10838000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10838000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10838000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16533000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10838000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16533000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) @@ -439,10 +450,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 385500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 308 # Transaction distribution system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 66fb99cb1..ef02c087f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21143500 # Number of ticks simulated -final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21012000 # Number of ticks simulated +final_tick 21012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30354 # Simulator instruction rate (inst/s) -host_op_rate 54988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119268705 # Simulator tick rate (ticks/s) -host_mem_usage 303472 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 49067 # Simulator instruction rate (inst/s) +host_op_rate 88883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191585973 # Simulator tick rate (ticks/s) +host_mem_usage 310932 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 832407123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 426797834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1259204957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 832407123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 832407123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 832407123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 426797834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1259204957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 837616600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 429468875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1267085475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 837616600 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 837616600 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 837616600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 429468875 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1267085475 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21095000 # Total gap between requests +system.physmem.totGap 20963500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,137 +186,137 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.440000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.807528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.488436 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 35 35.00% 35.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 31 31.00% 66.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.00% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.00% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.00% 95.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.00% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100 # Bytes accessed per row activation -system.physmem.totQLat 5105750 # Total ticks spent queuing -system.physmem.totMemAccLat 12924500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 99 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 239.838384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 160.844462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 248.938264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 34 34.34% 34.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32 32.32% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15 15.15% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 5.05% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.02% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 4.04% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.01% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.02% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 99 # Bytes accessed per row activation +system.physmem.totQLat 3956500 # Total ticks spent queuing +system.physmem.totMemAccLat 11775250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12244.00 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9488.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30994.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1262.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28238.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1270.13 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1262.23 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1270.13 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.86 # Data bus utilization in percentage -system.physmem.busUtilRead 9.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.92 # Data bus utilization in percentage +system.physmem.busUtilRead 9.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 307 # Number of row buffer hits during reads +system.physmem.readRowHits 308 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 50587.53 # Average gap between requests -system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 936000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 50272.18 # Average gap between requests +system.physmem.pageHitRate 73.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 189000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 951600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13058475 # Total energy per rank (pJ) -system.physmem_0.averagePower 824.789199 # Core power per rank (mW) +system.physmem_0.totalEnergy 13085760 # Total energy per rank (pJ) +system.physmem_0.averagePower 826.512553 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 438480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 239250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1513200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14021205 # Total energy per rank (pJ) -system.physmem_1.averagePower 885.596400 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 102500 # Time in different power states +system.physmem_1.actBackEnergy 10315575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 450750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13970490 # Total energy per rank (pJ) +system.physmem_1.averagePower 882.393179 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 973750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15223750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14667250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 3414 # Number of BP lookups -system.cpu.branchPred.condPredicted 3414 # Number of conditional branches predicted +system.cpu.branchPred.lookups 3416 # Number of BP lookups +system.cpu.branchPred.condPredicted 3416 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2533 # Number of BTB lookups -system.cpu.branchPred.BTBHits 863 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2538 # Number of BTB lookups +system.cpu.branchPred.BTBHits 864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.070272 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.042553 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 42288 # number of cpu cycles simulated +system.cpu.numCycles 42025 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12201 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15496 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3414 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1201 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1161 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 11194 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3416 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9646 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1195 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1127 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 2164 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 23748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.168519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.673732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2165 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 22628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.226003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.725670 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19483 82.04% 82.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 236 0.99% 83.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 173 0.73% 83.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 257 1.08% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 208 0.88% 85.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 228 0.96% 86.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 337 1.42% 88.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 205 0.86% 88.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2621 11.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18363 81.15% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 236 1.04% 82.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 174 0.77% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 258 1.14% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 208 0.92% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 227 1.00% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 337 1.49% 87.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 205 0.91% 88.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2620 11.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 23748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080732 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.366440 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7408 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3332 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 22628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.081285 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.368590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 10919 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7328 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3329 # Number of cycles decode is running system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 600 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25703 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 600 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12221 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2293 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 795 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3474 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4365 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24179 # Number of instructions processed by rename +system.cpu.decode.SquashCycles 597 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25699 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2276 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 782 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3470 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4314 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24173 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4214 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27545 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 59275 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 33508 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 4163 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 27542 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 59265 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 33505 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16482 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16479 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer @@ -324,109 +324,109 @@ system.cpu.memDep0.insertedLoads 2438 # Nu system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21419 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21416 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17882 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11697 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17876 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11694 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16519 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 23748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.752990 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.715169 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 22628 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.789995 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.748596 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18623 78.42% 78.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1142 4.81% 83.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 888 3.74% 86.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 640 2.69% 89.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 832 3.50% 93.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 584 2.46% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 601 2.53% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 314 1.32% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124 0.52% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17504 77.36% 77.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1142 5.05% 82.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 3.94% 86.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 637 2.82% 89.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 831 3.67% 92.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 584 2.58% 95.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 600 2.65% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 315 1.39% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124 0.55% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 23748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 22628 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 173 77.58% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 13.90% 91.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 8.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14368 80.35% 80.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2121 11.86% 92.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14362 80.34% 80.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2121 11.87% 92.29% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17882 # Type of FU issued -system.cpu.iq.rate 0.422862 # Inst issue rate -system.cpu.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 59806 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33148 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17876 # Type of FU issued +system.cpu.iq.rate 0.425366 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012531 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 58676 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33142 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16350 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18098 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18093 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -439,57 +439,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 600 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1925 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 68 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21444 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1916 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21441 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 58 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 694 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16910 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1967 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 972 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 565 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16903 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1966 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 973 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3249 # number of memory reference insts executed -system.cpu.iew.exec_branches 1660 # Number of branches executed +system.cpu.iew.exec_refs 3248 # number of memory reference insts executed +system.cpu.iew.exec_branches 1659 # Number of branches executed system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.399877 # Inst execution rate -system.cpu.iew.wb_sent 16617 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16357 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10994 # num instructions producing a value -system.cpu.iew.wb_consumers 17115 # num instructions consuming a value +system.cpu.iew.exec_rate 0.402213 # Inst execution rate +system.cpu.iew.wb_sent 16611 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16354 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10992 # num instructions producing a value +system.cpu.iew.wb_consumers 17112 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.386800 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642361 # average fanout of values written-back +system.cpu.iew.wb_rate 0.389149 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642356 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11696 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11693 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 587 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 21784 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.447438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.339216 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 584 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.471621 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.370778 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18538 85.10% 85.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1010 4.64% 89.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 544 2.50% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 738 3.39% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 369 1.69% 97.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 141 0.65% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.52% 98.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.33% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 259 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17422 84.30% 84.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1008 4.88% 89.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 544 2.63% 91.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 740 3.58% 95.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 368 1.78% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.68% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.55% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.35% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 259 1.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 21784 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20667 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,100 +536,100 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 42968 # The number of ROB reads -system.cpu.rob.rob_writes 44876 # The number of ROB writes +system.cpu.rob.rob_reads 41848 # The number of ROB reads +system.cpu.rob.rob_writes 44866 # The number of ROB writes system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18540 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19397 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127223 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127223 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21328 # number of integer regfile reads -system.cpu.int_regfile_writes 13105 # number of integer regfile writes +system.cpu.cpi 7.811338 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.811338 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128019 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128019 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21318 # number of integer regfile reads +system.cpu.int_regfile_writes 13103 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8064 # number of cc regfile reads +system.cpu.cc_regfile_reads 8054 # number of cc regfile reads system.cpu.cc_regfile_writes 5036 # number of cc regfile writes -system.cpu.misc_regfile_reads 7485 # number of misc regfile reads +system.cpu.misc_regfile_reads 7483 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.313704 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 82.324603 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.971631 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.950355 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.313704 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020096 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.324603 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020099 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020099 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5351 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5351 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1536 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1536 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5349 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5349 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1533 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1533 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits -system.cpu.dcache.overall_hits::total 2393 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 134 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 134 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2390 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2390 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2390 # number of overall hits +system.cpu.dcache.overall_hits::total 2390 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 212 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 212 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 212 # number of overall misses -system.cpu.dcache.overall_misses::total 212 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11119000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11119000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6761250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6761250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17880250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17880250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17880250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17880250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1670 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses +system.cpu.dcache.overall_misses::total 214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10515500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10515500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6241000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6241000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16756500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16756500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16756500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16756500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1669 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1669 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2605 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2605 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2605 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2605 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080240 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080240 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2604 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081486 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081382 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081382 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081382 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081382 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82977.611940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 82977.611940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86682.692308 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 86682.692308 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84340.801887 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84340.801887 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.082181 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082181 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082181 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082181 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77319.852941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77319.852941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80012.820513 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80012.820513 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 78301.401869 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78301.401869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 78301.401869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78301.401869 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 70 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 70 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 70 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses @@ -638,82 +638,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5695500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5695500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6612750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6612750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12308250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12308250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12308250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12308250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038323 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038323 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5436500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5436500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11599500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11599500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038346 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038346 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88992.187500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88992.187500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84778.846154 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84778.846154 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054531 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054531 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054531 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054531 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84945.312500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84945.312500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79012.820513 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79012.820513 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81686.619718 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81686.619718 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81686.619718 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81686.619718 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.513084 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1796 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 131.388880 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1795 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.507246 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.503623 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.513084 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064215 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064215 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 131.388880 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064155 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064155 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4604 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4604 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1796 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1796 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1796 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1796 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1796 # number of overall hits -system.cpu.icache.overall_hits::total 1796 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28645750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28645750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28645750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28645750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28645750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28645750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2164 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2164 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2164 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2164 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170055 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.170055 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.170055 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.170055 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.170055 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.170055 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77841.711957 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77841.711957 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77841.711957 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77841.711957 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4606 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4606 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1795 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1795 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1795 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1795 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1795 # number of overall hits +system.cpu.icache.overall_hits::total 1795 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 370 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 370 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 370 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 370 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 370 # number of overall misses +system.cpu.icache.overall_misses::total 370 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27513500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27513500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27513500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27513500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27513500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27513500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2165 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2165 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2165 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2165 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170901 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.170901 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.170901 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.170901 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.170901 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.170901 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74360.810811 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74360.810811 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74360.810811 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74360.810811 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74360.810811 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74360.810811 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -722,115 +722,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 276 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21933250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21933250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21933250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21933250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21933250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21933250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127542 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.127542 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.127542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79468.297101 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79468.297101 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21617000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21617000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127483 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127483 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127483 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.127483 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127483 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.127483 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78322.463768 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78322.463768 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78322.463768 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78322.463768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78322.463768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78322.463768 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.168393 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 162.995820 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.574096 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.594298 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000964 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.424574 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.571246 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004974 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 339 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 78 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 78 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21646250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5632500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27278750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6534750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6534750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21646250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12167250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33813500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21646250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12167250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33813500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6046000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6046000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5342000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5342000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32580000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32580000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 78 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 78 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 276 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 276 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 276 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 276 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996377 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997059 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996377 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996377 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996377 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78713.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88007.812500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80468.289086 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83778.846154 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83778.846154 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81087.529976 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81087.529976 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77512.820513 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77512.820513 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77061.818182 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77061.818182 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83468.750000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83468.750000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77061.818182 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80197.183099 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78129.496403 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77061.818182 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80197.183099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78129.496403 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,55 +844,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 78 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 78 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18201750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4837000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23038750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18201750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10392250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28594000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18201750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10392250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28594000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5266000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5266000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18442000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18442000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18442000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9978000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18442000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9978000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28420000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996377 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66188.181818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75578.125000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67960.914454 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71221.153846 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71221.153846 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67512.820513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67512.820513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67061.818182 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67061.818182 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73625 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73625 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67061.818182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70267.605634 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68153.477218 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67061.818182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70267.605634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68153.477218 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 276 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) @@ -908,14 +918,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 471250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 339 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 414000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution system.membus.trans_dist::ReadExResp 78 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 339 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) @@ -933,9 +943,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2222500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 6ad7b9146..478e12e63 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000107 # Number of seconds simulated -sim_ticks 107237 # Number of ticks simulated -final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107256 # Number of ticks simulated +final_tick 107256 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 59170 # Simulator instruction rate (inst/s) -host_op_rate 107175 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1178869 # Simulator tick rate (ticks/s) -host_mem_usage 466480 # Number of bytes of host memory used +host_inst_rate 57113 # Simulator instruction rate (inst/s) +host_op_rate 103447 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1138055 # Simulator tick rate (ticks/s) +host_mem_usage 467864 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 821805907 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 821805907 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 819418671 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 819418671 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1641224577 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1641224577 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 821660327 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 821660327 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 819273514 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 819273514 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1640933841 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1640933841 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1377 # Number of read requests accepted system.mem_ctrls.writeReqs 1373 # Number of write requests accepted system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 42624 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 45504 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 42752 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 43264 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 44864 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 43264 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 711 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 686 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 674 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 56 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 42 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 27 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 134 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 126 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 22 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 29 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 124 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 21 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 7 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 31 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 50 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 10 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 55 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 133 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 54 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 54 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 41 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 30 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 129 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 129 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 21 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 30 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 33 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 36 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 32 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 107133 # Total gap between requests +system.mem_ctrls.totGap 107152 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 666 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 676 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,14 +135,14 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see @@ -184,92 +184,93 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 272 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 306.823529 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 199.088320 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 295.785748 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 71 26.10% 26.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 86 31.62% 57.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 34 12.50% 70.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 20 7.35% 77.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 17 6.25% 83.82% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 3.31% 87.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 11 4.04% 91.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.10% 92.28% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 21 7.72% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 272 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 276 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 306.782609 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 194.488181 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 303.473845 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 80 28.99% 28.99% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 80 28.99% 57.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 33 11.96% 69.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 22 7.97% 77.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 18 6.52% 84.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 2.54% 86.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7 2.54% 89.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.45% 90.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 25 9.06% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 276 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 41 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.121951 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.902045 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.325621 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 4.88% 4.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 18 43.90% 48.78% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 92.68% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 2 4.88% 97.56% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.243902 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.023325 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.314970 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 2.44% 2.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 16 39.02% 41.46% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 85.37% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 12.20% 97.56% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 2.44% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 41 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 41 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.292683 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.274345 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.813754 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 36 87.80% 87.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 7.32% 95.12% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 4.88% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.487805 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.459950 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.003044 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 32 78.05% 78.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 2 4.88% 82.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 7.32% 90.24% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 4 9.76% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 41 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 9844 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22498 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3330 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 14.78 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 9573 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 22417 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3380 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 14.16 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 33.78 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 397.47 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 398.67 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 821.81 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 819.42 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 33.16 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 403.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 403.37 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 821.66 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 819.27 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 6.22 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.11 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.11 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 6.30 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.15 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.15 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.04 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 427 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 625 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 64.11 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes +system.mem_ctrls.avgWrQLen 25.88 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 443 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 622 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 65.53 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 88.98 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.96 # Average gap between requests -system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 3219840 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) +system.mem_ctrls.pageHitRate 77.45 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 390600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3319680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2685312 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 57895812 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10101000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 81532956 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 803.454502 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 16443 # Time in different power states +system.mem_ctrls_0.actBackEnergy 57105108 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10794600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 81609660 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 804.210371 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 17627 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 81669 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 80485 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1270080 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 705600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 4605120 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3784320 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1292760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 718200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4630080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3805056 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 62916372 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 5697000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 85589772 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 843.431798 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 9164 # Time in different power states +system.mem_ctrls_1.actBackEnergy 62793936 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5804400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 85655712 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 844.081594 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9408 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 89065 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 88844 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.apic_clk_domain.clock 16 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 107237 # number of cpu cycles simulated +system.cpu.numCycles 107256 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -290,7 +291,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.999991 # Number of idle cycles -system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles +system.cpu.num_busy_cycles 107255.000009 # Number of busy cycles system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000009 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -345,10 +346,10 @@ system.ruby.outstanding_req_hist::total 8852 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8852 -system.ruby.latency_hist::mean 11.114437 -system.ruby.latency_hist::gmean 4.638310 -system.ruby.latency_hist::stdev 22.979355 -system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 11.116584 +system.ruby.latency_hist::gmean 4.640695 +system.ruby.latency_hist::stdev 22.790037 +system.ruby.latency_hist | 8597 97.12% 97.12% | 214 2.42% 99.54% | 29 0.33% 99.86% | 4 0.05% 99.91% | 5 0.06% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8852 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -360,17 +361,17 @@ system.ruby.hit_latency_hist::total 7475 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1377 -system.ruby.miss_latency_hist::mean 55.163399 -system.ruby.miss_latency_hist::gmean 49.389540 -system.ruby.miss_latency_hist::stdev 33.124416 -system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 55.177197 +system.ruby.miss_latency_hist::gmean 49.553011 +system.ruby.miss_latency_hist::stdev 32.253276 +system.ruby.miss_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.411034 +system.ruby.network.routers0.percent_links_utilized 6.409898 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 system.ruby.network.routers0.msg_count.Response_Data::4 1377 @@ -379,7 +380,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers1.percent_links_utilized 6.411034 +system.ruby.network.routers1.percent_links_utilized 6.409898 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 system.ruby.network.routers1.msg_count.Response_Data::4 1377 @@ -388,7 +389,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.percent_links_utilized 6.411034 +system.ruby.network.routers2.percent_links_utilized 6.409898 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 system.ruby.network.routers2.msg_count.Response_Data::4 1377 @@ -405,32 +406,32 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.ruby.network.routers0.throttle0.link_utilization 6.418494 +system.ruby.network.routers0.throttle0.link_utilization 6.417357 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers0.throttle1.link_utilization 6.403573 +system.ruby.network.routers0.throttle1.link_utilization 6.402439 system.ruby.network.routers0.throttle1.msg_count.Control::2 1377 system.ruby.network.routers0.throttle1.msg_count.Data::2 1373 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 -system.ruby.network.routers1.throttle0.link_utilization 6.403573 +system.ruby.network.routers1.throttle0.link_utilization 6.402439 system.ruby.network.routers1.throttle0.msg_count.Control::2 1377 system.ruby.network.routers1.throttle0.msg_count.Data::2 1373 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 -system.ruby.network.routers1.throttle1.link_utilization 6.418494 +system.ruby.network.routers1.throttle1.link_utilization 6.417357 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.throttle0.link_utilization 6.418494 +system.ruby.network.routers2.throttle0.link_utilization 6.417357 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.throttle1.link_utilization 6.403573 +system.ruby.network.routers2.throttle1.link_utilization 6.402439 system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 @@ -445,13 +446,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1045 -system.ruby.LD.latency_hist::mean 24.819139 -system.ruby.LD.latency_hist::gmean 10.890845 -system.ruby.LD.latency_hist::stdev 28.082269 -system.ruby.LD.latency_hist | 546 52.25% 52.25% | 414 39.62% 91.87% | 77 7.37% 99.23% | 1 0.10% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 24.565550 +system.ruby.LD.latency_hist::gmean 10.818925 +system.ruby.LD.latency_hist::stdev 28.664875 +system.ruby.LD.latency_hist | 965 92.34% 92.34% | 74 7.08% 99.43% | 4 0.38% 99.81% | 1 0.10% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1045 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -460,21 +461,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 546 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 +system.ruby.LD.miss_latency_hist::bucket_size 64 +system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 499 -system.ruby.LD.miss_latency_hist::mean 48.693387 -system.ruby.LD.miss_latency_hist::gmean 44.641812 -system.ruby.LD.miss_latency_hist::stdev 23.667547 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 414 82.97% 82.97% | 77 15.43% 98.40% | 1 0.20% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 48.162325 +system.ruby.LD.miss_latency_hist::gmean 44.026667 +system.ruby.LD.miss_latency_hist::stdev 25.587548 +system.ruby.LD.miss_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 499 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 935 -system.ruby.ST.latency_hist::mean 16.765775 -system.ruby.ST.latency_hist::gmean 6.381495 -system.ruby.ST.latency_hist::stdev 28.609452 -system.ruby.ST.latency_hist | 895 95.72% 95.72% | 35 3.74% 99.47% | 1 0.11% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 16.914439 +system.ruby.ST.latency_hist::gmean 6.394076 +system.ruby.ST.latency_hist::stdev 28.735394 +system.ruby.ST.latency_hist | 895 95.72% 95.72% | 33 3.53% 99.25% | 3 0.32% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 935 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -486,18 +487,18 @@ system.ruby.ST.hit_latency_hist::total 681 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 254 -system.ruby.ST.miss_latency_hist::mean 53.673228 -system.ruby.ST.miss_latency_hist::gmean 48.282634 -system.ruby.ST.miss_latency_hist::stdev 33.823763 -system.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 35 13.78% 98.03% | 1 0.39% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 54.220472 +system.ruby.ST.miss_latency_hist::gmean 48.633946 +system.ruby.ST.miss_latency_hist::stdev 33.614512 +system.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 254 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6864 -system.ruby.IFETCH.latency_hist::mean 8.263112 -system.ruby.IFETCH.latency_hist::gmean 3.900453 -system.ruby.IFETCH.latency_hist::stdev 20.209679 -system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 8.284237 +system.ruby.IFETCH.latency_hist::gmean 3.905930 +system.ruby.IFETCH.latency_hist::stdev 19.803554 +system.ruby.IFETCH.latency_hist | 6729 98.03% 98.03% | 107 1.56% 99.59% | 22 0.32% 99.91% | 1 0.01% 99.93% | 4 0.06% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6864 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -509,10 +510,10 @@ system.ruby.IFETCH.hit_latency_hist::total 6241 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 623 -system.ruby.IFETCH.miss_latency_hist::mean 60.987159 -system.ruby.IFETCH.miss_latency_hist::gmean 54.083593 -system.ruby.IFETCH.miss_latency_hist::stdev 38.003932 -system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 61.219904 +system.ruby.IFETCH.miss_latency_hist::gmean 54.926300 +system.ruby.IFETCH.miss_latency_hist::stdev 35.218812 +system.ruby.IFETCH.miss_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 623 system.ruby.RMW_Read.latency_hist::bucket_size 4 system.ruby.RMW_Read.latency_hist::max_bucket 39 @@ -540,10 +541,10 @@ system.ruby.RMW_Read.miss_latency_hist::total 1 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1377 -system.ruby.Directory.miss_mach_latency_hist::mean 55.163399 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.389540 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.124416 -system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 55.177197 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.553011 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.253276 +system.ruby.Directory.miss_mach_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1377 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -571,29 +572,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.693387 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.641812 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 23.667547 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 414 82.97% 82.97% | 77 15.43% 98.40% | 1 0.20% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.162325 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.026667 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 25.587548 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 499 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 53.673228 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.282634 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.823763 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 35 13.78% 98.03% | 1 0.39% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 54.220472 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.633946 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.614512 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 254 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083593 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 38.003932 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.219904 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.926300 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.218812 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 5185b356a..ef7ce3c79 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358500 # Number of ticks simulated final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97635 # Simulator instruction rate (inst/s) -host_op_rate 176805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 514168344 # Simulator tick rate (ticks/s) -host_mem_usage 251928 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 304372 # Simulator instruction rate (inst/s) +host_op_rate 550952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1601632215 # Simulator tick rate (ticks/s) +host_mem_usage 308112 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -93,14 +93,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.791087 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.791087 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019724 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019724 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id @@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4226500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4226500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4266000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4266000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7236000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7236000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7236000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7236000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses @@ -187,24 +187,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.540319 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.544338 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.540319 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -261,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12156500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12156500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12156500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12156500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12156500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12156500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12270500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12270500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12270500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12270500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12270500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12270500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53817.982456 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53817.982456 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.006917 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.474338 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.536457 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.470460 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -297,61 +297,66 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14805500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11918000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 11918000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995614 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency @@ -366,55 +371,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3357500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3357500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9648000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9648000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9648000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15343000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9648000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15343000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) @@ -439,10 +449,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 342000 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 282 # Transaction distribution system.membus.trans_dist::ReadResp 282 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index c8bb95af1..95258693a 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,49 +1,49 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25499500 # Number of ticks simulated -final_tick 25499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24760000 # Number of ticks simulated +final_tick 24760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60058 # Simulator instruction rate (inst/s) -host_op_rate 60053 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120151989 # Simulator tick rate (ticks/s) -host_mem_usage 226048 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 82189 # Simulator instruction rate (inst/s) +host_op_rate 82182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 159657472 # Simulator tick rate (ticks/s) +host_mem_usage 295960 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 40576 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 22144 # Number of bytes read from this memory -system.physmem.bytes_read::total 62848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40704 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 636 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 62720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40576 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 634 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 346 # Number of read requests responded to by this memory -system.physmem.num_reads::total 982 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1596266593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 868409184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2464675778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1596266593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1596266593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1596266593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 868409184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2464675778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 982 # Number of read requests accepted +system.physmem.num_reads::total 980 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1638772213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 894345719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2533117932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1638772213 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1638772213 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1638772213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 894345719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2533117932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 980 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 982 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 980 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62848 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62720 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62848 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62720 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 86 # Per bank write bursts -system.physmem.perBankRdBursts::1 152 # Per bank write bursts -system.physmem.perBankRdBursts::2 79 # Per bank write bursts +system.physmem.perBankRdBursts::0 83 # Per bank write bursts +system.physmem.perBankRdBursts::1 155 # Per bank write bursts +system.physmem.perBankRdBursts::2 77 # Per bank write bursts system.physmem.perBankRdBursts::3 59 # Per bank write bursts system.physmem.perBankRdBursts::4 88 # Per bank write bursts system.physmem.perBankRdBursts::5 49 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25359500 # Total gap between requests +system.physmem.totGap 24609000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 982 # Read request sizes (log2) +system.physmem.readPktSize::6 980 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 220 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.836364 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.810990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 284.156672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 81 36.82% 36.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 62 28.18% 65.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 22 10.00% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 14 6.36% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 10 4.55% 85.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 3.18% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 2.73% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 2.73% 94.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 12 5.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 220 # Bytes accessed per row activation -system.physmem.totQLat 12877000 # Total ticks spent queuing -system.physmem.totMemAccLat 31289500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13113.03 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.971564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.051447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 289.757171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60 28.44% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 22 10.43% 71.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 5.69% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14 6.64% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12 5.69% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.42% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8 3.79% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 5.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation +system.physmem.totQLat 12705250 # Total ticks spent queuing +system.physmem.totMemAccLat 31080250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12964.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31863.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2464.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31714.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2533.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2464.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2533.12 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 19.26 # Data bus utilization in percentage -system.physmem.busUtilRead 19.26 # Data bus utilization in percentage for reads +system.physmem.busUtil 19.79 # Data bus utilization in percentage +system.physmem.busUtilRead 19.79 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.43 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 752 # Number of row buffer hits during reads +system.physmem.readRowHits 761 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 25824.34 # Average gap between requests -system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 929880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 507375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4547400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 25111.22 # Average gap between requests +system.physmem.pageHitRate 77.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 861840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 470250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4539600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 23657895 # Total energy per rank (pJ) -system.physmem_0.averagePower 1001.657370 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 688500 # Time in different power states +system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 23543775 # Total energy per rank (pJ) +system.physmem_0.averagePower 996.825615 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 2878200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15503715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 591000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21359100 # Total energy per rank (pJ) -system.physmem_1.averagePower 903.085461 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 888000 # Time in different power states +system.physmem_1.actBackEnergy 15819210 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 295500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21605295 # Total energy per rank (pJ) +system.physmem_1.averagePower 914.703429 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 407500 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21996000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22446250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 7477 # Number of BP lookups -system.cpu.branchPred.condPredicted 4177 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1616 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5400 # Number of BTB lookups -system.cpu.branchPred.BTBHits 850 # Number of BTB hits +system.cpu.branchPred.lookups 7026 # Number of BP lookups +system.cpu.branchPred.condPredicted 3965 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1425 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5143 # Number of BTB lookups +system.cpu.branchPred.BTBHits 872 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 15.740741 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1012 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 16.955085 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1033 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4911 # DTB read hits -system.cpu.dtb.read_misses 100 # DTB read misses +system.cpu.dtb.read_hits 4832 # DTB read hits +system.cpu.dtb.read_misses 93 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 5011 # DTB read accesses -system.cpu.dtb.write_hits 2106 # DTB write hits -system.cpu.dtb.write_misses 69 # DTB write misses +system.cpu.dtb.read_accesses 4925 # DTB read accesses +system.cpu.dtb.write_hits 2065 # DTB write hits +system.cpu.dtb.write_misses 72 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2175 # DTB write accesses -system.cpu.dtb.data_hits 7017 # DTB hits -system.cpu.dtb.data_misses 169 # DTB misses +system.cpu.dtb.write_accesses 2137 # DTB write accesses +system.cpu.dtb.data_hits 6897 # DTB hits +system.cpu.dtb.data_misses 165 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 7186 # DTB accesses -system.cpu.itb.fetch_hits 5467 # ITB hits -system.cpu.itb.fetch_misses 60 # ITB misses +system.cpu.dtb.data_accesses 7062 # DTB accesses +system.cpu.itb.fetch_hits 5266 # ITB hits +system.cpu.itb.fetch_misses 59 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5527 # ITB accesses +system.cpu.itb.fetch_accesses 5325 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 51000 # number of cpu cycles simulated +system.cpu.numCycles 49521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1416 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 41297 # Number of instructions fetch has processed -system.cpu.fetch.Branches 7477 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1862 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10878 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1697 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 471 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5467 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 803 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 27699 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.490920 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.868697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1262 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 39496 # Number of instructions fetch has processed +system.cpu.fetch.Branches 7026 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1905 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 11647 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1505 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 695 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5266 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 809 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.384950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.783550 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20832 75.21% 75.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 522 1.88% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 376 1.36% 78.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 569 2.05% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 524 1.89% 82.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 456 1.65% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 499 1.80% 85.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 422 1.52% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3499 12.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21883 76.73% 76.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 531 1.86% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 405 1.42% 80.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 525 1.84% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 527 1.85% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 419 1.47% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 492 1.73% 86.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 463 1.62% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3273 11.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 27699 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.146608 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.809745 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36892 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11130 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5276 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 643 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1210 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 704 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 509 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33151 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1210 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37566 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5376 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1365 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5257 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4377 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30969 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 361 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 477 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3380 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 23374 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 38597 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 38579 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.141879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.797561 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38016 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11989 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5115 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 629 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1147 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 376 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 32323 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 785 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1147 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38621 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5295 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1200 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5143 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5490 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30197 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 302 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 566 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4493 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 22785 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37650 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37632 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14234 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 57 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2267 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2994 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1466 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2948 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1410 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 7 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13645 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 56 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2153 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2897 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1434 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 31 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1365 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 27629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 22900 # Number of instructions issued +system.cpu.iq.iqInstsAdded 26855 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 22315 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14934 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8231 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 27699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.826745 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.538980 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 14161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.782488 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.503369 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19213 69.36% 69.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2603 9.40% 78.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1960 7.08% 85.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1418 5.12% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1237 4.47% 95.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 696 2.51% 97.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 372 1.34% 99.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 137 0.49% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 63 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20180 70.76% 70.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2624 9.20% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1911 6.70% 86.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1348 4.73% 91.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1241 4.35% 95.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 673 2.36% 98.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 344 1.21% 99.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 144 0.50% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 53 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 27699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28518 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 27 8.23% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 211 64.33% 72.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 90 27.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33 9.65% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 224 65.50% 75.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 85 24.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7493 65.81% 65.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2715 23.85% 89.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1173 10.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7386 65.50% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2741 24.31% 89.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1144 10.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11386 # Type of FU issued +system.cpu.iq.FU_type_0::total 11276 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7630 66.27% 66.28% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.29% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.29% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.31% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2714 23.57% 89.88% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1165 10.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7337 66.46% 66.48% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.49% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.49% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2570 23.28% 89.79% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1127 10.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11514 # Type of FU issued -system.cpu.iq.FU_type::total 22900 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.449020 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 168 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 328 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.006987 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007336 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.014323 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 73887 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 42626 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11039 # Type of FU issued +system.cpu.iq.FU_type::total 22315 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.450617 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 168 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 174 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 342 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.007529 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007797 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.015326 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73550 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 41081 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19615 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 23202 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22631 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1811 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1714 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 601 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 569 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 281 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 75 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 342 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 63 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1765 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 545 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1630 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 500 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 278 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1210 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3002 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 780 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 27815 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2876 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 747 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1147 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2841 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 538 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27054 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 353 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5710 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2799 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 505 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 21491 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2518 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2502 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 5020 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1136 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1278 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 21041 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2537 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2397 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4934 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1274 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 69 # number of nop insts executed -system.cpu.iew.exec_nop::1 67 # number of nop insts executed -system.cpu.iew.exec_nop::total 136 # number of nop insts executed -system.cpu.iew.exec_refs::0 3616 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3607 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 7223 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1734 # Number of branches executed -system.cpu.iew.exec_branches::1 1745 # Number of branches executed -system.cpu.iew.exec_branches::total 3479 # Number of branches executed -system.cpu.iew.exec_stores::0 1098 # Number of stores executed -system.cpu.iew.exec_stores::1 1105 # Number of stores executed -system.cpu.iew.exec_stores::total 2203 # Number of stores executed -system.cpu.iew.exec_rate 0.421392 # Inst execution rate -system.cpu.iew.wb_sent::0 10180 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 10330 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 20510 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9974 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 10135 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 20109 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5251 # num instructions producing a value -system.cpu.iew.wb_producers::1 5302 # num instructions producing a value -system.cpu.iew.wb_producers::total 10553 # num instructions producing a value -system.cpu.iew.wb_consumers::0 7044 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 7008 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 14052 # num instructions consuming a value +system.cpu.iew.exec_nop::0 74 # number of nop insts executed +system.cpu.iew.exec_nop::1 74 # number of nop insts executed +system.cpu.iew.exec_nop::total 148 # number of nop insts executed +system.cpu.iew.exec_refs::0 3628 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3464 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7092 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1676 # Number of branches executed +system.cpu.iew.exec_branches::1 1656 # Number of branches executed +system.cpu.iew.exec_branches::total 3332 # Number of branches executed +system.cpu.iew.exec_stores::0 1091 # Number of stores executed +system.cpu.iew.exec_stores::1 1067 # Number of stores executed +system.cpu.iew.exec_stores::total 2158 # Number of stores executed +system.cpu.iew.exec_rate 0.424890 # Inst execution rate +system.cpu.iew.wb_sent::0 10100 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9901 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 20001 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9896 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9739 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19635 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5244 # num instructions producing a value +system.cpu.iew.wb_producers::1 5132 # num instructions producing a value +system.cpu.iew.wb_producers::total 10376 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6970 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6831 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13801 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.195569 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.198725 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.394294 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.745457 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.756564 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.750996 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.199834 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.196664 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.396498 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.752367 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.751281 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.751830 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 15019 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1130 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 27612 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462770 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.343029 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1068 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28453 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.449091 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.311891 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22639 81.99% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2318 8.39% 90.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1067 3.86% 94.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 382 1.38% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 325 1.18% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 202 0.73% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 208 0.75% 98.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 146 0.53% 98.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 325 1.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23365 82.12% 82.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2421 8.51% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1102 3.87% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 384 1.35% 95.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 323 1.14% 96.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 209 0.73% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 206 0.72% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 116 0.41% 98.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 327 1.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28453 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12778 # Number of instructions committed @@ -707,25 +707,25 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6389 # Class of committed instruction system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 325 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 130940 # The number of ROB reads -system.cpu.rob.rob_writes 58397 # The number of ROB writes -system.cpu.timesIdled 389 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 327 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 131668 # The number of ROB reads +system.cpu.rob.rob_writes 56750 # The number of ROB writes +system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21003 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 8.003766 # CPI: Cycles Per Instruction -system.cpu.cpi::1 8.003766 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.001883 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.124941 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.124941 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.249882 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 26966 # number of integer regfile reads -system.cpu.int_regfile_writes 15368 # number of integer regfile writes +system.cpu.cpi::0 7.771657 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.771657 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.885829 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.128673 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.128673 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257345 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 26413 # number of integer regfile reads +system.cpu.int_regfile_writes 14990 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -733,289 +733,294 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 213.719872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 5036 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 213.559941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4863 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 346 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.554913 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.054913 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 213.719872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052178 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 213.559941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052139 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052139 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.084473 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 12454 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 12454 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 4006 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 4006 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1030 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 5036 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 5036 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 5036 # number of overall hits -system.cpu.dcache.overall_hits::total 5036 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses -system.cpu.dcache.overall_misses::total 1018 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26557000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26557000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 48843926 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 48843926 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75400926 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75400926 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75400926 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75400926 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 4324 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4324 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 12116 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 12116 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3840 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3840 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1023 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1023 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4863 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4863 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4863 # number of overall hits +system.cpu.dcache.overall_hits::total 4863 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 707 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 707 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1022 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1022 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1022 # number of overall misses +system.cpu.dcache.overall_misses::total 1022 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24108500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24108500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 53981926 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 53981926 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 78090426 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 78090426 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 78090426 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 78090426 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4155 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4155 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 6054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 6054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 6054 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 6054 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073543 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.073543 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.168153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.168153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.168153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.168153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83512.578616 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 83512.578616 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69777.037143 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69777.037143 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74067.707269 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74067.707269 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5713 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5885 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5885 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5885 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5885 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075812 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075812 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408671 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.408671 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76534.920635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76534.920635 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76353.502122 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76353.502122 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76409.418787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76409.418787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76409.418787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76409.418787 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6161 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.946154 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.323308 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 556 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 556 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 672 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 672 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 672 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 672 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 114 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 114 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 676 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 676 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 676 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 676 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 346 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18304750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18304750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11840493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11840493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30145243 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30145243 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30145243 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 30145243 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046716 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046716 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057152 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057152 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90617.574257 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90617.574257 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82225.645833 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82225.645833 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17596000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17596000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12625989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12625989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30221989 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30221989 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30221989 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30221989 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058794 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.058794 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058794 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.058794 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87542.288557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87542.288557 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87075.786207 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87075.786207 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87346.789017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87346.789017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87346.789017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87346.789017 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements::0 8 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 8 # number of replacements -system.cpu.icache.tags.tagsinuse 322.759154 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4537 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.111285 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 319.520873 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4318 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 636 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.789308 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 322.759154 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.157597 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.157597 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 630 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 243 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id 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misses -system.cpu.icache.overall_misses::cpu.inst 923 # number of overall misses -system.cpu.icache.overall_misses::total 923 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 70921745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 70921745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 70921745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 70921745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 70921745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 70921745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169048 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.169048 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.169048 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.169048 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.169048 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.169048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76838.293608 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76838.293608 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76838.293608 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76838.293608 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76838.293608 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76838.293608 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3978 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 319.520873 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.156016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.156016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 628 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.306641 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11148 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11148 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4318 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4318 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4318 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4318 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4318 # number of overall hits +system.cpu.icache.overall_hits::total 4318 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 938 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 938 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 938 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 938 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 938 # number of overall misses +system.cpu.icache.overall_misses::total 938 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69872996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69872996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69872996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69872996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69872996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69872996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5256 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5256 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5256 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5256 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.178463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.178463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.178463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.178463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.178463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.178463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74491.466951 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74491.466951 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74491.466951 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74491.466951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74491.466951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74491.466951 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3812 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 87 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 79 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 45.724138 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48.253165 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 285 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 285 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 285 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 285 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 285 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR 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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25468750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 68514000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997619 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 980 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10951500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10951500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44245000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44245000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15275500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15275500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44245000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26227000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 70472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44245000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26227000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 70472000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996855 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997967 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997967 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67681.210692 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77095.297030 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69950.477327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68718.750000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68718.750000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67681.210692 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73609.104046 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69769.857434 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67681.210692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73609.104046 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69769.857434 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75527.586207 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75527.586207 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69787.066246 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69787.066246 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75997.512438 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75997.512438 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69787.066246 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75800.578035 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71910.204082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69787.066246 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75800.578035 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71910.204082 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 144 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 144 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 837 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 201 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1280 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1968 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1972 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 62848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 984 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 990 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 984 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 990 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 984 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 492000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1076750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 574250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 838 # Transaction distribution -system.membus.trans_dist::ReadResp 838 # Transaction distribution -system.membus.trans_dist::ReadExReq 144 # Transaction distribution -system.membus.trans_dist::ReadExResp 144 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 62848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 990 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 954000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 519000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 835 # Transaction distribution +system.membus.trans_dist::ReadExReq 145 # Transaction distribution +system.membus.trans_dist::ReadExResp 145 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 835 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1960 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1960 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62720 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 982 # Request fanout histogram +system.membus.snoop_fanout::samples 980 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 982 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 980 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 982 # Request fanout histogram -system.membus.reqLayer0.occupancy 1219500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 980 # Request fanout histogram +system.membus.reqLayer0.occupancy 1192500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5224000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 5223750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index eba0d2782..85270cbb1 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27482500 # Number of ticks simulated -final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27401500 # Number of ticks simulated +final_tick 27401500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 15220 # Simulator instruction rate (inst/s) -host_op_rate 15220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28973949 # Simulator tick rate (ticks/s) -host_mem_usage 223564 # Number of bytes of host memory used -host_seconds 0.95 # Real time elapsed on the host +host_inst_rate 94035 # Simulator instruction rate (inst/s) +host_op_rate 94027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 178462571 # Simulator tick rate (ticks/s) +host_mem_usage 293360 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22016 # Nu system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory system.physmem.num_reads::total 492 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 801091604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344655690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1145747294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 801091604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 801091604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 801091604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344655690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1145747294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 803459665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 345674507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1149134171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 803459665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 803459665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 803459665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 345674507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1149134171 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 492 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27431000 # Total gap between requests +system.physmem.totGap 27350000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -187,72 +187,71 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.732394 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 270.110571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.824701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 18.31% 18.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 25.35% 43.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 405.633803 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 274.142926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.087748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 16.90% 16.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 26.76% 43.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 9.86% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.41% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 11.27% 77.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation -system.physmem.totQLat 3613750 # Total ticks spent queuing -system.physmem.totMemAccLat 12838750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3217000 # Total ticks spent queuing +system.physmem.totMemAccLat 12442000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7345.02 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6538.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26095.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1145.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25288.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1149.13 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1145.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1149.13 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.95 # Data bus utilization in percentage -system.physmem.busUtilRead 8.95 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.98 # Data bus utilization in percentage +system.physmem.busUtilRead 8.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 55754.07 # Average gap between requests +system.physmem.avgGap 55589.43 # Average gap between requests system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2059200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2067000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15743115 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 361500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20156895 # Total energy per rank (pJ) -system.physmem_0.averagePower 853.427679 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 520250 # Time in different power states +system.physmem_0.actBackEnergy 15796980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 314250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20171310 # Total energy per rank (pJ) +system.physmem_0.averagePower 854.037999 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 440750 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22332250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22411750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15564420 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 518250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19277100 # Total energy per rank (pJ) -system.physmem_1.averagePower 816.177825 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2637000 # Time in different power states +system.physmem_1.actBackEnergy 15639660 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 452250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19286340 # Total energy per rank (pJ) +system.physmem_1.averagePower 816.569039 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2456000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22058500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22168500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 8538 # Number of BP lookups -system.cpu.branchPred.condPredicted 5461 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1059 # Number of conditional branches incorrect +system.cpu.branchPred.lookups 8543 # Number of BP lookups +system.cpu.branchPred.condPredicted 5466 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups system.cpu.branchPred.BTBHits 3053 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. @@ -261,232 +260,232 @@ system.cpu.branchPred.usedRAS 609 # Nu system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54966 # number of cpu cycles simulated +system.cpu.numCycles 54804 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14246 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 40057 # Number of instructions fetch has processed -system.cpu.fetch.Branches 8538 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 14234 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 40091 # Number of instructions fetch has processed +system.cpu.fetch.Branches 8543 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 15957 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 15933 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 6438 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.235488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.378208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 6440 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.238026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.380017 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20898 64.46% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5494 16.95% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 685 2.11% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 505 1.56% 85.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 819 2.53% 87.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 909 2.80% 90.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 334 1.03% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 371 1.14% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2407 7.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20844 64.37% 64.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5506 17.00% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 683 2.11% 83.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 516 1.59% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 807 2.49% 87.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 911 2.81% 90.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 334 1.03% 91.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 372 1.15% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2410 7.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.155332 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.728760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11347 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12433 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 6847 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 640 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 32383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155883 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.731534 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11354 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12386 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 6823 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 665 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30502 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 30509 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11955 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1146 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9859 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 6898 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1409 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27684 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 11949 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1145 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9839 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 6913 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1382 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27687 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1012 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 986 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51692 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 42838 # Number of integer rename lookups +system.cpu.rename.RenameLookups 51693 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 42839 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 767 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3842 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3673 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.serializingInsts 766 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 785 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3795 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2349 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 23661 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9945 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 9951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6530 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.676208 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.425800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.677022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.427893 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24009 74.05% 74.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3087 9.52% 83.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1572 4.85% 88.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1483 4.57% 93.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 954 2.94% 95.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 709 2.19% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 413 1.27% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 155 0.48% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23977 74.04% 74.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3084 9.52% 83.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1575 4.86% 88.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1484 4.58% 93.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 922 2.85% 95.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 733 2.26% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 411 1.27% 99.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 157 0.48% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32422 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32383 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 111 49.33% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 49 21.78% 71.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 65 28.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111 49.55% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 49 21.88% 71.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 28.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16300 74.35% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3501 15.97% 90.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16295 74.32% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3505 15.99% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2124 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 21924 # Type of FU issued -system.cpu.iq.rate 0.398865 # Inst issue rate -system.cpu.iq.fu_busy_cnt 225 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34352 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.400044 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010217 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76509 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 34365 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20239 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22149 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22148 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 901 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1147 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25507 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3673 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions +system.cpu.iew.iewBlockCycles 1144 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2349 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20914 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3347 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20912 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1126 # number of nop insts executed -system.cpu.iew.exec_refs 5371 # number of memory reference insts executed -system.cpu.iew.exec_branches 4427 # Number of branches executed +system.cpu.iew.exec_nop 1127 # number of nop insts executed +system.cpu.iew.exec_refs 5373 # number of memory reference insts executed +system.cpu.iew.exec_branches 4424 # Number of branches executed system.cpu.iew.exec_stores 2024 # Number of stores executed -system.cpu.iew.exec_rate 0.380490 # Inst execution rate -system.cpu.iew.wb_sent 20501 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 20244 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9848 # num instructions producing a value -system.cpu.iew.wb_consumers 12670 # num instructions consuming a value +system.cpu.iew.exec_rate 0.381578 # Inst execution rate +system.cpu.iew.wb_sent 20497 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 20239 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9852 # num instructions producing a value +system.cpu.iew.wb_consumers 12795 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.368300 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.777269 # average fanout of values written-back +system.cpu.iew.wb_rate 0.369298 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.769988 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10287 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10294 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1059 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30361 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.499391 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.308685 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.500066 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312560 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23816 78.44% 78.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3429 11.29% 89.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1193 3.93% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 637 2.10% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 331 1.09% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 224 0.74% 97.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 397 1.31% 98.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 272 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23779 78.43% 78.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3460 11.41% 89.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1176 3.88% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 592 1.95% 95.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 324 1.07% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 261 0.86% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 394 1.30% 98.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 63 0.21% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 271 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30361 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30320 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -532,36 +531,36 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 54715 # The number of ROB reads -system.cpu.rob.rob_writes 52974 # The number of ROB writes +system.cpu.commit.bw_lim_events 271 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 54682 # The number of ROB reads +system.cpu.rob.rob_writes 52990 # The number of ROB writes system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 22421 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads -system.cpu.ipc 0.262635 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.262635 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 33408 # number of integer regfile reads -system.cpu.int_regfile_writes 18606 # number of integer regfile writes -system.cpu.misc_regfile_reads 7133 # number of misc regfile reads +system.cpu.cpi 3.796342 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.796342 # CPI: Total CPI of All Threads +system.cpu.ipc 0.263411 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.263411 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 33404 # number of integer regfile reads +system.cpu.int_regfile_writes 18604 # number of integer regfile writes +system.cpu.misc_regfile_reads 7136 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.556611 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.713941 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4125 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 28.061224 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.556611 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024062 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024062 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.713941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024100 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9489 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9489 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 3086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -572,64 +571,64 @@ system.cpu.dcache.demand_hits::cpu.data 4119 # nu system.cpu.dcache.demand_hits::total 4119 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 4119 # number of overall hits system.cpu.dcache.overall_hits::total 4119 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 137 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 137 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 138 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 138 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 546 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 546 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 546 # number of overall misses -system.cpu.dcache.overall_misses::total 546 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9397000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27538481 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27538481 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36935481 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36935481 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36935481 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36935481 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3223 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 547 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 547 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 547 # number of overall misses +system.cpu.dcache.overall_misses::total 547 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9332000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9332000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27213977 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27213977 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36545977 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36545977 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36545977 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36545977 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4665 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4665 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4665 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4665 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042507 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.042507 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042804 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042804 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117042 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117042 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117042 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67647.401099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67647.401099 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1052 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.117231 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117231 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117231 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117231 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67623.188406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67623.188406 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66537.841076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66537.841076 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66811.658135 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66811.658135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66811.658135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66811.658135 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1080 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.538462 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 73 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 398 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 398 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 398 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 399 # number of demand (read+write) MSHR hits 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ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6389250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6389250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11532500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11532500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11532500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11532500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020168 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5162500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5162500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6419500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6419500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11582000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11582000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11582000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11582000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 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overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79423.076923 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79423.076923 # average ReadReq mshr miss latency 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average of tags in use +system.cpu.icache.tags.total_refs 5908 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.063584 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.075145 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 190.975563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.093250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.093250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 191.519539 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093515 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093515 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13222 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13222 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5904 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5904 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5904 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5904 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5904 # number of overall hits -system.cpu.icache.overall_hits::total 5904 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 534 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 534 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 534 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 534 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 534 # number of overall misses -system.cpu.icache.overall_misses::total 534 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37367000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37367000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37367000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37367000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37367000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37367000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6438 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6438 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6438 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6438 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6438 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6438 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082945 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082945 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082945 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082945 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082945 # miss rate for overall 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ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 36225500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 36225500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 36225500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 36225500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6440 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6440 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6440 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6440 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082609 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082609 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082609 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082609 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082609 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68093.045113 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68093.045113 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68093.045113 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68093.045113 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68093.045113 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68093.045113 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 188 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 188 # number of ReadReq MSHR hits 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misses system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26526250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26526250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26526250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26526250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26526250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26526250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053743 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.053743 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.053743 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76665.462428 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76665.462428 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26213500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26213500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26213500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26213500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26213500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26213500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053727 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053727 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053727 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.053727 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053727 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.053727 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75761.560694 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75761.560694 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75761.560694 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75761.560694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75761.560694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75761.560694 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 224.896195 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 225.494304 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 190.368376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.527819 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005810 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006863 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 190.884921 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.609384 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001056 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006882 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 344 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 344 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 492 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26158750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5078750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31237500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6304750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6304750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 26158750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11383500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 37542250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 26158750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11383500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 37542250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6293500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6293500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25673000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25673000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5066000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5066000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25673000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11359500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37032500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25673000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11359500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37032500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 346 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 346 # number of ReadCleanReq accesses(hits+misses) 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accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994220 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994220 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76042.877907 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78134.615385 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76375.305623 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75960.843373 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75960.843373 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76305.386179 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76305.386179 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75825.301205 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75825.301205 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74630.813953 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74630.813953 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77938.461538 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77938.461538 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74630.813953 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76753.378378 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75269.308943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74630.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76753.378378 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75269.308943 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,55 +843,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4272750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26134000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5278250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5278250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21861250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31412250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21861250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31412250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5463500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5463500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22233000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22233000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4426000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4426000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22233000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9889500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32122500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22233000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9889500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32122500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994220 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65825.301205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65825.301205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64630.813953 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64630.813953 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68092.307692 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68092.307692 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64630.813953 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66820.945946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65289.634146 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64630.813953 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66820.945946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65289.634146 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) @@ -908,14 +917,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 245000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 409 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 519000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadResp 408 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) @@ -931,9 +940,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 492 # Request fanout histogram -system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 593500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2599750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2604000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 56b893c5d..625747903 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41368500 # Number of ticks simulated final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311873 # Simulator instruction rate (inst/s) -host_op_rate 311783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 850451247 # Simulator tick rate (ticks/s) -host_mem_usage 289340 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 372083 # Simulator instruction rate (inst/s) +host_op_rate 371955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1014555487 # Simulator tick rate (ticks/s) +host_mem_usage 290028 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.991492 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.991492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id @@ -172,14 +172,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4547500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4547500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4590000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4590000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7452000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7452000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7452000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7452000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -188,24 +188,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.777491 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.777491 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.075087 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.075087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id @@ -262,33 +262,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14896500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14896500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14896500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14896500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14896500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14896500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53201.785714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53201.785714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.625818 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.105687 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.520131 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy @@ -298,61 +298,66 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17378000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.510574 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency @@ -367,55 +372,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13405500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5589000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5589000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3612500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3612500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5865000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5865000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) @@ -440,10 +450,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 420000 # La system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 331 # Transaction distribution system.membus.trans_dist::ReadResp 331 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index fd1fa8729..bc3ca9120 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041219500 # Number of ticks simulated -final_tick 147041219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 147041221500 # Number of ticks simulated +final_tick 147041221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 770569 # Simulator instruction rate (inst/s) -host_op_rate 774399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1250931150 # Simulator tick rate (ticks/s) -host_mem_usage 437476 # Number of bytes of host memory used -host_seconds 117.55 # Real time elapsed on the host +host_inst_rate 1077194 # Simulator instruction rate (inst/s) +host_op_rate 1082547 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1748701394 # Simulator tick rate (ticks/s) +host_mem_usage 444972 # Number of bytes of host memory used +host_seconds 84.09 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082439 # number of cpu cycles simulated +system.cpu.numCycles 294082443 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576862 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082438.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294082442.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732305 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593917 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.593910 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410415000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593917 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 54410415500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593910 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361087000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361087000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508357000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11508357000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508475500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11508475500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1170574500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1170574500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 120000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 120000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981754500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11981754500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981874500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11981874500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.940168 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.940168 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.067359 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.067359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.154003 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.154003 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12009.940168 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12009.940168 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 40000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 40000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.067359 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.067359 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.154003 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.154003 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120567 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120565 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120565 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id @@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32032000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32032000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32032000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32034000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32034000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32034000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32034000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32034000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32034000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses @@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53475.792988 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53475.792988 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53475.792988 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53475.792988 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53475.792988 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53475.792988 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53479.131886 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53479.131886 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53479.131886 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53479.131886 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31133500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 31133500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31133500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 31133500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31133500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 31133500 # number of overall MSHR miss cycles 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52479.131886 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852356 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 9567.852238 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446284 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172984 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233089 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446176 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172976 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233086 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy 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miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42517.218862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42517.218862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42520.797227 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42520.797227 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42509.302326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42509.302326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42520.797227 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42520.797227 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 256 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1890101 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1890101 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1890101 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1887384500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 792 # Transaction distribution system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution system.membus.trans_dist::ReadExResp 14548 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) @@ -624,9 +636,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 76963500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 76964500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index ebb41442e..37bdd5ca5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,79 +1,73 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107944000 # Number of ticks simulated -final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107900000 # Number of ticks simulated +final_tick 107900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128828 # Simulator instruction rate (inst/s) -host_op_rate 128828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13989470 # Simulator tick rate (ticks/s) -host_mem_usage 239356 # Number of bytes of host memory used -host_seconds 7.72 # Real time elapsed on the host -sim_insts 994048 # Number of instructions simulated -sim_ops 994048 # Number of ops (including micro ops) simulated +host_inst_rate 161691 # Simulator instruction rate (inst/s) +host_op_rate 161690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17527940 # Simulator tick rate (ticks/s) +host_mem_usage 308804 # Number of bytes of host memory used +host_seconds 6.16 # Real time elapsed on the host +sim_insts 995346 # Number of instructions simulated +sim_ops 995346 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5440 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 576 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42816 # Number of bytes read from this memory +system.physmem.bytes_read::total 42944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 85 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 9 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 669 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 214629808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100200104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47432002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11858000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 4150300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7707700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2964500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7707700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 396650115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 214629808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47432002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 4150300 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2964500 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269176610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 214629808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100200104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47432002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11858000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 4150300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7707700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2964500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7707700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 396650115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 670 # Number of read requests accepted +system.physmem.num_reads::total 671 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 214717331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100240964 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50417053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11862836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7710843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 5338276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7710843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 397998146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 214717331 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50417053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 5338276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270472660 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 214717331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100240964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50417053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11862836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7710843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 5338276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7710843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 397998146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 672 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 670 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 672 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42880 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 43008 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42880 # Total read bytes from the system interface side +system.physmem.bytesReadSys 43008 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 115 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 75 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 27 # Per bank write bursts +system.physmem.perBankRdBursts::2 30 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts system.physmem.perBankRdBursts::4 66 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts @@ -105,14 +99,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107916000 # Total gap between requests +system.physmem.totGap 107872000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 670 # Read request sizes (log2) +system.physmem.readPktSize::6 672 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,11 +114,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -216,319 +210,319 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.702703 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.430987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 234.776821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 43 29.05% 29.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 26.35% 55.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25 16.89% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19 12.84% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.05% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.05% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 3.38% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.35% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 2.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation -system.physmem.totQLat 6539750 # Total ticks spent queuing -system.physmem.totMemAccLat 19102250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9760.82 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.744966 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.953250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 233.682770 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 43 28.86% 28.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40 26.85% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25 16.78% 72.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17 11.41% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 5.37% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 4.70% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 2.68% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.34% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 2.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 149 # Bytes accessed per row activation +system.physmem.totQLat 7242000 # Total ticks spent queuing +system.physmem.totMemAccLat 19842000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3360000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10776.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28510.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 397.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29526.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 398.59 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 397.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 398.59 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.10 # Data bus utilization in percentage -system.physmem.busUtilRead 3.10 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.11 # Data bus utilization in percentage +system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 511 # Number of row buffer hits during reads +system.physmem.readRowHits 512 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 161068.66 # Average gap between requests -system.physmem.pageHitRate 76.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2761200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 160523.81 # Average gap between requests +system.physmem.pageHitRate 76.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2776800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 39247065 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 26461500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 76167750 # Total energy per rank (pJ) -system.physmem_0.averagePower 750.559832 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 46478250 # Time in different power states +system.physmem_0.actBackEnergy 34825860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30339750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75652080 # Total energy per rank (pJ) +system.physmem_0.averagePower 745.478401 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 52910500 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 54316750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 47852500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 30855240 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 33814500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 73943955 # Total energy per rank (pJ) -system.physmem_1.averagePower 728.745214 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 59727000 # Time in different power states +system.physmem_1.actBackEnergy 31297275 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 33426750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 73998240 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.280213 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 59054500 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 42022000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 42666000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81450 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78581 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1205 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78182 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75500 # Number of BTB hits +system.cpu0.branchPred.lookups 81516 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78639 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1206 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 78220 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75547 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.569543 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 747 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.582715 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 751 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215889 # number of cpu cycles simulated +system.cpu0.numCycles 215801 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20419 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 481443 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81450 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76247 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165590 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2709 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 19984 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 481810 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81516 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76298 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165347 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2214 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7225 # Number of cache lines fetched +system.cpu0.fetch.PendingTrapStallCycles 2206 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7238 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 189580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.539524 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.227640 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 188895 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.550676 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.226315 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 32064 16.91% 16.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77818 41.05% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818 0.43% 58.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1146 0.60% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 623 0.33% 59.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72992 38.50% 97.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 703 0.37% 98.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 447 0.24% 98.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2969 1.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 31263 16.55% 16.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77878 41.23% 57.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 817 0.43% 58.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1146 0.61% 58.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 622 0.33% 59.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73043 38.67% 97.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 702 0.37% 98.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 447 0.24% 98.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2977 1.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 189580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.377277 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.230049 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 19697 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 152079 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 672 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1354 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 469796 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1354 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16409 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2266 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15970 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 152076 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1505 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 466337 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1001 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 319451 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 929999 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 702902 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 305355 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14096 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed +system.cpu0.fetch.rateDist::total 188895 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.377737 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.232659 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15795 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18848 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152228 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 669 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1355 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 470263 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1355 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16424 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2157 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15249 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152226 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1484 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 466822 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 991 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 319803 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 930944 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 703631 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 305659 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14144 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 901 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4587 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148758 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75265 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72519 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72258 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 390345 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 4515 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148895 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75333 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72583 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72320 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 390748 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 13187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqInstsIssued 387435 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 13210 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11146 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.041339 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.140292 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 188895 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.051060 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.134423 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 35140 18.54% 18.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4258 2.25% 20.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73622 38.83% 59.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73334 38.68% 98.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1646 0.87% 99.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 901 0.48% 99.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 423 0.22% 99.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 182 0.10% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 74 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34285 18.15% 18.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4265 2.26% 20.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73704 39.02% 59.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73391 38.85% 98.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1671 0.88% 99.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 904 0.48% 99.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 416 0.22% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 183 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 189580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 188895 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 91 32.73% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 30.22% 62.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 37.05% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 90 32.14% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 85 30.36% 62.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 105 37.50% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164205 42.43% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.43% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 148197 38.29% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74595 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164414 42.44% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.44% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 148348 38.29% 80.73% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74673 19.27% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 386997 # Type of FU issued -system.cpu0.iq.rate 1.792574 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 404550 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 387435 # Type of FU issued +system.cpu0.iq.rate 1.795335 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 280 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000723 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 964068 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 404976 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 385522 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 387275 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 387715 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71895 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71972 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2491 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2476 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1617 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1354 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2232 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 464248 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148758 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75265 # Number of dispatched store instructions +system.cpu0.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2123 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 464714 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148895 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75333 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 333 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1104 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 385946 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147890 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1051 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 331 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1444 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 386358 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 148024 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1077 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72936 # number of nop insts executed -system.cpu0.iew.exec_refs 222349 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76534 # Number of branches executed -system.cpu0.iew.exec_stores 74459 # Number of stores executed -system.cpu0.iew.exec_rate 1.787706 # Inst execution rate -system.cpu0.iew.wb_sent 385475 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 385100 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 228400 # num instructions producing a value -system.cpu0.iew.wb_consumers 231722 # num instructions consuming a value +system.cpu0.iew.exec_nop 72999 # number of nop insts executed +system.cpu0.iew.exec_refs 222560 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76623 # Number of branches executed +system.cpu0.iew.exec_stores 74536 # Number of stores executed +system.cpu0.iew.exec_rate 1.790344 # Inst execution rate +system.cpu0.iew.wb_sent 385902 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 385522 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 228646 # num instructions producing a value +system.cpu0.iew.wb_consumers 231982 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.783787 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.985664 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.786470 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.985620 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13801 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13812 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1205 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186928 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.409398 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.152220 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1206 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186239 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.420760 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.150366 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 35407 18.94% 18.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75555 40.42% 59.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1920 1.03% 60.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 633 0.34% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 494 0.26% 60.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71651 38.33% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 511 0.27% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 494 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34563 18.56% 18.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75593 40.59% 59.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1959 1.05% 60.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 634 0.34% 60.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 503 0.27% 60.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71729 38.51% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 522 0.28% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186928 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 450384 # Number of instructions committed -system.cpu0.commit.committedOps 450384 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186239 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 450840 # Number of instructions committed +system.cpu0.commit.committedOps 450840 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219907 # Number of memory references committed -system.cpu0.commit.loads 146267 # Number of loads committed +system.cpu0.commit.refs 220135 # Number of memory references committed +system.cpu0.commit.loads 146419 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75527 # Number of branches committed +system.cpu0.commit.branches 75603 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303686 # Number of committed integer instructions. +system.cpu0.commit.int_insts 303990 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72259 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 158134 35.11% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72335 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 158286 35.11% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction @@ -557,625 +551,625 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146351 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73640 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 146503 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73716 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction -system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 649458 # The number of ROB reads -system.cpu0.rob.rob_writes 931043 # The number of ROB writes +system.cpu0.commit.op_class_0::total 450840 # Class of committed instruction +system.cpu0.commit.bw_lim_events 486 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 649244 # The number of ROB reads +system.cpu0.rob.rob_writes 931981 # The number of ROB writes system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26309 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 378041 # Number of Instructions Simulated -system.cpu0.committedOps 378041 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.571073 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.571073 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.751090 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.751090 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 690199 # number of integer regfile reads -system.cpu0.int_regfile_writes 311415 # number of integer regfile writes +system.cpu0.idleCycles 26906 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 378421 # Number of Instructions Simulated +system.cpu0.committedOps 378421 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.570267 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.570267 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.753565 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.753565 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 690917 # number of integer regfile reads +system.cpu0.int_regfile_writes 311762 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 224240 # number of misc regfile reads +system.cpu0.misc_regfile_reads 224455 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 140.939988 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148370 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.011743 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 148491 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 867.660819 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 868.368421 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 140.939988 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275273 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275273 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.011743 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275414 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 598524 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 598524 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75399 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75399 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73059 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73059 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 599051 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 599051 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75429 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75429 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73130 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73130 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148458 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148458 # number of overall hits -system.cpu0.dcache.overall_hits::total 148458 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 514 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 514 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 539 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 539 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 148559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 148559 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148559 # number of overall hits +system.cpu0.dcache.overall_hits::total 148559 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 540 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 540 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1053 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1053 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1053 # number of overall misses -system.cpu0.dcache.overall_misses::total 1053 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17626915 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17626915 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36442515 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36442515 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 680000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 680000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 54069430 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 54069430 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 54069430 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 54069430 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75913 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75913 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73598 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73598 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1084 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1084 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1084 # number of overall misses +system.cpu0.dcache.overall_misses::total 1084 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16932500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16932500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35823993 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35823993 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 460000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 460000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 52756493 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 52756493 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 52756493 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 52756493 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75969 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75969 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73674 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73674 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149511 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149511 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149511 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149511 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006771 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006771 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007324 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007324 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 149643 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149643 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 149643 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 149643 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007108 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007108 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007384 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007384 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007043 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007043 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007244 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007244 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007244 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007244 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31356.481481 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31356.481481 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65852.928309 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65852.928309 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21904.761905 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 21904.761905 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48668.351476 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 48668.351476 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48668.351476 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 48668.351476 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 79.692308 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 330 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 330 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 362 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 362 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 692 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 692 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 692 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 184 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 357 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 357 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 369 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 369 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 726 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 726 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 726 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 726 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6770753 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6770753 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8530978 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8530978 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 646500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 646500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15301731 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15301731 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15301731 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15301731 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002405 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002405 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6813000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6813000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8643000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8643000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 439000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 439000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15456000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15456000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15456000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15456000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002409 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002375 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002375 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002415 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002415 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37229.508197 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37229.508197 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 49388.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 49388.571429 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20904.761905 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20904.761905 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43173.184358 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43173.184358 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43173.184358 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43173.184358 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 323 # number of replacements -system.cpu0.icache.tags.tagsinuse 240.188663 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6428 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 240.334366 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6439 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.469055 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.486971 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.188663 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469118 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.469118 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.334366 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469403 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.469403 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7839 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7839 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6428 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6428 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6428 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6428 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6428 # number of overall hits -system.cpu0.icache.overall_hits::total 6428 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses -system.cpu0.icache.overall_misses::total 797 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40514746 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40514746 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40514746 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40514746 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40514746 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40514746 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7225 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7225 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7225 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7225 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7225 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7225 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110311 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110311 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110311 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110311 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110311 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110311 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 50834.060226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 50834.060226 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 7852 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7852 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6439 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6439 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6439 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6439 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6439 # number of overall hits +system.cpu0.icache.overall_hits::total 6439 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 799 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 799 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 799 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 799 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 799 # number of overall misses +system.cpu0.icache.overall_misses::total 799 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40829000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40829000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40829000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40829000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40829000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40829000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7238 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7238 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7238 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7238 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7238 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7238 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110390 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110390 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110390 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110390 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110390 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110390 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51100.125156 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51100.125156 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51100.125156 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51100.125156 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51100.125156 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 182 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 182 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 182 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31043001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31043001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31043001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31043001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31043001 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31043001 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085121 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085121 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085121 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31621000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31621000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31621000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31621000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31621000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31621000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084968 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084968 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084968 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084968 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51416.260163 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51416.260163 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51416.260163 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52261 # Number of BP lookups -system.cpu1.branchPred.condPredicted 48386 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1341 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 44394 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 43169 # Number of BTB hits +system.cpu1.branchPred.lookups 53963 # Number of BP lookups +system.cpu1.branchPred.condPredicted 50167 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1346 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 46229 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 44971 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.240618 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.278764 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 927 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162232 # number of cpu cycles simulated +system.cpu1.numCycles 162372 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 31153 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 288417 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52261 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 44075 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 122623 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2833 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 29926 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 299894 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 53963 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 45898 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 123960 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2845 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1159 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 21623 # Number of cache lines fetched +system.cpu1.fetch.PendingTrapStallCycles 1155 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 20576 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156364 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.844523 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.218152 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::samples 156476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.916550 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.231802 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 56063 35.85% 35.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 50599 32.36% 68.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6236 3.99% 72.20% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3531 2.26% 74.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 937 0.60% 75.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 32564 20.83% 95.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1222 0.78% 96.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 843 0.54% 97.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4369 2.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 52995 33.87% 33.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51987 33.22% 67.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5834 3.73% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3448 2.20% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 958 0.61% 73.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 34873 22.29% 95.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1256 0.80% 96.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 838 0.54% 97.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4287 2.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156364 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.322137 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.777806 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18077 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 54814 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 78767 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3280 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1416 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 271927 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1416 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18807 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 25020 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13667 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 79411 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 18033 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 268621 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 15397 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 31 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.332342 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.846956 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18007 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50929 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 83026 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3082 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1422 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 283749 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1422 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18719 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22929 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13387 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84356 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 15653 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 280426 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 13898 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 189765 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 514915 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 401460 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 175087 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14678 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 22640 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 74986 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 35614 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 35483 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 30428 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 223482 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13593 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.439008 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.385420 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 198372 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 540599 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 420692 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 183271 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15101 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1203 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1280 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 20103 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 79058 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 37890 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 37399 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 32713 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 233810 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5671 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 234514 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 14000 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11968 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 653 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156476 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.498722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.383815 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 59519 38.06% 38.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 20894 13.36% 51.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 35016 22.39% 73.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 34585 22.12% 95.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3417 2.19% 98.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1600 1.02% 99.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 882 0.56% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 240 0.15% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 211 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 56669 36.22% 36.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 19562 12.50% 48.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 37085 23.70% 72.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 36801 23.52% 95.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3420 2.19% 98.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1602 1.02% 99.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 884 0.56% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 239 0.15% 99.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 214 0.14% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156364 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156476 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 92 27.88% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 29 8.79% 36.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 87 24.58% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 58 16.38% 40.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 59.04% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 110922 49.30% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 79078 35.14% 84.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 35009 15.56% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 114757 48.93% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 82569 35.21% 84.14% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37188 15.86% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 225009 # Type of FU issued -system.cpu1.iq.rate 1.386958 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 243255 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 234514 # Type of FU issued +system.cpu1.iq.rate 1.444301 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 354 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001510 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 625904 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 253521 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 232777 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 225339 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 234868 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 30296 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 32465 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2626 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2830 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1552 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1669 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1416 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7338 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 266019 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 165 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 74986 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 35614 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1422 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6958 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 277649 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 222 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 79058 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 37890 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1125 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1578 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 223948 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 74035 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 481 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1587 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 233397 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 77941 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1117 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 36391 # number of nop insts executed -system.cpu1.iew.exec_refs 108940 # number of memory reference insts executed -system.cpu1.iew.exec_branches 45914 # Number of branches executed -system.cpu1.iew.exec_stores 34905 # Number of stores executed -system.cpu1.iew.exec_rate 1.380418 # Inst execution rate -system.cpu1.iew.wb_sent 223649 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 223369 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 126652 # num instructions producing a value -system.cpu1.iew.wb_consumers 133295 # num instructions consuming a value +system.cpu1.iew.exec_nop 38168 # number of nop insts executed +system.cpu1.iew.exec_refs 115010 # number of memory reference insts executed +system.cpu1.iew.exec_branches 47577 # Number of branches executed +system.cpu1.iew.exec_stores 37069 # Number of stores executed +system.cpu1.iew.exec_rate 1.437421 # Inst execution rate +system.cpu1.iew.wb_sent 233106 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 232777 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 132706 # num instructions producing a value +system.cpu1.iew.wb_consumers 139339 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.376849 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.950163 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.433603 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.952397 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14380 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5466 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1341 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 153714 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.636819 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.057713 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14853 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5018 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1346 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 153761 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.708866 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.078798 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 64759 42.13% 42.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 42554 27.68% 69.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5173 3.37% 73.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6281 4.09% 77.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1529 0.99% 78.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 30355 19.75% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 785 0.51% 98.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 966 0.63% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1312 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61362 39.91% 39.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 44235 28.77% 68.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5219 3.39% 72.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5854 3.81% 75.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1519 0.99% 76.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 32513 21.15% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 819 0.53% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 953 0.62% 99.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1287 0.84% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 153714 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 251602 # Number of instructions committed -system.cpu1.commit.committedOps 251602 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 153761 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 262757 # Number of instructions committed +system.cpu1.commit.committedOps 262757 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 106422 # Number of memory references committed -system.cpu1.commit.loads 72360 # Number of loads committed -system.cpu1.commit.membars 4751 # Number of memory barriers committed -system.cpu1.commit.branches 44778 # Number of branches committed +system.cpu1.commit.refs 112449 # Number of memory references committed +system.cpu1.commit.loads 76228 # Number of loads committed +system.cpu1.commit.membars 4303 # Number of memory barriers committed +system.cpu1.commit.branches 46487 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 173320 # Number of committed integer instructions. +system.cpu1.commit.int_insts 181057 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 35567 14.14% 14.14% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 104862 41.68% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.81% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 77111 30.65% 86.46% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 34062 13.54% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 37276 14.19% 14.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 108729 41.38% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.57% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 80531 30.65% 86.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 36221 13.78% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 417798 # The number of ROB reads -system.cpu1.rob.rob_writes 534614 # The number of ROB writes +system.cpu1.commit.op_class_0::total 262757 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1287 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 429498 # The number of ROB reads +system.cpu1.rob.rob_writes 557934 # The number of ROB writes system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 46290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 211284 # Number of Instructions Simulated -system.cpu1.committedOps 211284 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.767839 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.767839 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.302357 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.302357 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 386957 # number of integer regfile reads -system.cpu1.int_regfile_writes 181537 # number of integer regfile writes +system.cpu1.idleCycles 5896 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 221178 # Number of Instructions Simulated +system.cpu1.committedOps 221178 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.734124 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.734124 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.362168 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.362168 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 405088 # number of integer regfile reads +system.cpu1.int_regfile_writes 189742 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 110600 # number of misc regfile reads +system.cpu1.misc_regfile_reads 116634 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.579817 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 40184 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.592984 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42361 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1435.142857 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1512.892857 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.579817 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049961 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.049961 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.592984 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049986 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.049986 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 311400 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 311400 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 43257 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 43257 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 33840 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 33840 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 77097 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 77097 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 77097 # number of overall hits -system.cpu1.dcache.overall_hits::total 77097 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 466 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 466 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 153 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 153 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses -system.cpu1.dcache.overall_misses::total 619 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9865731 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9865731 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3999011 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3999011 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 673507 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 673507 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13864742 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13864742 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13864742 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13864742 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 43723 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 43723 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 33993 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 33993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.tag_accesses 326938 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 326938 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 44990 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 44990 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 35982 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 35982 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 80972 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 80972 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 80972 # number of overall hits +system.cpu1.dcache.overall_hits::total 80972 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 461 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 461 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 170 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 170 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 631 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 631 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 631 # number of overall misses +system.cpu1.dcache.overall_misses::total 631 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8707500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8707500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4222000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4222000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 652500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 652500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12929500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12929500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12929500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12929500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 45451 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 45451 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 36152 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 36152 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 77716 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 77716 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 77716 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 77716 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010658 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.010658 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004501 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004501 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.826087 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007965 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007965 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007965 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007965 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893 # average overall miss latency +system.cpu1.dcache.demand_accesses::cpu1.data 81603 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 81603 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 81603 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 81603 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010143 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010143 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004702 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004702 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007733 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007733 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007733 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007733 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18888.286334 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18888.286334 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24835.294118 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24835.294118 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11651.785714 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11651.785714 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20490.491284 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20490.491284 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20490.491284 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1184,106 +1178,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 344 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 344 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 303 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 303 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 62 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 365 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 365 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 365 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 365 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 275 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 275 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1943270 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1943270 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1707489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1707489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 587993 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 587993 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3650759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3650759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3650759 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3650759 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003820 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003820 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003177 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003177 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.826087 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003539 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003539 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1924500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1924500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 596500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 596500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3884000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3884000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3884000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3884000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003476 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003476 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002987 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002987 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003260 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003260 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003260 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003260 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.379747 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12180.379747 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18143.518519 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18143.518519 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10651.785714 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10651.785714 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14601.503759 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14601.503759 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14601.503759 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 385 # number of replacements -system.cpu1.icache.tags.tagsinuse 83.683741 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21045 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 42.344064 # Average number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 85.488179 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19990 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.980000 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 83.683741 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.163445 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.163445 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id +system.cpu1.icache.tags.occ_blocks::cpu1.inst 85.488179 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.166969 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.166969 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 115 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22120 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22120 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21045 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21045 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21045 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21045 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21045 # number of overall hits -system.cpu1.icache.overall_hits::total 21045 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 578 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 578 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 578 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 578 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 578 # number of overall misses -system.cpu1.icache.overall_misses::total 578 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14251747 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14251747 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14251747 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14251747 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14251747 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14251747 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21623 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21623 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21623 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21623 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21623 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21623 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026731 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.026731 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026731 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.026731 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026731 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.026731 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24657.001730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24657.001730 # average overall miss latency +system.cpu1.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.224609 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 21076 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21076 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 19990 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19990 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19990 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19990 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19990 # number of overall hits +system.cpu1.icache.overall_hits::total 19990 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 586 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 586 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 586 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 586 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 586 # number of overall misses +system.cpu1.icache.overall_misses::total 586 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14253000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14253000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14253000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14253000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14253000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14253000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20576 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20576 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20576 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20576 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20576 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20576 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028480 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028480 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028480 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028480 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028480 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028480 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24322.525597 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24322.525597 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24322.525597 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24322.525597 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24322.525597 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1292,410 +1286,410 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11245503 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11245503 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11245503 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11245503 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11245503 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11245503 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022985 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022985 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022985 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 86 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 86 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 86 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 86 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 500 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 500 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 500 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11778500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11778500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11778500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11778500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11778500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11778500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024300 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024300 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024300 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024300 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23557 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23557 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23557 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51309 # Number of BP lookups -system.cpu2.branchPred.condPredicted 47950 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1280 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 43975 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 43053 # Number of BTB hits +system.cpu2.branchPred.lookups 40179 # Number of BP lookups +system.cpu2.branchPred.condPredicted 36730 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1284 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 32851 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 31814 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.903354 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 96.843323 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 891 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 161860 # number of cpu cycles simulated +system.cpu2.numCycles 162000 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 31583 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 282068 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51309 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 43939 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 125716 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2717 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 38502 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 208114 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 40179 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 32705 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 119095 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2725 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1207 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 22884 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 412 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 159877 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.764281 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.167875 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1151 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 29772 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 430 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160123 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.299713 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.967894 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 59518 37.23% 37.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51095 31.96% 69.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 7306 4.57% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3438 2.15% 75.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 997 0.62% 76.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 31616 19.78% 96.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1254 0.78% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 769 0.48% 97.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3884 2.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 78817 49.22% 49.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 43234 27.00% 76.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 10666 6.66% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3447 2.15% 85.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1063 0.66% 85.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 17019 10.63% 96.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1193 0.75% 97.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 770 0.48% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3914 2.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 159877 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.316996 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.742667 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17468 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 61085 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 76240 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3716 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1358 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 267722 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1358 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18170 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 29188 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12834 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 77782 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 20535 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 264399 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 18336 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 160123 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.248019 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.284654 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17927 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 88037 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 47537 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5250 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1362 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 193193 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1362 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18611 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 44936 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13295 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 49321 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 32588 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 189743 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 29082 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 12 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 185298 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 503121 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 392507 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 170476 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14822 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1180 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 25168 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 73362 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 34382 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 35300 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 29228 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 218628 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13773 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.379166 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.379581 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 129905 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 340650 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 270570 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 115581 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14324 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1221 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1285 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 37412 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 47453 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 19802 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 23979 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 14667 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 152040 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10334 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 157175 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13577 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11994 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160123 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.981589 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.305622 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 63376 39.64% 39.64% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23374 14.62% 54.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 33553 20.99% 75.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 33206 20.77% 96.02% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3423 2.14% 98.16% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1623 1.02% 99.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 877 0.55% 99.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 230 0.14% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 215 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 83163 51.94% 51.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 32837 20.51% 72.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 19129 11.95% 84.39% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 18742 11.70% 96.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3350 2.09% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1588 0.99% 99.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 888 0.55% 99.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 204 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 159877 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160123 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 86 23.69% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 68 18.73% 42.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 85 23.42% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 69 19.01% 42.42% # attempts to use FU when none available system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 108751 49.32% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 78120 35.43% 84.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 33626 15.25% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 82729 52.63% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.63% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 55347 35.21% 87.85% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 19099 12.15% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 220497 # Type of FU issued -system.cpu2.iq.rate 1.362270 # Inst issue rate +system.cpu2.iq.FU_type_0::total 157175 # Type of FU issued +system.cpu2.iq.rate 0.970216 # Inst issue rate system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 239427 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fu_busy_rate 0.002310 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 474890 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 175995 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 155491 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 220860 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 157538 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 28926 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 14398 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2863 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2822 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1691 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1616 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1358 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 8128 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 261616 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 204 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 73362 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 34382 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1362 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 11555 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 187117 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 206 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 47453 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 19802 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1045 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1500 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 219377 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 72164 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1120 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1028 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1490 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 156065 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 46210 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1110 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 36005 # number of nop insts executed -system.cpu2.iew.exec_refs 105679 # number of memory reference insts executed -system.cpu2.iew.exec_branches 45327 # Number of branches executed -system.cpu2.iew.exec_stores 33515 # Number of stores executed -system.cpu2.iew.exec_rate 1.355350 # Inst execution rate -system.cpu2.iew.wb_sent 219089 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 218768 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 123331 # num instructions producing a value -system.cpu2.iew.wb_consumers 129941 # num instructions consuming a value +system.cpu2.iew.exec_nop 24743 # number of nop insts executed +system.cpu2.iew.exec_refs 65197 # number of memory reference insts executed +system.cpu2.iew.exec_branches 33975 # Number of branches executed +system.cpu2.iew.exec_stores 18987 # Number of stores executed +system.cpu2.iew.exec_rate 0.963364 # Inst execution rate +system.cpu2.iew.wb_sent 155796 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 155491 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 82775 # num instructions producing a value +system.cpu2.iew.wb_consumers 89322 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.351588 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.949131 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.959821 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.926703 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14642 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 6361 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1280 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 157221 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.570534 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.031430 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14525 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9553 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1284 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 157478 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.095639 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.783689 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 69336 44.10% 44.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 41971 26.70% 70.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5151 3.28% 74.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7156 4.55% 78.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1534 0.98% 79.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 28975 18.43% 98.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 827 0.53% 98.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1310 0.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 92218 58.56% 58.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 30640 19.46% 78.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5207 3.31% 81.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 10311 6.55% 87.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1532 0.97% 88.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 14554 9.24% 98.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 759 0.48% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 956 0.61% 99.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1301 0.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 157221 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 246921 # Number of instructions committed -system.cpu2.commit.committedOps 246921 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 157478 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 172539 # Number of instructions committed +system.cpu2.commit.committedOps 172539 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 103190 # Number of memory references committed -system.cpu2.commit.loads 70499 # Number of loads committed -system.cpu2.commit.membars 5644 # Number of memory barriers committed -system.cpu2.commit.branches 44296 # Number of branches committed +system.cpu2.commit.refs 62817 # Number of memory references committed +system.cpu2.commit.loads 44631 # Number of loads committed +system.cpu2.commit.membars 8825 # Number of memory barriers committed +system.cpu2.commit.branches 32966 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 169605 # Number of committed integer instructions. +system.cpu2.commit.int_insts 117894 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 35083 14.21% 14.21% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 103004 41.72% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 76143 30.84% 86.76% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 32691 13.24% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 23742 13.76% 13.76% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 77155 44.72% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 58.48% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 53456 30.98% 89.46% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 18186 10.54% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 416888 # The number of ROB reads -system.cpu2.rob.rob_writes 525783 # The number of ROB writes -system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1983 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 46662 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 206194 # Number of Instructions Simulated -system.cpu2.committedOps 206194 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.784989 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.784989 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.273903 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.273903 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 376797 # number of integer regfile reads -system.cpu2.int_regfile_writes 176595 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 172539 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 342655 # The number of ROB reads +system.cpu2.rob.rob_writes 376773 # The number of ROB writes +system.cpu2.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 46457 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 139972 # Number of Instructions Simulated +system.cpu2.committedOps 139972 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.157374 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.157374 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.864025 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.864025 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 255225 # number of integer regfile reads +system.cpu2.int_regfile_writes 121437 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 107278 # number of misc regfile reads +system.cpu2.misc_regfile_reads 66781 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 24.051885 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 38880 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 23.055357 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 24315 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1340.689655 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 838.448276 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.051885 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.046976 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.046976 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.055357 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045030 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.045030 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 303893 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 303893 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42781 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42781 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 32487 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 32487 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 75268 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 75268 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 75268 # number of overall hits -system.cpu2.dcache.overall_hits::total 75268 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 440 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 440 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 573 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 573 # number of overall misses -system.cpu2.dcache.overall_misses::total 573 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7341783 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7341783 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2962762 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2962762 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 594005 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 594005 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 10304545 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 10304545 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 10304545 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 10304545 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 43221 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 32620 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 32620 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 75841 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 75841 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 75841 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 75841 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010180 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010180 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004077 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004077 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.802817 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007555 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007555 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007555 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007555 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127 # average overall miss latency +system.cpu2.dcache.tags.tag_accesses 200189 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 200189 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 31354 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 31354 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 17953 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 17953 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 17 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 49307 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 49307 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 49307 # number of overall hits +system.cpu2.dcache.overall_hits::total 49307 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 441 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 441 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 151 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 151 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 65 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 65 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 592 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 592 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 592 # number of overall misses +system.cpu2.dcache.overall_misses::total 592 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 6519500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 6519500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3142000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3142000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 710000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 710000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 9661500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 9661500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 9661500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 9661500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 31795 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 31795 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 18104 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 18104 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 82 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 82 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 49899 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 49899 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 49899 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 49899 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013870 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.013870 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008341 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.008341 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.792683 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.792683 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011864 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.011864 # miss rate for demand accesses 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+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 16320.101351 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 16320.101351 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1704,106 +1698,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 285 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 31 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 316 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 316 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 316 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 257 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 257 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1424773 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1424773 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1555988 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1555988 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 508495 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 508495 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2980761 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2980761 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2980761 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2980761 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003586 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003586 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003127 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003127 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003389 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003389 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.083871 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.083871 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15254.784314 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15254.784314 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8920.964912 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8920.964912 # average SwapReq mshr miss latency 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of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 560 # number of overall misses -system.cpu2.icache.overall_misses::total 560 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8454990 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8454990 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8454990 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8454990 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8454990 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8454990 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 22884 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 22884 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 22884 # number of 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15098.196429 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15098.196429 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15098.196429 # average overall miss latency +system.cpu2.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 30268 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 30268 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 29208 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 29208 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 29208 # number of demand (read+write) hits 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# number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1812,409 +1806,409 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 66 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 66 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 66 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 494 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 494 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 494 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 494 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 494 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 494 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6668508 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6668508 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6668508 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6668508 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6668508 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6668508 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021587 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021587 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021587 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 496 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 496 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 496 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 496 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6709500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6709500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6709500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6709500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6709500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6709500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.016660 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.016660 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.016660 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.016660 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13527.217742 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13527.217742 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13527.217742 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 49957 # Number of BP lookups -system.cpu3.branchPred.condPredicted 46526 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1263 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 42773 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 41661 # Number of BTB hits +system.cpu3.branchPred.lookups 59537 # Number of BP lookups +system.cpu3.branchPred.condPredicted 56113 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1261 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 52336 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 51268 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.400229 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.959340 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 894 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 161075 # number of cpu cycles simulated +system.cpu3.numCycles 161647 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 32422 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 272949 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49957 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 42547 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 124988 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2685 # Number of cycles fetch has spent squashing -system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.icacheStallCycles 26901 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 335954 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 59537 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 52162 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 130682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2681 # Number of cycles fetch has spent squashing +system.cpu3.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1170 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 23669 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 411 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 159935 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.706625 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.149562 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps +system.cpu3.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 18139 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 423 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 160153 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 2.097707 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.240976 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 61940 38.73% 38.73% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 50129 31.34% 70.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7684 4.80% 74.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3433 2.15% 77.02% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1026 0.64% 77.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 29810 18.64% 96.30% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1265 0.79% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 775 0.48% 97.58% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3873 2.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 45773 28.58% 28.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 56940 35.55% 64.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 4846 3.03% 67.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3496 2.18% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1060 0.66% 70.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 42180 26.34% 96.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1201 0.75% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 768 0.48% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3889 2.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 159935 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.310147 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.694546 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17524 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 64435 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 72722 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3902 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1342 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 258692 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1342 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18198 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 31170 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12771 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 73832 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 22612 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 255419 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 23 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 160153 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.368315 # Number of branch fetches per cycle +system.cpu3.fetch.rate 2.078319 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 16971 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 42083 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 97172 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 2577 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1340 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 322134 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1340 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 17645 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 17747 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12855 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 98257 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 12299 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 318864 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 10783 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 178600 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 483471 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 377749 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 164114 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14486 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1167 # count of serializing insts renamed +system.cpu3.rename.RenamedOperands 225541 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 621446 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 481213 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 211532 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14009 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1171 # count of serializing insts renamed system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 27248 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 70256 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32624 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33902 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 27488 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 210626 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13428 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.332429 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.375890 # Number of insts issued each cycle +system.cpu3.rename.skidInsts 16730 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 92339 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 45060 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 43467 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 39931 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 267326 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 4600 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 267770 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12807 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10139 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 551 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 160153 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.671964 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.354316 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 65625 41.03% 41.03% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 24603 15.38% 56.42% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31869 19.93% 76.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 31495 19.69% 96.03% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3384 2.12% 98.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1646 1.03% 99.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 234 0.15% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 48755 30.44% 30.44% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 16655 10.40% 40.84% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 44376 27.71% 68.55% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 43948 27.44% 95.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3484 2.18% 98.17% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1651 1.03% 99.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 222 0.14% 99.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 159935 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 160153 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 83 23.71% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 23.71% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 58 16.57% 40.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 59.71% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 86 25.67% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 40 11.94% 37.61% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 105687 49.59% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 75490 35.42% 85.02% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31925 14.98% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 128178 47.87% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 95149 35.53% 83.40% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 44443 16.60% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 213102 # Type of FU issued -system.cpu3.iq.rate 1.322999 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 231462 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 267770 # Type of FU issued +system.cpu3.iq.rate 1.656511 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 335 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001251 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 696028 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 284773 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 266078 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 213452 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 268105 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 27230 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 39763 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2740 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2450 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1547 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1342 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8471 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 252649 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 70256 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32624 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1081 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1340 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 5357 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 316296 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 170 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 92339 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 45060 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu3.iew.memOrderViolationEvents 40 # Number of memory order violations system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1012 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1478 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 211973 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 69143 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1129 # Number of squashed instructions skipped in execute +system.cpu3.iew.predictedNotTakenIncorrect 1001 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1467 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 266621 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 91475 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1149 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34658 # number of nop insts executed -system.cpu3.iew.exec_refs 100953 # number of memory reference insts executed -system.cpu3.iew.exec_branches 44015 # Number of branches executed -system.cpu3.iew.exec_stores 31810 # Number of stores executed -system.cpu3.iew.exec_rate 1.315989 # Inst execution rate -system.cpu3.iew.wb_sent 211700 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 211399 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 118601 # num instructions producing a value -system.cpu3.iew.wb_consumers 125234 # num instructions consuming a value +system.cpu3.iew.exec_nop 44370 # number of nop insts executed +system.cpu3.iew.exec_refs 135810 # number of memory reference insts executed +system.cpu3.iew.exec_branches 53906 # Number of branches executed +system.cpu3.iew.exec_stores 44335 # Number of stores executed +system.cpu3.iew.exec_rate 1.649403 # Inst execution rate +system.cpu3.iew.wb_sent 266372 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 266078 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 153535 # num instructions producing a value +system.cpu3.iew.wb_consumers 160065 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.312426 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.947035 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.646044 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.959204 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14249 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6748 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1263 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 157342 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.514834 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.009338 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 13497 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 4049 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1261 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157643 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.920440 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.127029 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 72048 45.79% 45.79% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 40652 25.84% 71.63% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5170 3.29% 74.91% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7572 4.81% 79.73% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1532 0.97% 80.70% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 27266 17.33% 98.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 833 0.53% 98.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 969 0.62% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1300 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 52663 33.41% 33.41% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 50442 32.00% 65.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5240 3.32% 68.73% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 4903 3.11% 71.84% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1534 0.97% 72.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 39716 25.19% 98.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 903 0.57% 98.58% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 957 0.61% 99.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1285 0.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 157342 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 238347 # Number of instructions committed -system.cpu3.commit.committedOps 238347 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157643 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 302744 # Number of instructions committed +system.cpu3.commit.committedOps 302744 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 98515 # Number of memory references committed -system.cpu3.commit.loads 67516 # Number of loads committed -system.cpu3.commit.membars 6034 # Number of memory barriers committed -system.cpu3.commit.branches 42994 # Number of branches committed +system.cpu3.commit.refs 133402 # Number of memory references committed +system.cpu3.commit.loads 89889 # Number of loads committed +system.cpu3.commit.membars 3344 # Number of memory barriers committed +system.cpu3.commit.branches 52826 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 163632 # Number of committed integer instructions. +system.cpu3.commit.int_insts 208356 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 33784 14.17% 14.17% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 100014 41.96% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.14% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 73550 30.86% 86.99% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 30999 13.01% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 43625 14.41% 14.41% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 122373 40.42% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.83% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 93233 30.80% 85.63% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 43513 14.37% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 408052 # The number of ROB reads -system.cpu3.rob.rob_writes 507784 # The number of ROB writes +system.cpu3.commit.op_class_0::total 302744 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1285 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 472013 # The number of ROB reads +system.cpu3.rob.rob_writes 634991 # The number of ROB writes system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1140 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 47445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 198529 # Number of Instructions Simulated -system.cpu3.committedOps 198529 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.811342 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.811342 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.232525 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.232525 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 362535 # number of integer regfile reads -system.cpu3.int_regfile_writes 170128 # number of integer regfile writes +system.cpu3.idleCycles 1494 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 46809 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 255775 # Number of Instructions Simulated +system.cpu3.committedOps 255775 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.631989 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.631989 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.582306 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.582306 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 467282 # number of integer regfile reads +system.cpu3.int_regfile_writes 217631 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 102551 # number of misc regfile reads +system.cpu3.misc_regfile_reads 137439 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.026048 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 37058 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.171664 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 49547 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1323.500000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1769.535714 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.026048 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.044973 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.044973 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.171664 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047210 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047210 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 291822 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 291822 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 41456 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41456 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 30794 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 30794 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 72250 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 72250 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 72250 # number of overall hits -system.cpu3.dcache.overall_hits::total 72250 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 440 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 440 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 577 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 577 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 577 # number of overall misses -system.cpu3.dcache.overall_misses::total 577 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7521134 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 7521134 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3020012 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3020012 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 589507 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 589507 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 10541146 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 10541146 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 10541146 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 10541146 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41896 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41896 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 30931 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 30931 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 72827 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 72827 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 72827 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 72827 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010502 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010502 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004429 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004429 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007923 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007923 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007923 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007923 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 381069 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 381069 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 51168 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 51168 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 43290 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 43290 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 10 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 94458 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 94458 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 94458 # number of overall hits +system.cpu3.dcache.overall_hits::total 94458 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 527 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 527 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 164 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 164 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 49 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 49 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 691 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 691 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 691 # number of overall misses +system.cpu3.dcache.overall_misses::total 691 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8076500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3222500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3222500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 607500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 607500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11299000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11299000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11299000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11299000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 51695 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 51695 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 43454 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 43454 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 59 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 59 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 95149 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 95149 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 95149 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 95149 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010194 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010194 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003774 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003774 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830508 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.830508 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007262 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007262 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007262 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007262 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15325.426945 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15325.426945 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19649.390244 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19649.390244 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12397.959184 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 12397.959184 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16351.664255 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16351.664255 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16351.664255 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16351.664255 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2223,385 +2217,389 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 288 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 322 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 322 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 322 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 255 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 255 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1429011 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1429011 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1527238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1527238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 508493 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 508493 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2956249 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2956249 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2956249 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2956249 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003628 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003628 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003330 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003330 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003501 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003501 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9401.388158 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9401.388158 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9416.537037 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9416.537037 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 382 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 434 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 434 # 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occupancy per task id -system.cpu3.icache.tags.tag_accesses 24167 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 24167 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 23109 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23109 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23109 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23109 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23109 # number of overall hits -system.cpu3.icache.overall_hits::total 23109 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 560 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 560 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 560 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 560 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 560 # number of overall misses -system.cpu3.icache.overall_misses::total 560 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7349496 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7349496 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7349496 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7349496 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7349496 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7349496 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 23669 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 23669 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 23669 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 23669 # number 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13124.100000 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13124.100000 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13124.100000 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 18637 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 18637 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 17573 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 17573 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 17573 # number of demand (read+write) hits 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48 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 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MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6152504 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6152504 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6152504 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6152504 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6152504 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6152504 # number of overall MSHR miss cycles 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overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6839000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6839000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6839000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6839000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6839000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6839000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.027455 # mshr miss rate for ReadReq accesses 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average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13732.931727 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 421.791819 # Cycle average of tags in use -system.l2c.tags.total_refs 1669 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 536 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.113806 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 422.903421 # Cycle average of tags in use +system.l2c.tags.total_refs 2336 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 538 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.342007 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 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0.006453 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 538 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008179 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 20118 # Number of tag accesses -system.l2c.tags.data_accesses 20118 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 251 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 414 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 481 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 491 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1669 # number of ReadReq hits +system.l2c.tags.age_task_id_blocks_1024::2 139 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008209 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 25512 # Number of tag accesses +system.l2c.tags.data_accesses 25512 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 251 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 412 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 486 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 485 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1634 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 414 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 486 # number of demand (read+write) hits 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number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 364 # number of ReadCleanReq misses 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+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86730.769231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64944.444444 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 80115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69571.428571 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 539 # Transaction distribution -system.membus.trans_dist::ReadResp 538 # Transaction distribution -system.membus.trans_dist::UpgradeReq 276 # Transaction distribution -system.membus.trans_dist::UpgradeResp 76 # Transaction distribution -system.membus.trans_dist::ReadExReq 171 # Transaction distribution +system.membus.trans_dist::ReadResp 540 # Transaction distribution +system.membus.trans_dist::UpgradeReq 281 # Transaction distribution +system.membus.trans_dist::UpgradeResp 75 # Transaction distribution +system.membus.trans_dist::ReadExReq 168 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1731 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1731 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42816 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 240 # Total snoops (count) -system.membus.snoop_fanout::samples 986 # Request fanout histogram +system.membus.trans_dist::ReadSharedReq 541 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42944 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 243 # Total snoops (count) +system.membus.snoop_fanout::samples 990 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 986 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 990 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 986 # Request fanout histogram -system.membus.reqLayer0.occupancy 941000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 990 # Request fanout histogram +system.membus.reqLayer0.occupancy 926003 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3702674 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3714925 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.4 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2762 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2761 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2768 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 401 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 401 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1229 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::CleanEvict 670 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2109 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 660 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1469 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 988 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1144 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 350 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6560 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 150464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1012 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram +system.toL2Bus.pkt_size::total 150784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1022 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4941 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -2836,29 +2828,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4941 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1736971 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 994999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4941 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2489462 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 921499 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 532769 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 506002 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 762997 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 751497 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 438748 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 425967 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 744992 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 748987 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 415244 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 449462 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 747996 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 748992 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 406758 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 400481 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 833acaaf7..6ed919c46 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1398636 # Simulator instruction rate (inst/s) -host_op_rate 1398593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181097192 # Simulator tick rate (ticks/s) -host_mem_usage 299844 # Number of bytes of host memory used -host_seconds 0.48 # Real time elapsed on the host +host_inst_rate 1750110 # Simulator instruction rate (inst/s) +host_op_rate 1750047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226603798 # Simulator tick rate (ticks/s) +host_mem_usage 303668 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -59,255 +59,7 @@ system.physmem.bw_total::cpu2.data 9486130 # To system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 423 # Transaction distribution -system.membus.trans_dist::ReadResp 423 # Transaction distribution -system.membus.trans_dist::UpgradeReq 273 # Transaction distribution -system.membus.trans_dist::UpgradeResp 80 # Transaction distribution -system.membus.trans_dist::ReadExReq 412 # Transaction distribution -system.membus.trans_dist::ReadExResp 136 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1108 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1108 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 15456 # Number of tag accesses -system.l2c.tags.data_accesses 15456 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 355 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 3 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 1 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.trans_dist::ReadReq 2179 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 711 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 716 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 718 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5733 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2867 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2867 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2867 # Request fanout histogram system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 175415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -367,54 +119,6 @@ system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 175388 # Class of executed instruction -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits -system.cpu0.icache.overall_hits::total 174921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. @@ -481,6 +185,54 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits +system.cpu0.icache.overall_hits::total 174921 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173297 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -539,54 +291,6 @@ system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 167432 # Class of executed instruction -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits -system.cpu1.icache.overall_hits::total 167074 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses -system.cpu1.icache.overall_misses::total 358 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. @@ -650,6 +354,54 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets nan system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173296 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -708,54 +460,6 @@ system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Cl system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::total 167367 # Class of executed instruction -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits -system.cpu2.icache.overall_hits::total 167009 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses -system.cpu2.icache.overall_misses::total 358 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. @@ -820,6 +524,54 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets nan system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 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number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses +system.cpu2.icache.overall_misses::total 358 # number of overall misses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173297 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -878,54 +630,6 @@ system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Cl system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::total 167304 # Class of executed instruction -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits -system.cpu3.icache.overall_hits::total 166945 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses -system.cpu3.icache.overall_misses::total 359 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. @@ -989,5 +693,307 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy 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number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use +system.l2c.tags.total_refs 2271 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.394299 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 23864 # Number of tag accesses +system.l2c.tags.data_accesses 23864 # Number of data accesses +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits 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(read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 185 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 296 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits +system.l2c.overall_hits::cpu2.inst 355 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits 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(read+write) misses +system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::total 559 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 282 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 62 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 3 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 1 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses +system.l2c.overall_misses::total 559 # number of overall misses +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) 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number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 273 # Transaction distribution +system.membus.trans_dist::UpgradeResp 80 # Transaction distribution +system.membus.trans_dist::ReadExReq 412 # Transaction distribution +system.membus.trans_dist::ReadExResp 136 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1108 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1108 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1051 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) 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master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 0 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3918 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 67fefac90..89934d478 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000260 # Number of seconds simulated -sim_ticks 260037500 # Number of ticks simulated -final_tick 260037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 260073500 # Number of ticks simulated +final_tick 260073500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 961598 # Simulator instruction rate (inst/s) -host_op_rate 961579 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 379344878 # Simulator tick rate (ticks/s) -host_mem_usage 302744 # Number of bytes of host memory used -host_seconds 0.69 # Real time elapsed on the host -sim_insts 659142 # Number of instructions simulated -sim_ops 659142 # Number of ops (including micro ops) simulated +host_inst_rate 1077387 # Simulator instruction rate (inst/s) +host_op_rate 1077364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 425087977 # Simulator tick rate (ticks/s) +host_mem_usage 303432 # Number of bytes of host memory used +host_seconds 0.61 # Real time elapsed on the host +sim_insts 659129 # Number of instructions simulated +sim_ops 659129 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 70143729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40609527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 1722828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3691775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 15013219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5660722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 246118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3691775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 140779695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 70143729 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 1722828 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 15013219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 246118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 87125895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 70143729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40609527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1722828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3691775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 15013219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5660722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 246118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3691775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140779695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 70134020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40603906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 3445180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3937348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 13288551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5413854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 246084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3691264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140760208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 70134020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 3445180 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 13288551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 246084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 87113835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 70134020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40603906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 3445180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3937348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 13288551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5413854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 246084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3691264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 140760208 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 520075 # number of cpu cycles simulated +system.cpu0.numCycles 520147 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 157392 # Number of instructions committed -system.cpu0.committedOps 157392 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108420 # Number of integer alu accesses +system.cpu0.committedInsts 157434 # Number of instructions committed +system.cpu0.committedOps 157434 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108448 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25835 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108420 # number of integer instructions +system.cpu0.num_conditional_control_insts 25842 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108448 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 313418 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110026 # number of times the integer registers were written +system.cpu0.num_int_register_reads 313502 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110054 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73430 # number of memory refs -system.cpu0.num_load_insts 48613 # Number of load instructions -system.cpu0.num_store_insts 24817 # Number of store instructions +system.cpu0.num_mem_refs 73451 # number of memory refs +system.cpu0.num_load_insts 48627 # Number of load instructions +system.cpu0.num_store_insts 24824 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 520074.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 520146.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26700 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23427 14.88% 14.88% # Class of executed instruction -system.cpu0.op_class::IntAlu 60513 38.43% 53.31% # Class of executed instruction +system.cpu0.Branches 26707 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23434 14.88% 14.88% # Class of executed instruction +system.cpu0.op_class::IntAlu 60527 38.43% 53.31% # Class of executed instruction system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction @@ -114,36 +114,36 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::MemRead 48697 30.93% 84.24% # Class of executed instruction -system.cpu0.op_class::MemWrite 24817 15.76% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 48711 30.93% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 24824 15.76% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 157454 # Class of executed instruction +system.cpu0.op_class::total 157496 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.649829 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 72898 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.650768 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 72919 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 436.514970 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 436.640719 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.649829 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284472 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284472 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.650768 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284474 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284474 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 293953 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 293953 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48433 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48433 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24583 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24583 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 294037 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 294037 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48447 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48447 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24590 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24590 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73016 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73016 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73016 # number of overall hits -system.cpu0.dcache.overall_hits::total 73016 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73037 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73037 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73037 # number of overall hits +system.cpu0.dcache.overall_hits::total 73037 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -154,46 +154,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 353 # system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4637996 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4637996 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6976000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4613500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4613500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6976500 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11613996 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11613996 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11613996 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11613996 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48603 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48603 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24766 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 11590000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11590000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11590000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11590000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48617 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48617 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24773 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24773 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73369 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73369 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73369 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73369 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003498 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003498 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007389 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007389 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73390 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73390 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73390 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73390 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003497 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003497 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007387 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007387 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004811 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004811 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004811 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004811 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004810 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004810 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004810 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004810 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27138.235294 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27138.235294 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38122.950820 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38122.950820 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32832.861190 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32832.861190 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,88 +214,88 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4372004 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4372004 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6701500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6701500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11073504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11073504 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11073504 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11073504 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003498 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003498 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007389 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4443500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4443500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6793500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6793500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11237000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11237000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11237000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11237000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003497 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003497 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007387 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007387 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004811 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004811 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004810 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004810 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26138.235294 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26138.235294 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37122.950820 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37122.950820 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.581030 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 156988 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 212.583222 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157030 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 336.162741 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 336.252677 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.581030 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415197 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.415197 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.583222 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415202 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.415202 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 157922 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 157922 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 156988 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 156988 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 156988 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 156988 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 156988 # number of overall hits -system.cpu0.icache.overall_hits::total 156988 # number of overall hits +system.cpu0.icache.tags.tag_accesses 157964 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 157964 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157030 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157030 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157030 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157030 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157030 # number of overall hits +system.cpu0.icache.overall_hits::total 157030 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18041500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18041500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18041500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18041500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18041500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18041500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 157455 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 157455 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 157455 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 157455 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 157455 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 157455 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002966 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002966 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002966 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002966 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002966 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002966 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38632.762313 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38632.762313 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18042500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18042500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18042500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18042500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18042500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18042500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 157497 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 157497 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 157497 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 157497 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 157497 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 157497 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002965 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002965 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002965 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002965 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002965 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002965 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38634.903640 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38634.903640 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -310,158 +310,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17341000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17341000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17341000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17341000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17341000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17341000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002966 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002966 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002966 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17575500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17575500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17575500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17575500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17575500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17575500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002965 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002965 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002965 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 520075 # number of cpu cycles simulated +system.cpu1.numCycles 520147 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 168980 # Number of instructions committed -system.cpu1.committedOps 168980 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 110320 # Number of integer alu accesses +system.cpu1.committedInsts 165571 # Number of instructions committed +system.cpu1.committedOps 165571 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 111555 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 33339 # number of instructions that are conditional controls -system.cpu1.num_int_insts 110320 # number of integer instructions +system.cpu1.num_conditional_control_insts 31016 # number of instructions that are conditional controls +system.cpu1.num_int_insts 111555 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 270098 # number of times the integer registers were read -system.cpu1.num_int_register_writes 102062 # number of times the integer registers were written +system.cpu1.num_int_register_reads 284333 # number of times the integer registers were read +system.cpu1.num_int_register_writes 108565 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 53149 # number of memory refs -system.cpu1.num_load_insts 40825 # Number of load instructions -system.cpu1.num_store_insts 12324 # Number of store instructions +system.cpu1.num_mem_refs 56707 # number of memory refs +system.cpu1.num_load_insts 41448 # Number of load instructions +system.cpu1.num_store_insts 15259 # Number of store instructions system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles -system.cpu1.num_busy_cycles 452347.998260 # Number of busy cycles -system.cpu1.not_idle_fraction 0.869775 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.130225 # Percentage of idle cycles -system.cpu1.Branches 34992 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25772 15.25% 15.25% # Class of executed instruction -system.cpu1.op_class::IntAlu 74368 44.00% 59.25% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.25% # Class of executed instruction -system.cpu1.op_class::MemRead 56548 33.46% 92.71% # Class of executed instruction -system.cpu1.op_class::MemWrite 12324 7.29% 100.00% # Class of executed instruction +system.cpu1.num_busy_cycles 452419.998260 # Number of busy cycles +system.cpu1.not_idle_fraction 0.869793 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.130207 # Percentage of idle cycles +system.cpu1.Branches 32668 # Number of branches fetched +system.cpu1.op_class::No_OpClass 23452 14.16% 14.16% # Class of executed instruction +system.cpu1.op_class::IntAlu 74986 45.28% 59.44% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.44% # Class of executed instruction +system.cpu1.op_class::MemRead 51906 31.34% 90.79% # Class of executed instruction +system.cpu1.op_class::MemWrite 15259 9.21% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 169012 # Class of executed instruction +system.cpu1.op_class::total 165603 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.995164 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 26990 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 899.666667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.035238 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 32753 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1129.413793 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.995164 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050772 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050772 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.035238 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050850 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050850 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 212815 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 212815 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 40655 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40655 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 12144 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 12144 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 52799 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 52799 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 52799 # number of overall hits -system.cpu1.dcache.overall_hits::total 52799 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 162 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 162 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses -system.cpu1.dcache.overall_misses::total 270 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2619475 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2619475 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1982498 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1982498 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 237000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4601973 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4601973 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4601973 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4601973 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40817 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40817 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 12252 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 12252 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 53069 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 53069 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 53069 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 53069 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003969 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003969 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008815 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008815 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005088 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005088 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005088 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005088 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4232.142857 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444 # average overall miss latency +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 227042 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 227042 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 41284 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41284 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 15082 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 15082 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 56366 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 56366 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 56366 # number of overall hits +system.cpu1.dcache.overall_hits::total 56366 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 156 # number of ReadReq misses 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WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 56631 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 56631 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 56631 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 56631 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003764 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007175 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.007175 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.833333 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004679 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004679 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004679 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004679 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18972.477064 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18972.477064 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4572.727273 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4572.727273 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,99 +470,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2358525 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2358525 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1818502 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1818502 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 153000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4177027 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4177027 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4177027 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4177027 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003969 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008815 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008815 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005088 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005088 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2732.142857 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2227000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2227000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 196500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 196500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4186000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4186000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4186000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4186000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003764 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007175 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007175 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.833333 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004679 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004679 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14275.641026 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14275.641026 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17972.477064 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17972.477064 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3572.727273 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3572.727273 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency 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Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128315 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.128315 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.699918 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128320 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.128320 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 169379 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 169379 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 168647 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 168647 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 168647 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 168647 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 168647 # number of overall hits -system.cpu1.icache.overall_hits::total 168647 # number of overall hits +system.cpu1.icache.tags.tag_accesses 165970 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 165970 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 165238 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 165238 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 165238 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 165238 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 165238 # number of overall hits +system.cpu1.icache.overall_hits::total 165238 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5333988 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5333988 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5333988 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5333988 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5333988 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5333988 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 169013 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 169013 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 169013 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 169013 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 169013 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 169013 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002166 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002166 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002166 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14573.737705 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14573.737705 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5351500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5351500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5351500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5351500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5351500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5351500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 165604 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 165604 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 165604 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 165604 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 165604 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 165604 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002210 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002210 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002210 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14621.584699 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14621.584699 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14621.584699 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14621.584699 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,158 +577,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4778012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4778012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4778012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4778012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4778012 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4778012 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4985500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4985500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4985500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4985500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4985500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4985500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 520075 # number of cpu cycles simulated +system.cpu2.numCycles 520146 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 164869 # Number of instructions committed -system.cpu2.committedOps 164869 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110069 # Number of integer alu accesses +system.cpu2.committedInsts 160598 # Number of instructions committed +system.cpu2.committedOps 160598 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 111601 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31409 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110069 # number of integer instructions +system.cpu2.num_conditional_control_insts 28506 # number of instructions that are conditional controls +system.cpu2.num_int_insts 111601 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 276820 # number of times the integer registers were read -system.cpu2.num_int_register_writes 105549 # number of times the integer registers were written +system.cpu2.num_int_register_reads 294560 # number of times the integer registers were read +system.cpu2.num_int_register_writes 113655 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 54829 # number of memory refs -system.cpu2.num_load_insts 40701 # Number of load instructions -system.cpu2.num_store_insts 14128 # Number of store instructions -system.cpu2.num_idle_cycles 67985.001739 # Number of idle cycles -system.cpu2.num_busy_cycles 452089.998261 # Number of busy cycles -system.cpu2.not_idle_fraction 0.869278 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.130722 # Percentage of idle cycles -system.cpu2.Branches 33062 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23842 14.46% 14.46% # Class of executed instruction -system.cpu2.op_class::IntAlu 74244 45.02% 59.48% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::MemRead 52687 31.95% 91.43% # Class of executed instruction -system.cpu2.op_class::MemWrite 14128 8.57% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 59264 # number of memory refs +system.cpu2.num_load_insts 41473 # Number of load instructions +system.cpu2.num_store_insts 17791 # Number of store instructions +system.cpu2.num_idle_cycles 67981.871041 # Number of idle cycles +system.cpu2.num_busy_cycles 452164.128959 # Number of busy cycles +system.cpu2.not_idle_fraction 0.869302 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.130698 # Percentage of idle cycles +system.cpu2.Branches 30158 # Number of branches fetched +system.cpu2.op_class::No_OpClass 20943 13.04% 13.04% # Class of executed instruction +system.cpu2.op_class::IntAlu 75009 46.70% 59.73% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.73% # Class of executed instruction +system.cpu2.op_class::MemRead 46887 29.19% 88.92% # Class of executed instruction +system.cpu2.op_class::MemWrite 17791 11.08% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 164901 # Class of executed instruction +system.cpu2.op_class::total 160630 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.767003 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30481 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.808310 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 37821 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1051.068966 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1304.172414 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.767003 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054232 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.054232 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.808310 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054313 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.054313 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 219531 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 219531 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 40534 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40534 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 13949 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 13949 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54483 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54483 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54483 # number of overall hits -system.cpu2.dcache.overall_hits::total 54483 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 159 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 159 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses -system.cpu2.dcache.overall_misses::total 267 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2767480 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2767480 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2022500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2022500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 237000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4789980 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4789980 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4789980 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4789980 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40693 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40693 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14057 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14057 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 54750 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 54750 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 54750 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 54750 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003907 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003907 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007683 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007683 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004877 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004877 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004877 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004877 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4232.142857 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17940 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17940 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17940 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17940 # average overall miss latency +system.cpu2.dcache.tags.tag_accesses 237265 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 237265 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 41314 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 41314 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 17614 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 17614 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 58928 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58928 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58928 # number of overall hits +system.cpu2.dcache.overall_hits::total 58928 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 151 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 261 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 261 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 261 # number of overall misses +system.cpu2.dcache.overall_misses::total 261 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2416500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2416500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2235500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2235500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 248000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 248000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4652000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4652000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4652000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4652000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41465 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41465 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 17724 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 17724 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 65 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 59189 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 59189 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 59189 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 59189 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003642 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003642 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006206 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006206 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.846154 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.846154 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004410 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004410 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004410 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004410 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20322.727273 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4509.090909 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4509.090909 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,99 +737,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2514020 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2514020 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1860500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1860500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 153000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4374520 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4374520 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4374520 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4374520 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003907 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003907 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007683 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007683 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004877 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004877 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2732.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2265500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2265500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2125500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2125500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4391000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4391000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4391000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4391000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003642 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003642 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006206 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006206 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.846154 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004410 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004410 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15003.311258 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15003.311258 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19322.727273 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19322.727273 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3509.090909 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3509.090909 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 70.145256 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164536 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 70.147178 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 160265 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 449.551913 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 437.882514 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.145256 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137002 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.137002 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.147178 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137006 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.137006 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165268 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165268 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 164536 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164536 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164536 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164536 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164536 # number of overall hits -system.cpu2.icache.overall_hits::total 164536 # number of overall hits +system.cpu2.icache.tags.tag_accesses 160997 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 160997 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 160265 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 160265 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 160265 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 160265 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 160265 # number of overall hits +system.cpu2.icache.overall_hits::total 160265 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7445997 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7445997 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7445997 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7445997 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7445997 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7445997 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 164902 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 164902 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 164902 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 164902 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 164902 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 164902 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 20344.254098 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 20344.254098 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7437500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7437500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7437500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7437500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7437500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7437500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 160631 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 160631 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 160631 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 160631 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 160631 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 160631 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002279 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002279 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002279 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002279 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002279 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002279 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20321.038251 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 20321.038251 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 20321.038251 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 20321.038251 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -844,158 +844,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6894003 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6894003 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6894003 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6894003 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6894003 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6894003 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7071500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7071500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7071500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7071500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7071500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7071500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002279 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002279 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002279 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19321.038251 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 520075 # number of cpu cycles simulated +system.cpu3.numCycles 520146 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167901 # Number of instructions committed -system.cpu3.committedOps 167901 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 110672 # Number of integer alu accesses +system.cpu3.committedInsts 175526 # Number of instructions committed +system.cpu3.committedOps 175526 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 107877 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 32621 # number of instructions that are conditional controls -system.cpu3.num_int_insts 110672 # number of integer instructions +system.cpu3.num_conditional_control_insts 37833 # number of instructions that are conditional controls +system.cpu3.num_int_insts 107877 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 274378 # number of times the integer registers were read -system.cpu3.num_int_register_writes 104026 # number of times the integer registers were written +system.cpu3.num_int_register_reads 242346 # number of times the integer registers were read +system.cpu3.num_int_register_writes 89400 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 54219 # number of memory refs -system.cpu3.num_load_insts 41000 # Number of load instructions -system.cpu3.num_store_insts 13219 # Number of store instructions -system.cpu3.num_idle_cycles 68239.001738 # Number of idle cycles -system.cpu3.num_busy_cycles 451835.998262 # Number of busy cycles -system.cpu3.not_idle_fraction 0.868790 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.131210 # Percentage of idle cycles -system.cpu3.Branches 34277 # Number of branches fetched -system.cpu3.op_class::No_OpClass 25056 14.92% 14.92% # Class of executed instruction -system.cpu3.op_class::IntAlu 74547 44.39% 59.31% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.31% # Class of executed instruction -system.cpu3.op_class::MemRead 55111 32.82% 92.13% # Class of executed instruction -system.cpu3.op_class::MemWrite 13219 7.87% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 46213 # number of memory refs +system.cpu3.num_load_insts 39592 # Number of load instructions +system.cpu3.num_store_insts 6621 # Number of store instructions +system.cpu3.num_idle_cycles 68237.870548 # Number of idle cycles +system.cpu3.num_busy_cycles 451908.129452 # Number of busy cycles +system.cpu3.not_idle_fraction 0.868810 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.131190 # Percentage of idle cycles +system.cpu3.Branches 39491 # Number of branches fetched +system.cpu3.op_class::No_OpClass 30262 17.24% 17.24% # Class of executed instruction +system.cpu3.op_class::IntAlu 73148 41.67% 58.90% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.90% # Class of executed instruction +system.cpu3.op_class::MemRead 65527 37.32% 96.23% # Class of executed instruction +system.cpu3.op_class::MemWrite 6621 3.77% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 167933 # Class of executed instruction +system.cpu3.op_class::total 175558 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 26.810589 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 28657 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 988.172414 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 26.732151 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 15554 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 518.466667 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.810589 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052364 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.052364 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.732151 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.052211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 217093 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 217093 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40832 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40832 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 13038 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 13038 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 53870 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 53870 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 53870 # number of overall hits -system.cpu3.dcache.overall_hits::total 53870 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 160 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 160 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2513476 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2513476 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2024000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2024000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 244500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 244500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4537476 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4537476 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4537476 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4537476 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 40992 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 40992 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 13146 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 13146 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 54138 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 54138 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 54138 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 54138 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003903 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003903 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008215 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008215 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.816901 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004950 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004950 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004950 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004950 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4215.517241 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4215.517241 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597 # average overall miss latency +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 185088 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 185088 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 39402 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 39402 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 6435 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 6435 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 45837 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 45837 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 45837 # number of overall hits +system.cpu3.dcache.overall_hits::total 45837 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 182 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 182 # number of ReadReq misses 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SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 46124 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 46124 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 46124 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 46124 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004598 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004598 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016055 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.016055 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.759494 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.759494 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006222 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006222 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006222 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006222 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4608.333333 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4608.333333 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1004,99 +1004,99 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2256524 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2256524 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1862000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1862000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 157500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 157500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4118524 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4118524 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4118524 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4118524 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003903 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003903 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008215 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008215 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2715.517241 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2715.517241 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 182 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 60 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 287 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 287 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3041000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3041000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1623500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1623500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 216500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 216500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4664500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4664500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4664500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4664500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004598 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004598 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016055 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016055 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.759494 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.759494 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.006222 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.006222 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16708.791209 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16708.791209 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15461.904762 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15461.904762 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3608.333333 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3608.333333 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 67.819588 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 167567 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 67.821849 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 175192 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 456.585831 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 477.362398 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.819588 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132460 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.132460 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.821849 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132465 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.132465 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 168301 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 168301 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 167567 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 167567 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 167567 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 167567 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 167567 # number of overall hits -system.cpu3.icache.overall_hits::total 167567 # number of overall hits +system.cpu3.icache.tags.tag_accesses 175926 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 175926 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 175192 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 175192 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 175192 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 175192 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 175192 # number of overall hits +system.cpu3.icache.overall_hits::total 175192 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5144490 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5144490 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5144490 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5144490 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5144490 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5144490 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167934 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167934 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167934 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167934 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167934 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167934 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002185 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002185 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002185 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002185 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002185 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002185 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14017.683924 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14017.683924 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14017.683924 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14017.683924 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5136500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5136500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5136500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5136500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5136500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5136500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 175559 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 175559 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 175559 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 175559 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 175559 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 175559 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002090 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002090 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002090 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002090 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002090 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002090 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13995.912807 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13995.912807 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13995.912807 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13995.912807 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1111,46 +1111,46 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4586010 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4586010 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4586010 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4586010 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4586010 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4586010 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002185 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002185 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002185 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12495.940054 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4769500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4769500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4769500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4769500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4769500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4769500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002090 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002090 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002090 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002090 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12995.912807 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12995.912807 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12995.912807 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.350598 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 349.351676 # Cycle average of tags in use +system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.890412 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.950361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.237281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.226273 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.814088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 47.344433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.154120 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.888026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.845603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.890425 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.950289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.237156 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.367865 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.832949 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 47.203910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.135421 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.888032 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.845628 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000722 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy @@ -1159,21 +1159,22 @@ system.l2c.tags.occ_task_id_blocks::1024 429 # Oc system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 15709 # Number of tag accesses -system.l2c.tags.data_accesses 15709 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.tags.tag_accesses 19677 # Number of tag accesses +system.l2c.tags.data_accesses 19677 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 302 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits @@ -1192,25 +1193,26 @@ system.l2c.overall_hits::cpu2.data 3 # nu system.l2c.overall_hits::cpu3.inst 358 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 64 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 64 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 372 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses @@ -1229,59 +1231,61 @@ system.l2c.overall_misses::cpu2.data 23 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 592 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14963000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3465000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 714500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 3356500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 420000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 103500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23584500 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 744000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 791500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 740000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7473000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14963000 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 735000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 797000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 744000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7473500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14964000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 740000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3341500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 453500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 19499000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 3465000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 105000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 419000 # number of ReadSharedReq miss cycles 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of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 14963000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 740000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 840000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 3341500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1216000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 453500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 848500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 31066000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14964000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 714500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 848000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 3356500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1211500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 843500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 31057500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 740000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 840000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 3341500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1216000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 453500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 848500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 31066000 # number of overall miss cycles system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 366 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 366 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 367 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1566 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 11 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 104 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses @@ -1300,15 +1304,6 @@ system.l2c.overall_accesses::cpu2.data 26 # nu system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses @@ -1319,6 +1314,16 @@ system.l2c.ReadExReq_miss_rate::cpu1.data 1 # m system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.237548 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.750000 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses @@ -1337,38 +1342,39 @@ system.l2c.overall_miss_rate::cpu2.data 0.884615 # mi system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52501.754386 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51035.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52445.312500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50888.888889 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 51750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52410 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52766.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52857.142857 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52626.760563 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53133.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52630.281690 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52505.263158 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52857.142857 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52210.937500 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 50388.888889 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 52416.666667 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 52500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 52500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 52375 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 52250 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 52480.769231 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 53000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52461.993243 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52857.142857 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 52210.937500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52869.565217 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52476.351351 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52505.263158 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency 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overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.038251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.640000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40510.465116 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40525.922078 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41107.142857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40785.714286 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 42642.857143 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 42500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 42500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43590.181818 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42500 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42519.774011 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 430 # Transaction distribution system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 272 # Transaction distribution system.membus.trans_dist::UpgradeResp 77 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) @@ -1565,26 +1573,28 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 914 # Request fanout histogram -system.membus.reqLayer0.occupancy 679142 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 665648 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2961502 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2948008 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2217 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2217 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4812 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 846 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5316 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) @@ -1594,8 +1604,8 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1029 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2921 # Request fanout histogram +system.toL2Bus.snoops 1037 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3986 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1606,29 +1616,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2921 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3986 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2921 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1466989 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 3986 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1998491 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 503996 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 503490 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 552488 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 431973 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 419983 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 550497 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 423980 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 412483 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 554490 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 428476 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 467954 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index e7443957c..4a69b5566 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.010140 # Number of seconds simulated -sim_ticks 10139920 # Number of ticks simulated -final_tick 10139920 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.010085 # Number of seconds simulated +sim_ticks 10084846 # Number of ticks simulated +final_tick 10084846 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 145167 # Simulator tick rate (ticks/s) -host_mem_usage 481408 # Number of bytes of host memory used -host_seconds 69.85 # Real time elapsed on the host +host_tick_rate 135609 # Simulator tick rate (ticks/s) +host_mem_usage 534216 # Number of bytes of host memory used +host_seconds 74.37 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39722368 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39722368 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14274816 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14274816 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 620662 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 620662 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 223044 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 223044 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 3917424201 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 3917424201 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1407783888 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1407783888 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 5325208088 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 5325208088 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 620666 # Number of read requests accepted -system.mem_ctrls.writeReqs 223044 # Number of write requests accepted -system.mem_ctrls.readBursts 620666 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 223044 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39325760 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 396864 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14138944 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39722624 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14274816 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 6201 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 2091 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39539520 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39539520 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14190848 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14190848 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 617805 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 617805 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 221732 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 221732 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 3920686543 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 3920686543 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1407145731 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1407145731 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 5327832274 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 5327832274 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 617810 # Number of read requests accepted +system.mem_ctrls.writeReqs 221732 # Number of write requests accepted +system.mem_ctrls.readBursts 617810 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 221732 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 39149376 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 390400 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14065216 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39539840 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14190848 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 6100 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 1940 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76321 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76908 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76950 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 77228 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 77214 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76769 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76576 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 76499 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76472 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76445 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76295 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76401 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76651 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76559 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76484 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 76402 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27303 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27584 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27647 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27851 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27807 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27671 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27568 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27490 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27622 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27185 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27442 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27653 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27274 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27861 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27499 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27233 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,29 +69,29 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 10139879 # Total gap between requests +system.mem_ctrls.totGap 10084812 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 620666 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 617810 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 223044 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 34202 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 67883 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 107442 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 137013 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 123761 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 83967 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 43765 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 16432 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 221732 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 33764 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 67305 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 107562 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 136575 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 123260 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 83360 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 43779 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 16105 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -131,35 +131,35 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 102 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 1701 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 5412 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 9478 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 12746 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 14568 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 15535 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 16087 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 16159 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 16083 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 15677 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 15094 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 14842 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 14767 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 14802 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 14952 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 15339 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 4340 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1928 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 791 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 311 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 122 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 100 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 1824 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 5451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 9639 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 12681 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 14370 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 15508 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 15925 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 16112 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 15973 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 15537 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 15061 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 14828 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 14675 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 14690 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 14838 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 15284 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 4187 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 1849 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 776 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 270 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 109 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -180,165 +180,168 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 335053 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 159.568976 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 125.655089 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 125.561192 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 136625 40.78% 40.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 126781 37.84% 78.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44480 13.28% 91.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 17048 5.09% 96.98% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6525 1.95% 98.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2297 0.69% 99.61% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 855 0.26% 99.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 301 0.09% 99.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 141 0.04% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 335053 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13793 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 44.545857 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 43.515478 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 9.590118 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-19 13 0.09% 0.09% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-23 63 0.46% 0.55% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-27 253 1.83% 2.39% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::28-31 644 4.67% 7.05% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-35 1374 9.96% 17.02% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-39 2023 14.67% 31.68% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-43 2256 16.36% 48.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::44-47 2260 16.39% 64.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-51 1885 13.67% 78.09% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::52-55 1286 9.32% 87.41% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-59 772 5.60% 93.01% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::60-63 480 3.48% 96.49% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-67 280 2.03% 98.52% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::68-71 112 0.81% 99.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-75 40 0.29% 99.62% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::76-79 38 0.28% 99.90% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-83 9 0.07% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::84-87 2 0.01% 99.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-91 2 0.01% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::112-115 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13793 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13793 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.016893 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.015738 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.203483 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13672 99.12% 99.12% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 53 0.38% 99.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 36 0.26% 99.77% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 22 0.16% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 9 0.07% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13793 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 29132870 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 40807705 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3072325 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 47.41 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 332248 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 160.163733 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 126.016641 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 126.021242 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 134990 40.63% 40.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 125717 37.84% 78.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 44100 13.27% 91.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17233 5.19% 96.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6597 1.99% 98.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2403 0.72% 99.64% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 797 0.24% 99.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 271 0.08% 99.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 140 0.04% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 332248 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13719 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 44.587579 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 43.567132 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 9.560965 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-15 1 0.01% 0.01% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-19 10 0.07% 0.08% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-23 52 0.38% 0.46% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-27 254 1.85% 2.31% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::28-31 679 4.95% 7.26% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-35 1331 9.70% 16.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-39 1929 14.06% 31.02% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-43 2366 17.25% 48.27% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::44-47 2213 16.13% 64.40% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-51 1878 13.69% 78.09% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::52-55 1269 9.25% 87.34% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-59 815 5.94% 93.28% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::60-63 445 3.24% 96.52% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-67 259 1.89% 98.41% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::68-71 126 0.92% 99.33% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-75 51 0.37% 99.70% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::76-79 25 0.18% 99.88% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-83 8 0.06% 99.94% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::84-87 3 0.02% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-91 2 0.01% 99.98% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::92-95 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-115 2 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 13719 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13719 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.019316 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.017844 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.231611 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13593 99.08% 99.08% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 51 0.37% 99.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 36 0.26% 99.72% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 22 0.16% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 11 0.08% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 4 0.03% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 2 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13719 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 28969420 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 40591891 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3058545 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 47.36 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 66.41 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 3878.31 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1394.38 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 3917.45 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1407.78 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 66.36 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 3882.00 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1394.69 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 3920.72 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1407.15 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 41.19 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 30.30 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 10.89 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 5.50 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.47 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 285829 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 214496 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 46.52 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.08 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 12.02 # Average gap between requests -system.mem_ctrls.pageHitRate 59.89 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 2532486600 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 1406937000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7666913280 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2290011264 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 662145120 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 6909126408 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 21943800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 21489563472 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 2119.780745 # Core power per rank (mW) +system.mem_ctrls.busUtil 41.22 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 30.33 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 10.90 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 5.49 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 26.46 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 285743 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 213481 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 46.71 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.13 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 12.01 # Average gap between requests +system.mem_ctrls.pageHitRate 60.04 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 2511379080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1395210600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7632905280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2278067328 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 658585200 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 6872035140 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 21818400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 21370001028 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2119.367180 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 20 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 338520 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 336700 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 9799109 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 9746493 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 662145120 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 219079728 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 5890395600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 6771620448 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.969581 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 9799112 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 338520 # Time in different power states +system.mem_ctrls_1.refreshEnergy 658585200 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 217901880 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5858727600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 6735214680 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.969572 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9746430 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 336700 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 99636 # number of read accesses completed -system.cpu0.num_writes 55756 # number of write accesses completed -system.cpu1.num_reads 99812 # number of read accesses completed -system.cpu1.num_writes 55738 # number of write accesses completed -system.cpu2.num_reads 99728 # number of read accesses completed -system.cpu2.num_writes 55111 # number of write accesses completed -system.cpu3.num_reads 99867 # number of read accesses completed -system.cpu3.num_writes 55484 # number of write accesses completed -system.cpu4.num_reads 99170 # number of read accesses completed -system.cpu4.num_writes 55261 # number of write accesses completed -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 55396 # number of write accesses completed -system.cpu6.num_reads 99231 # number of read accesses completed -system.cpu6.num_writes 55296 # number of write accesses completed -system.cpu7.num_reads 99263 # number of read accesses completed -system.cpu7.num_writes 55610 # number of write accesses completed +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 54904 # number of write accesses completed +system.cpu1.num_reads 98267 # number of read accesses completed +system.cpu1.num_writes 54988 # number of write accesses completed +system.cpu2.num_reads 99798 # number of read accesses completed +system.cpu2.num_writes 55147 # number of write accesses completed +system.cpu3.num_reads 98142 # number of read accesses completed +system.cpu3.num_writes 54997 # number of write accesses completed +system.cpu4.num_reads 99042 # number of read accesses completed +system.cpu4.num_writes 55133 # number of write accesses completed +system.cpu5.num_reads 99461 # number of read accesses completed +system.cpu5.num_writes 55195 # number of write accesses completed +system.cpu6.num_reads 99533 # number of read accesses completed +system.cpu6.num_writes 55095 # number of write accesses completed +system.cpu7.num_reads 99126 # number of read accesses completed +system.cpu7.num_writes 55305 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 2048 # delay histogram for all message system.ruby.delayHist::max_bucket 20479 # delay histogram for all message -system.ruby.delayHist::samples 4993549 # delay histogram for all message -system.ruby.delayHist::mean 200.268799 # delay histogram for all message -system.ruby.delayHist::stdev 576.702096 # delay histogram for all message -system.ruby.delayHist | 4855621 97.24% 97.24% | 131487 2.63% 99.87% | 6055 0.12% 99.99% | 370 0.01% 100.00% | 13 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 4993549 # delay histogram for all message +system.ruby.delayHist::samples 4974912 # delay histogram for all message +system.ruby.delayHist::mean 203.140608 # delay histogram for all message +system.ruby.delayHist::stdev 582.111066 # delay histogram for all message +system.ruby.delayHist | 4834308 97.17% 97.17% | 133920 2.69% 99.87% | 6363 0.13% 99.99% | 304 0.01% 100.00% | 15 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 4974912 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 626470 -system.ruby.outstanding_req_hist::mean 15.998466 -system.ruby.outstanding_req_hist::gmean 15.997202 -system.ruby.outstanding_req_hist::stdev 0.125833 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 17 0.00% 0.02% | 626349 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 626470 +system.ruby.outstanding_req_hist::samples 623553 +system.ruby.outstanding_req_hist::mean 15.998456 +system.ruby.outstanding_req_hist::gmean 15.997185 +system.ruby.outstanding_req_hist::stdev 0.126140 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 19 0.00% 0.02% | 623430 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 623553 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 626342 -system.ruby.latency_hist::mean 2071.919100 -system.ruby.latency_hist::gmean 1588.311546 -system.ruby.latency_hist::stdev 1228.835712 -system.ruby.latency_hist | 165846 26.48% 26.48% | 150976 24.10% 50.58% | 148385 23.69% 74.27% | 132690 21.18% 95.46% | 28063 4.48% 99.94% | 382 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 626342 +system.ruby.latency_hist::samples 623425 +system.ruby.latency_hist::mean 2070.305650 +system.ruby.latency_hist::gmean 1615.472448 +system.ruby.latency_hist::stdev 1197.783939 +system.ruby.latency_hist | 158292 25.39% 25.39% | 157674 25.29% 50.68% | 153146 24.57% 75.25% | 128715 20.65% 95.89% | 25317 4.06% 99.95% | 281 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 623425 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 9 +system.ruby.hit_latency_hist::samples 8 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 9 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 8 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 626333 -system.ruby.miss_latency_hist::mean 2071.948829 -system.ruby.miss_latency_hist::gmean 1588.454694 -system.ruby.miss_latency_hist::stdev 1228.819513 -system.ruby.miss_latency_hist | 165837 26.48% 26.48% | 150976 24.10% 50.58% | 148385 23.69% 74.27% | 132690 21.19% 95.46% | 28063 4.48% 99.94% | 382 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626333 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 2 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78425 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78427 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 623417 +system.ruby.miss_latency_hist::mean 2070.332179 +system.ruby.miss_latency_hist::gmean 1615.602823 +system.ruby.miss_latency_hist::stdev 1197.768731 +system.ruby.miss_latency_hist | 158284 25.39% 25.39% | 157674 25.29% 50.68% | 153146 24.57% 75.25% | 128715 20.65% 95.89% | 25317 4.06% 99.95% | 281 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 623417 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78229 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78230 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -351,9 +354,9 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78414 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78415 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 2 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 77517 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77519 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -366,9 +369,9 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl2.L1Dcache.demand_hits 3 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78001 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78004 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78390 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78391 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -381,9 +384,9 @@ system.ruby.l1_cntrl2.prefetcher.hits 0 # nu system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78494 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78495 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 77490 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 77490 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -397,8 +400,8 @@ system.ruby.l1_cntrl3.prefetcher.partial_hits 0 system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl4.L1Dcache.demand_hits 2 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78222 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78224 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Dcache.demand_misses 77712 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77714 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -411,9 +414,9 @@ system.ruby.l1_cntrl4.prefetcher.hits 0 # nu system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl5.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78386 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78386 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 2 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 77950 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77952 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -427,8 +430,8 @@ system.ruby.l1_cntrl5.prefetcher.partial_hits 0 system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl6.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78056 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78056 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78084 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78084 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -442,8 +445,8 @@ system.ruby.l1_cntrl6.prefetcher.partial_hits 0 system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl7.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78357 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78357 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78070 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78070 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -456,541 +459,541 @@ system.ruby.l1_cntrl7.prefetcher.hits 0 # nu system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l2_cntrl0.L2cache.demand_hits 21 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 626317 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 626338 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 29 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 623394 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 623423 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers00.percent_links_utilized 4.037004 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+system.ruby.network.routers08.throttle0.msg_count.Response_Control::2 618261 +system.ruby.network.routers08.throttle0.msg_count.Writeback_Data::0 117821 +system.ruby.network.routers08.throttle0.msg_count.Writeback_Data::1 415374 +system.ruby.network.routers08.throttle0.msg_count.Writeback_Control::0 209365 +system.ruby.network.routers08.throttle0.msg_bytes.Control::0 4987536 +system.ruby.network.routers08.throttle0.msg_bytes.Response_Data::1 44571744 +system.ruby.network.routers08.throttle0.msg_bytes.Response_Control::1 6481648 +system.ruby.network.routers08.throttle0.msg_bytes.Response_Control::2 4946088 +system.ruby.network.routers08.throttle0.msg_bytes.Writeback_Data::0 8483112 +system.ruby.network.routers08.throttle0.msg_bytes.Writeback_Data::1 29906928 +system.ruby.network.routers08.throttle0.msg_bytes.Writeback_Control::0 1674920 +system.ruby.network.routers08.throttle1.link_utilization 47.120819 +system.ruby.network.routers08.throttle1.msg_count.Control::0 617810 +system.ruby.network.routers08.throttle1.msg_count.Request_Control::2 606978 +system.ruby.network.routers08.throttle1.msg_count.Response_Data::1 839566 +system.ruby.network.routers08.throttle1.msg_count.Response_Control::1 723243 +system.ruby.network.routers08.throttle1.msg_bytes.Control::0 4942480 +system.ruby.network.routers08.throttle1.msg_bytes.Request_Control::2 4855824 +system.ruby.network.routers08.throttle1.msg_bytes.Response_Data::1 60448752 +system.ruby.network.routers08.throttle1.msg_bytes.Response_Control::1 5785944 +system.ruby.network.routers09.throttle0.link_utilization 14.920739 +system.ruby.network.routers09.throttle0.msg_count.Control::0 617810 +system.ruby.network.routers09.throttle0.msg_count.Response_Data::1 221732 +system.ruby.network.routers09.throttle0.msg_count.Response_Control::1 396069 +system.ruby.network.routers09.throttle0.msg_bytes.Control::0 4942480 +system.ruby.network.routers09.throttle0.msg_bytes.Response_Data::1 15964704 +system.ruby.network.routers09.throttle0.msg_bytes.Response_Control::1 3168552 +system.ruby.network.routers09.throttle1.link_utilization 30.630344 +system.ruby.network.routers09.throttle1.msg_count.Response_Data::1 617805 +system.ruby.network.routers09.throttle1.msg_count.Response_Control::1 617801 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::1 44481960 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Control::1 4942408 +system.ruby.network.routers10.throttle0.link_utilization 4.073126 +system.ruby.network.routers10.throttle0.msg_count.Request_Control::2 76562 +system.ruby.network.routers10.throttle0.msg_count.Response_Data::1 78227 +system.ruby.network.routers10.throttle0.msg_count.Response_Control::1 40932 +system.ruby.network.routers10.throttle0.msg_bytes.Request_Control::2 612496 +system.ruby.network.routers10.throttle0.msg_bytes.Response_Data::1 5632344 +system.ruby.network.routers10.throttle0.msg_bytes.Response_Control::1 327456 +system.ruby.network.routers10.throttle1.link_utilization 4.036477 +system.ruby.network.routers10.throttle1.msg_count.Request_Control::2 76035 +system.ruby.network.routers10.throttle1.msg_count.Response_Data::1 77515 +system.ruby.network.routers10.throttle1.msg_count.Response_Control::1 40475 +system.ruby.network.routers10.throttle1.msg_bytes.Request_Control::2 608280 +system.ruby.network.routers10.throttle1.msg_bytes.Response_Data::1 5581080 +system.ruby.network.routers10.throttle1.msg_bytes.Response_Control::1 323800 +system.ruby.network.routers10.throttle2.link_utilization 4.083726 +system.ruby.network.routers10.throttle2.msg_count.Request_Control::2 76800 +system.ruby.network.routers10.throttle2.msg_count.Response_Data::1 78387 +system.ruby.network.routers10.throttle2.msg_count.Response_Control::1 41392 +system.ruby.network.routers10.throttle2.msg_bytes.Request_Control::2 614400 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::1 5643864 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Control::1 331136 +system.ruby.network.routers10.throttle3.link_utilization 4.034132 +system.ruby.network.routers10.throttle3.msg_count.Request_Control::2 75829 +system.ruby.network.routers10.throttle3.msg_count.Response_Data::1 77486 +system.ruby.network.routers10.throttle3.msg_count.Response_Control::1 40469 +system.ruby.network.routers10.throttle3.msg_bytes.Request_Control::2 606632 +system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::1 5578992 +system.ruby.network.routers10.throttle3.msg_bytes.Response_Control::1 323752 +system.ruby.network.routers10.throttle4.link_utilization 4.046690 +system.ruby.network.routers10.throttle4.msg_count.Request_Control::2 76225 +system.ruby.network.routers10.throttle4.msg_count.Response_Data::1 77710 +system.ruby.network.routers10.throttle4.msg_count.Response_Control::1 40595 +system.ruby.network.routers10.throttle4.msg_bytes.Request_Control::2 609800 +system.ruby.network.routers10.throttle4.msg_bytes.Response_Data::1 5595120 +system.ruby.network.routers10.throttle4.msg_bytes.Response_Control::1 324760 +system.ruby.network.routers10.throttle5.link_utilization 4.060558 +system.ruby.network.routers10.throttle5.msg_count.Request_Control::2 76384 +system.ruby.network.routers10.throttle5.msg_count.Response_Data::1 77947 +system.ruby.network.routers10.throttle5.msg_count.Response_Control::1 41095 +system.ruby.network.routers10.throttle5.msg_bytes.Request_Control::2 611072 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::1 5612184 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::1 328760 +system.ruby.network.routers10.throttle6.link_utilization 4.066919 +system.ruby.network.routers10.throttle6.msg_count.Request_Control::2 76485 +system.ruby.network.routers10.throttle6.msg_count.Response_Data::1 78080 +system.ruby.network.routers10.throttle6.msg_count.Response_Control::1 41080 +system.ruby.network.routers10.throttle6.msg_bytes.Request_Control::2 611880 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::1 5621760 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::1 328640 +system.ruby.network.routers10.throttle7.link_utilization 4.066701 +system.ruby.network.routers10.throttle7.msg_count.Request_Control::2 76489 +system.ruby.network.routers10.throttle7.msg_count.Response_Data::1 78066 +system.ruby.network.routers10.throttle7.msg_count.Response_Control::1 41158 +system.ruby.network.routers10.throttle7.msg_bytes.Request_Control::2 611912 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::1 5620752 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::1 329264 +system.ruby.network.routers10.throttle8.link_utilization 62.626117 +system.ruby.network.routers10.throttle8.msg_count.Control::0 623442 +system.ruby.network.routers10.throttle8.msg_count.Response_Data::1 619052 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::1 810206 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::2 618261 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::0 117821 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::1 415374 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0 209365 +system.ruby.network.routers10.throttle8.msg_bytes.Control::0 4987536 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::1 44571744 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::1 6481648 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::2 4946088 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::0 8483112 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::1 29906928 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 1674920 +system.ruby.network.routers10.throttle9.link_utilization 14.920739 +system.ruby.network.routers10.throttle9.msg_count.Control::0 617810 +system.ruby.network.routers10.throttle9.msg_count.Response_Data::1 221732 +system.ruby.network.routers10.throttle9.msg_count.Response_Control::1 396069 +system.ruby.network.routers10.throttle9.msg_bytes.Control::0 4942480 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1 15964704 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3168552 system.ruby.delayVCHist.vnet_0::bucket_size 2048 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 20479 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 1574320 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 631.193011 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 885.262867 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1436392 91.24% 91.24% | 131487 8.35% 99.59% | 6055 0.38% 99.98% | 370 0.02% 100.00% | 13 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 1574320 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 1568858 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 640.119386 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 891.952930 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 1428254 91.04% 91.04% | 133920 8.54% 99.57% | 6363 0.41% 99.98% | 304 0.02% 100.00% | 15 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 1568858 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 8 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 79 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 2805873 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 2.261817 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 4.246713 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 2397962 85.46% 85.46% | 340890 12.15% 97.61% | 58848 2.10% 99.71% | 7632 0.27% 99.98% | 517 0.02% 100.00% | 24 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 2805873 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 2795245 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 2.269717 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 4.251012 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 2388876 85.46% 85.46% | 339265 12.14% 97.60% | 59099 2.11% 99.71% | 7462 0.27% 99.98% | 530 0.02% 100.00% | 12 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 2795245 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 613356 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.009639 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.138885 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 610408 99.52% 99.52% | 0 0.00% 99.52% | 2940 0.48% 100.00% | 0 0.00% 100.00% | 8 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 613356 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 610809 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.009522 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.137860 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 607905 99.52% 99.52% | 0 0.00% 99.52% | 2900 0.47% 100.00% | 0 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 610809 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 1024 system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 402616 -system.ruby.LD.latency_hist::mean 2072.049427 -system.ruby.LD.latency_hist::gmean 1588.762336 -system.ruby.LD.latency_hist::stdev 1228.569503 -system.ruby.LD.latency_hist | 106527 26.46% 26.46% | 97059 24.11% 50.57% | 95427 23.70% 74.27% | 85360 21.20% 95.47% | 17986 4.47% 99.94% | 257 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 402616 +system.ruby.LD.latency_hist::samples 401087 +system.ruby.LD.latency_hist::mean 2069.126818 +system.ruby.LD.latency_hist::gmean 1613.676021 +system.ruby.LD.latency_hist::stdev 1198.428887 +system.ruby.LD.latency_hist | 102022 25.44% 25.44% | 101345 25.27% 50.70% | 98349 24.52% 75.22% | 82950 20.68% 95.91% | 16249 4.05% 99.96% | 172 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 401087 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 6 +system.ruby.LD.hit_latency_hist::samples 5 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 6 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 5 system.ruby.LD.miss_latency_hist::bucket_size 1024 system.ruby.LD.miss_latency_hist::max_bucket 10239 -system.ruby.LD.miss_latency_hist::samples 402610 -system.ruby.LD.miss_latency_hist::mean 2072.080261 -system.ruby.LD.miss_latency_hist::gmean 1588.910848 -system.ruby.LD.miss_latency_hist::stdev 1228.552693 -system.ruby.LD.miss_latency_hist | 106521 26.46% 26.46% | 97059 24.11% 50.57% | 95427 23.70% 74.27% | 85360 21.20% 95.47% | 17986 4.47% 99.94% | 257 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 402610 +system.ruby.LD.miss_latency_hist::samples 401082 +system.ruby.LD.miss_latency_hist::mean 2069.152575 +system.ruby.LD.miss_latency_hist::gmean 1613.802512 +system.ruby.LD.miss_latency_hist::stdev 1198.414154 +system.ruby.LD.miss_latency_hist | 102017 25.44% 25.44% | 101345 25.27% 50.70% | 98349 24.52% 75.22% | 82950 20.68% 95.91% | 16249 4.05% 99.96% | 172 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 401082 system.ruby.ST.latency_hist::bucket_size 1024 system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 223726 -system.ruby.ST.latency_hist::mean 2071.684565 -system.ruby.ST.latency_hist::gmean 1587.500627 -system.ruby.ST.latency_hist::stdev 1229.317345 -system.ruby.ST.latency_hist | 59319 26.51% 26.51% | 53917 24.10% 50.61% | 52958 23.67% 74.28% | 47330 21.16% 95.44% | 10077 4.50% 99.94% | 125 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223726 +system.ruby.ST.latency_hist::samples 222338 +system.ruby.ST.latency_hist::mean 2072.432207 +system.ruby.ST.latency_hist::gmean 1618.718174 +system.ruby.ST.latency_hist::stdev 1196.619363 +system.ruby.ST.latency_hist | 56270 25.31% 25.31% | 56329 25.33% 50.64% | 54797 24.65% 75.29% | 45765 20.58% 95.87% | 9068 4.08% 99.95% | 109 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 222338 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 system.ruby.ST.hit_latency_hist::samples 3 @@ -1000,215 +1003,213 @@ system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | system.ruby.ST.hit_latency_hist::total 3 system.ruby.ST.miss_latency_hist::bucket_size 1024 system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 223723 -system.ruby.ST.miss_latency_hist::mean 2071.712305 -system.ruby.ST.miss_latency_hist::gmean 1587.634133 -system.ruby.ST.miss_latency_hist::stdev 1229.302246 -system.ruby.ST.miss_latency_hist | 59316 26.51% 26.51% | 53917 24.10% 50.61% | 52958 23.67% 74.28% | 47330 21.16% 95.44% | 10077 4.50% 99.94% | 125 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223723 -system.ruby.Directory_Controller.Fetch 620666 0.00% 0.00% -system.ruby.Directory_Controller.Data 223044 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 620662 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 223044 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 397614 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 620666 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 223044 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 397614 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 620662 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 223044 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50387 12.51% 12.51% | 50364 12.51% 25.02% | 50179 12.46% 37.49% | 50465 12.53% 50.02% | 50375 12.51% 62.53% | 50436 12.53% 75.06% | 50129 12.45% 87.51% | 50302 12.49% 100.00% -system.ruby.L1Cache_Controller.Load::total 402637 -system.ruby.L1Cache_Controller.Store | 28042 12.53% 12.53% | 28053 12.54% 25.07% | 27828 12.44% 37.51% | 28030 12.53% 50.04% | 27852 12.45% 62.48% | 27954 12.49% 74.98% | 27928 12.48% 87.46% | 28057 12.54% 100.00% -system.ruby.L1Cache_Controller.Store::total 223744 -system.ruby.L1Cache_Controller.Inv | 76503 12.54% 12.54% | 76387 12.52% 25.05% | 75991 12.45% 37.51% | 76469 12.53% 50.04% | 76247 12.49% 62.53% | 76392 12.52% 75.05% | 76025 12.46% 87.51% | 76209 12.49% 100.00% -system.ruby.L1Cache_Controller.Inv::total 610223 -system.ruby.L1Cache_Controller.L1_Replacement | 552329 12.49% 12.49% | 554080 12.53% 25.02% | 551001 12.46% 37.48% | 553019 12.51% 49.99% | 552775 12.50% 62.49% | 553813 12.53% 75.02% | 551589 12.47% 87.49% | 552978 12.51% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 4421584 -system.ruby.L1Cache_Controller.Fwd_GETX | 235 12.95% 12.95% | 233 12.84% 25.80% | 206 11.36% 37.16% | 229 12.62% 49.78% | 229 12.62% 62.40% | 224 12.35% 74.75% | 227 12.51% 87.27% | 231 12.73% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1814 -system.ruby.L1Cache_Controller.Fwd_GETS | 155 11.75% 11.75% | 179 13.57% 25.32% | 158 11.98% 37.30% | 167 12.66% 49.96% | 159 12.05% 62.02% | 186 14.10% 76.12% | 154 11.68% 87.79% | 161 12.21% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 1319 -system.ruby.L1Cache_Controller.Data | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Data::total 10 -system.ruby.L1Cache_Controller.Data_Exclusive | 49564 12.51% 12.51% | 49570 12.51% 25.02% | 49411 12.47% 37.49% | 49662 12.53% 50.02% | 49589 12.51% 62.53% | 49661 12.53% 75.07% | 49353 12.45% 87.52% | 49453 12.48% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 396263 -system.ruby.L1Cache_Controller.DataS_fromL1 | 167 12.66% 12.66% | 162 12.28% 24.94% | 164 12.43% 37.38% | 179 13.57% 50.95% | 170 12.89% 63.84% | 150 11.37% 75.21% | 153 11.60% 86.81% | 174 13.19% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 1319 -system.ruby.L1Cache_Controller.Data_all_Acks | 28690 12.54% 12.54% | 28678 12.54% 25.08% | 28423 12.43% 37.51% | 28648 12.52% 50.03% | 28457 12.44% 62.47% | 28571 12.49% 74.96% | 28547 12.48% 87.44% | 28727 12.56% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 228741 -system.ruby.L1Cache_Controller.Ack | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Ack::total 10 -system.ruby.L1Cache_Controller.Ack_all | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 10 -system.ruby.L1Cache_Controller.WB_Ack | 40897 12.52% 12.52% | 40967 12.54% 25.06% | 40490 12.39% 37.45% | 41087 12.58% 50.03% | 40664 12.45% 62.48% | 41053 12.57% 75.05% | 40626 12.44% 87.48% | 40894 12.52% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 326678 -system.ruby.L1Cache_Controller.NP.Load | 50378 12.51% 12.51% | 50348 12.51% 25.02% | 50170 12.46% 37.48% | 50455 12.53% 50.02% | 50362 12.51% 62.53% | 50427 12.53% 75.06% | 50123 12.45% 87.51% | 50292 12.49% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 402555 -system.ruby.L1Cache_Controller.NP.Store | 28035 12.53% 12.53% | 28046 12.54% 25.07% | 27823 12.44% 37.51% | 28023 12.53% 50.04% | 27848 12.45% 62.49% | 27949 12.49% 74.98% | 27917 12.48% 87.46% | 28052 12.54% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 223693 -system.ruby.L1Cache_Controller.NP.Inv | 220 12.34% 12.34% | 229 12.84% 25.18% | 209 11.72% 36.90% | 233 13.07% 49.97% | 235 13.18% 63.15% | 247 13.85% 77.01% | 202 11.33% 88.33% | 208 11.67% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 1783 -system.ruby.L1Cache_Controller.I.Load | 7 10.94% 10.94% | 14 21.88% 32.81% | 4 6.25% 39.06% | 10 15.62% 54.69% | 9 14.06% 68.75% | 6 9.38% 78.12% | 6 9.38% 87.50% | 8 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 64 -system.ruby.L1Cache_Controller.I.Store | 5 11.63% 11.63% | 6 13.95% 25.58% | 4 9.30% 34.88% | 6 13.95% 48.84% | 3 6.98% 55.81% | 4 9.30% 65.12% | 10 23.26% 88.37% | 5 11.63% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 43 -system.ruby.L1Cache_Controller.I.L1_Replacement | 37358 12.52% 12.52% | 37278 12.50% 25.02% | 37354 12.52% 37.54% | 37224 12.48% 50.02% | 37375 12.53% 62.54% | 37164 12.46% 75.00% | 37269 12.49% 87.49% | 37314 12.51% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 298336 -system.ruby.L1Cache_Controller.S.Inv | 693 12.90% 12.90% | 679 12.64% 25.54% | 642 11.95% 37.48% | 666 12.40% 49.88% | 649 12.08% 61.96% | 646 12.02% 73.98% | 661 12.30% 86.28% | 737 13.72% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 5373 -system.ruby.L1Cache_Controller.S.L1_Replacement | 154 13.01% 13.01% | 143 12.08% 25.08% | 142 11.99% 37.08% | 159 13.43% 50.51% | 164 13.85% 64.36% | 153 12.92% 77.28% | 139 11.74% 89.02% | 130 10.98% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1184 -system.ruby.L1Cache_Controller.E.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 60.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 5 -system.ruby.L1Cache_Controller.E.Store | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 3 -system.ruby.L1Cache_Controller.E.Inv | 23423 12.54% 12.54% | 23271 12.45% 24.99% | 23422 12.53% 37.52% | 23280 12.46% 49.98% | 23423 12.54% 62.52% | 23370 12.51% 75.03% | 23365 12.50% 87.53% | 23299 12.47% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 186853 -system.ruby.L1Cache_Controller.E.L1_Replacement | 26089 12.49% 12.49% | 26232 12.55% 25.04% | 25939 12.41% 37.45% | 26323 12.60% 50.05% | 26112 12.50% 62.55% | 26240 12.56% 75.11% | 25933 12.41% 87.52% | 26081 12.48% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 208949 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 45 11.25% 11.25% | 58 14.50% 25.75% | 43 10.75% 36.50% | 53 13.25% 49.75% | 43 10.75% 60.50% | 45 11.25% 71.75% | 50 12.50% 84.25% | 63 15.75% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 400 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 6 10.71% 10.71% | 8 14.29% 25.00% | 7 12.50% 37.50% | 5 8.93% 46.43% | 10 17.86% 64.29% | 6 10.71% 75.00% | 5 8.93% 83.93% | 9 16.07% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 56 -system.ruby.L1Cache_Controller.M.Load | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 1 -system.ruby.L1Cache_Controller.M.Inv | 13143 12.49% 12.49% | 13204 12.55% 25.04% | 13192 12.54% 37.57% | 13169 12.51% 50.09% | 13209 12.55% 62.64% | 13024 12.38% 75.01% | 13141 12.49% 87.50% | 13152 12.50% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 105234 -system.ruby.L1Cache_Controller.M.L1_Replacement | 14808 12.58% 12.58% | 14737 12.52% 25.09% | 14554 12.36% 37.45% | 14768 12.54% 49.99% | 14555 12.36% 62.36% | 14815 12.58% 74.94% | 14695 12.48% 87.42% | 14815 12.58% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 117747 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 28 10.57% 10.57% | 45 16.98% 27.55% | 23 8.68% 36.23% | 29 10.94% 47.17% | 27 10.19% 57.36% | 50 18.87% 76.23% | 29 10.94% 87.17% | 34 12.83% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 265 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 60 12.50% 12.50% | 65 13.54% 26.04% | 56 11.67% 37.71% | 64 13.33% 51.04% | 59 12.29% 63.33% | 62 12.92% 76.25% | 60 12.50% 88.75% | 54 11.25% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 480 -system.ruby.L1Cache_Controller.IS.Inv | 40 12.27% 12.27% | 42 12.88% 25.15% | 42 12.88% 38.04% | 43 13.19% 51.23% | 36 11.04% 62.27% | 40 12.27% 74.54% | 41 12.58% 87.12% | 42 12.88% 100.00% -system.ruby.L1Cache_Controller.IS.Inv::total 326 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 304582 12.48% 12.48% | 306242 12.55% 25.03% | 304848 12.49% 37.52% | 305151 12.51% 50.03% | 305139 12.50% 62.53% | 305447 12.52% 75.05% | 304421 12.48% 87.53% | 304369 12.47% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2440199 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49564 12.51% 12.51% | 49570 12.51% 25.02% | 49411 12.47% 37.49% | 49662 12.53% 50.02% | 49589 12.51% 62.53% | 49661 12.53% 75.07% | 49353 12.45% 87.52% | 49453 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 396263 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 167 12.66% 12.66% | 162 12.28% 24.94% | 164 12.43% 37.38% | 179 13.57% 50.95% | 170 12.89% 63.84% | 150 11.37% 75.21% | 153 11.60% 86.81% | 174 13.19% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1319 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 614 13.06% 13.06% | 587 12.48% 25.54% | 557 11.85% 37.39% | 577 12.27% 49.66% | 574 12.21% 61.87% | 581 12.36% 74.22% | 582 12.38% 86.60% | 630 13.40% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4702 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 169338 12.50% 12.50% | 169448 12.50% 25.00% | 168164 12.41% 37.41% | 169394 12.50% 49.91% | 169430 12.50% 62.41% | 169994 12.54% 74.96% | 169132 12.48% 87.44% | 170269 12.56% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1355169 -system.ruby.L1Cache_Controller.IM.Data | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 10 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 28036 12.53% 12.53% | 28049 12.54% 25.07% | 27824 12.44% 37.51% | 28028 12.53% 50.04% | 27847 12.45% 62.48% | 27950 12.49% 74.98% | 27924 12.48% 87.46% | 28055 12.54% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 223713 -system.ruby.L1Cache_Controller.SM.Ack | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 10 -system.ruby.L1Cache_Controller.SM.Ack_all | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 10 -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 40 12.27% 12.27% | 42 12.88% 25.15% | 42 12.88% 38.04% | 43 13.19% 51.23% | 36 11.04% 62.27% | 40 12.27% 74.54% | 41 12.58% 87.12% | 42 12.88% 100.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 326 -system.ruby.L1Cache_Controller.M_I.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.M_I.Load::total 2 -system.ruby.L1Cache_Controller.M_I.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_I.Store::total 1 -system.ruby.L1Cache_Controller.M_I.Inv | 38961 12.55% 12.55% | 38942 12.54% 25.09% | 38456 12.39% 37.48% | 39054 12.58% 50.06% | 38676 12.46% 62.51% | 39041 12.57% 75.09% | 38589 12.43% 87.52% | 38751 12.48% 100.00% -system.ruby.L1Cache_Controller.M_I.Inv::total 310470 -system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 162 14.10% 14.10% | 130 11.31% 25.41% | 140 12.18% 37.60% | 147 12.79% 50.39% | 159 13.84% 64.23% | 129 11.23% 75.46% | 148 12.88% 88.34% | 134 11.66% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1149 -system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 89 11.37% 11.37% | 106 13.54% 24.90% | 95 12.13% 37.04% | 98 12.52% 49.55% | 90 11.49% 61.05% | 118 15.07% 76.12% | 89 11.37% 87.48% | 98 12.52% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 783 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 1685 11.79% 11.79% | 1791 12.53% 24.32% | 1802 12.61% 36.93% | 1792 12.54% 49.46% | 1742 12.19% 61.65% | 1766 12.36% 74.01% | 1802 12.61% 86.62% | 1913 13.38% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 14293 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 1 10.00% 10.00% | 2 20.00% 30.00% | 2 20.00% 50.00% | 0 0.00% 50.00% | 2 20.00% 70.00% | 2 20.00% 90.00% | 0 0.00% 90.00% | 1 10.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 10 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::samples 222335 +system.ruby.ST.miss_latency_hist::mean 2072.460130 +system.ruby.ST.miss_latency_hist::gmean 1618.855581 +system.ruby.ST.miss_latency_hist::stdev 1196.603290 +system.ruby.ST.miss_latency_hist | 56267 25.31% 25.31% | 56329 25.34% 50.64% | 54797 24.65% 75.29% | 45765 20.58% 95.87% | 9068 4.08% 99.95% | 109 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 222335 +system.ruby.Directory_Controller.Fetch 617810 0.00% 0.00% +system.ruby.Directory_Controller.Data 221732 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 617805 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 221732 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 396069 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 617810 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 221732 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 396069 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 617805 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 221732 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50630 12.62% 12.62% | 49663 12.38% 25.00% | 50388 12.56% 37.57% | 49765 12.41% 49.97% | 49962 12.46% 62.43% | 50103 12.49% 74.92% | 50413 12.57% 87.49% | 50187 12.51% 100.00% +system.ruby.L1Cache_Controller.Load::total 401111 +system.ruby.L1Cache_Controller.Store | 27600 12.41% 12.41% | 27856 12.53% 24.94% | 28004 12.59% 37.54% | 27726 12.47% 50.00% | 27753 12.48% 62.49% | 27852 12.53% 75.01% | 27673 12.45% 87.46% | 27886 12.54% 100.00% +system.ruby.L1Cache_Controller.Store::total 222350 +system.ruby.L1Cache_Controller.Inv | 76146 12.53% 12.53% | 75657 12.45% 24.98% | 76432 12.58% 37.55% | 75459 12.42% 49.97% | 75850 12.48% 62.45% | 76014 12.51% 74.95% | 76119 12.52% 87.48% | 76126 12.52% 100.00% +system.ruby.L1Cache_Controller.Inv::total 607803 +system.ruby.L1Cache_Controller.L1_Replacement | 552196 12.54% 12.54% | 550326 12.50% 25.04% | 552899 12.56% 37.60% | 548553 12.46% 50.06% | 549178 12.47% 62.53% | 548891 12.47% 75.00% | 551846 12.53% 87.53% | 548920 12.47% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 4402809 +system.ruby.L1Cache_Controller.Fwd_GETX | 232 13.19% 13.19% | 234 13.30% 26.49% | 225 12.79% 39.28% | 210 11.94% 51.22% | 213 12.11% 63.33% | 216 12.28% 75.61% | 231 13.13% 88.74% | 198 11.26% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1759 +system.ruby.L1Cache_Controller.Fwd_GETS | 184 14.76% 14.76% | 144 11.55% 26.30% | 143 11.47% 37.77% | 160 12.83% 50.60% | 162 12.99% 63.59% | 154 12.35% 75.94% | 135 10.83% 86.77% | 165 13.23% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 1247 +system.ruby.L1Cache_Controller.Data | 0 0.00% 0.00% | 3 27.27% 27.27% | 0 0.00% 27.27% | 2 18.18% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% +system.ruby.L1Cache_Controller.Data::total 11 +system.ruby.L1Cache_Controller.Data_Exclusive | 49783 12.61% 12.61% | 48864 12.38% 24.99% | 49581 12.56% 37.56% | 48942 12.40% 49.96% | 49189 12.46% 62.42% | 49331 12.50% 74.92% | 49626 12.57% 87.49% | 49364 12.51% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 394680 +system.ruby.L1Cache_Controller.DataS_fromL1 | 168 13.47% 13.47% | 154 12.35% 25.82% | 157 12.59% 38.41% | 164 13.15% 51.56% | 141 11.31% 62.87% | 150 12.03% 74.90% | 155 12.43% 87.33% | 158 12.67% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 1247 +system.ruby.L1Cache_Controller.Data_all_Acks | 28276 12.43% 12.43% | 28494 12.53% 24.96% | 28649 12.59% 37.55% | 28378 12.47% 50.03% | 28378 12.47% 62.50% | 28465 12.51% 75.01% | 28297 12.44% 87.45% | 28542 12.55% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 227479 +system.ruby.L1Cache_Controller.Ack | 0 0.00% 0.00% | 3 27.27% 27.27% | 0 0.00% 27.27% | 2 18.18% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% +system.ruby.L1Cache_Controller.Ack::total 11 +system.ruby.L1Cache_Controller.Ack_all | 0 0.00% 0.00% | 3 27.27% 27.27% | 0 0.00% 27.27% | 2 18.18% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 11 +system.ruby.L1Cache_Controller.WB_Ack | 40932 12.51% 12.51% | 40469 12.37% 24.88% | 41392 12.65% 37.53% | 40465 12.37% 49.90% | 40593 12.41% 62.31% | 41093 12.56% 74.87% | 41076 12.55% 87.42% | 41154 12.58% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 327174 +system.ruby.L1Cache_Controller.NP.Load | 50624 12.62% 12.62% | 49650 12.38% 25.00% | 50379 12.56% 37.57% | 49757 12.41% 49.97% | 49954 12.46% 62.43% | 50092 12.49% 74.92% | 50401 12.57% 87.49% | 50176 12.51% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 401033 +system.ruby.L1Cache_Controller.NP.Store | 27589 12.41% 12.41% | 27853 12.53% 24.94% | 28000 12.60% 37.53% | 27722 12.47% 50.00% | 27749 12.48% 62.49% | 27841 12.52% 75.01% | 27669 12.45% 87.46% | 27884 12.54% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 222307 +system.ruby.L1Cache_Controller.NP.Inv | 234 14.18% 14.18% | 198 12.00% 26.18% | 204 12.36% 38.55% | 217 13.15% 51.70% | 207 12.55% 64.24% | 208 12.61% 76.85% | 164 9.94% 86.79% | 218 13.21% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 1650 +system.ruby.L1Cache_Controller.I.Load | 6 9.09% 9.09% | 11 16.67% 25.76% | 8 12.12% 37.88% | 8 12.12% 50.00% | 6 9.09% 59.09% | 8 12.12% 71.21% | 11 16.67% 87.88% | 8 12.12% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 66 +system.ruby.L1Cache_Controller.I.Store | 10 27.78% 27.78% | 3 8.33% 36.11% | 3 8.33% 44.44% | 3 8.33% 52.78% | 3 8.33% 61.11% | 9 25.00% 86.11% | 3 8.33% 94.44% | 2 5.56% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 36 +system.ruby.L1Cache_Controller.I.L1_Replacement | 37124 12.58% 12.58% | 36897 12.51% 25.09% | 36843 12.49% 37.58% | 36860 12.49% 50.07% | 36970 12.53% 62.61% | 36689 12.44% 75.04% | 36882 12.50% 87.54% | 36746 12.46% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 295011 +system.ruby.L1Cache_Controller.S.Inv | 743 13.54% 13.54% | 675 12.30% 25.83% | 689 12.55% 38.39% | 684 12.46% 50.85% | 663 12.08% 62.93% | 649 11.82% 74.75% | 686 12.50% 87.25% | 700 12.75% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 5489 +system.ruby.L1Cache_Controller.S.L1_Replacement | 149 13.41% 13.41% | 132 11.88% 25.29% | 139 12.51% 37.80% | 149 13.41% 51.22% | 136 12.24% 63.46% | 146 13.14% 76.60% | 106 9.54% 86.14% | 154 13.86% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1111 +system.ruby.L1Cache_Controller.E.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 2 +system.ruby.L1Cache_Controller.E.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 2 +system.ruby.L1Cache_Controller.E.Inv | 23229 12.57% 12.57% | 22892 12.39% 24.96% | 23105 12.50% 37.46% | 23121 12.51% 49.98% | 23143 12.52% 62.50% | 23004 12.45% 74.95% | 23259 12.59% 87.54% | 23027 12.46% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 184780 +system.ruby.L1Cache_Controller.E.L1_Replacement | 26480 12.65% 12.65% | 25896 12.37% 25.02% | 26409 12.61% 37.63% | 25762 12.30% 49.94% | 25986 12.41% 62.35% | 26263 12.54% 74.89% | 26302 12.56% 87.45% | 26267 12.55% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 209365 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 64 13.53% 13.53% | 68 14.38% 27.91% | 60 12.68% 40.59% | 56 11.84% 52.43% | 51 10.78% 63.21% | 52 10.99% 74.21% | 58 12.26% 86.47% | 64 13.53% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 473 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 10 16.95% 16.95% | 8 13.56% 30.51% | 6 10.17% 40.68% | 3 5.08% 45.76% | 8 13.56% 59.32% | 11 18.64% 77.97% | 7 11.86% 89.83% | 6 10.17% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 59 +system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 3 +system.ruby.L1Cache_Controller.M.Store | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 1 +system.ruby.L1Cache_Controller.M.Inv | 13045 12.57% 12.57% | 13205 12.72% 25.29% | 12928 12.45% 37.74% | 12932 12.46% 50.20% | 13051 12.57% 62.77% | 12938 12.46% 75.23% | 12814 12.34% 87.58% | 12896 12.42% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 103809 +system.ruby.L1Cache_Controller.M.L1_Replacement | 14456 12.27% 12.27% | 14574 12.37% 24.64% | 14984 12.72% 37.36% | 14704 12.48% 49.84% | 14607 12.40% 62.23% | 14831 12.59% 74.82% | 14776 12.54% 87.36% | 14889 12.64% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 117821 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 27 11.25% 11.25% | 30 12.50% 23.75% | 39 16.25% 40.00% | 30 12.50% 52.50% | 32 13.33% 65.83% | 24 10.00% 75.83% | 31 12.92% 88.75% | 27 11.25% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 240 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 68 14.59% 14.59% | 47 10.09% 24.68% | 53 11.37% 36.05% | 58 12.45% 48.50% | 61 13.09% 61.59% | 55 11.80% 73.39% | 50 10.73% 84.12% | 74 15.88% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 466 +system.ruby.L1Cache_Controller.IS.Inv | 33 10.09% 10.09% | 43 13.15% 23.24% | 34 10.40% 33.64% | 48 14.68% 48.32% | 39 11.93% 60.24% | 40 12.23% 72.48% | 48 14.68% 87.16% | 42 12.84% 100.00% +system.ruby.L1Cache_Controller.IS.Inv::total 327 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 306619 12.62% 12.62% | 302229 12.44% 25.06% | 305593 12.58% 37.64% | 302624 12.46% 50.10% | 302601 12.46% 62.56% | 301776 12.42% 74.98% | 305829 12.59% 87.57% | 301854 12.43% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2429125 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49783 12.61% 12.61% | 48864 12.38% 24.99% | 49581 12.56% 37.56% | 48942 12.40% 49.96% | 49189 12.46% 62.42% | 49331 12.50% 74.92% | 49626 12.57% 87.49% | 49364 12.51% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 394680 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 168 13.47% 13.47% | 154 12.35% 25.82% | 157 12.59% 38.41% | 164 13.15% 51.56% | 141 11.31% 62.87% | 150 12.03% 74.90% | 155 12.43% 87.33% | 158 12.67% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1247 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 646 13.38% 13.38% | 598 12.39% 25.77% | 612 12.68% 38.44% | 608 12.59% 51.04% | 589 12.20% 63.24% | 579 11.99% 75.23% | 580 12.01% 87.24% | 616 12.76% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4828 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 167368 12.39% 12.39% | 170598 12.63% 25.03% | 168931 12.51% 37.54% | 168454 12.47% 50.01% | 168878 12.51% 62.52% | 169186 12.53% 75.05% | 167951 12.44% 87.48% | 169010 12.52% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1350376 +system.ruby.L1Cache_Controller.IM.Data | 0 0.00% 0.00% | 3 27.27% 27.27% | 0 0.00% 27.27% | 2 18.18% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 11 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27597 12.41% 12.41% | 27853 12.53% 24.94% | 28003 12.60% 37.54% | 27722 12.47% 50.01% | 27750 12.48% 62.49% | 27846 12.52% 75.01% | 27669 12.45% 87.46% | 27884 12.54% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 222324 +system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 3 27.27% 27.27% | 0 0.00% 27.27% | 2 18.18% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 11 +system.ruby.L1Cache_Controller.SM.Ack_all | 0 0.00% 0.00% | 3 27.27% 27.27% | 0 0.00% 27.27% | 2 18.18% 45.45% | 1 9.09% 54.55% | 1 9.09% 63.64% | 2 18.18% 81.82% | 2 18.18% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 11 +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 33 10.09% 10.09% | 43 13.15% 23.24% | 34 10.40% 33.64% | 48 14.68% 48.32% | 39 11.93% 60.24% | 40 12.23% 72.48% | 48 14.68% 87.16% | 42 12.84% 100.00% +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 327 +system.ruby.L1Cache_Controller.M_I.Inv | 38841 12.47% 12.47% | 38621 12.40% 24.86% | 39453 12.66% 37.53% | 38426 12.33% 49.86% | 38725 12.43% 62.29% | 39149 12.57% 74.85% | 39128 12.56% 87.41% | 39222 12.59% 100.00% +system.ruby.L1Cache_Controller.M_I.Inv::total 311565 +system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 141 13.48% 13.48% | 136 13.00% 26.48% | 126 12.05% 38.53% | 124 11.85% 50.38% | 130 12.43% 62.81% | 140 13.38% 76.20% | 142 13.58% 89.77% | 107 10.23% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1046 +system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 106 14.68% 14.68% | 89 12.33% 27.01% | 84 11.63% 38.64% | 99 13.71% 52.35% | 93 12.88% 65.24% | 88 12.19% 77.42% | 78 10.80% 88.23% | 85 11.77% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 722 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 1848 13.34% 13.34% | 1624 11.72% 25.06% | 1730 12.49% 37.55% | 1817 13.12% 50.67% | 1645 11.87% 62.54% | 1717 12.39% 74.94% | 1730 12.49% 87.43% | 1742 12.57% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 13853 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 2 28.57% 42.86% | 1 14.29% 57.14% | 3 42.86% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 7 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 4 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 23 12.50% 12.50% | 20 10.87% 23.37% | 28 15.22% 38.59% | 24 13.04% 51.63% | 19 10.33% 61.96% | 24 13.04% 75.00% | 26 14.13% 89.13% | 20 10.87% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 184 -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 39212 12.55% 12.55% | 39176 12.54% 25.09% | 38688 12.38% 37.48% | 39295 12.58% 50.06% | 38922 12.46% 62.52% | 39287 12.58% 75.09% | 38824 12.43% 87.52% | 38981 12.48% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 312385 -system.ruby.L2Cache_Controller.L1_GETS 404349 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 226057 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 16561 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 317938 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 6824 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 4940882 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 620662 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 620658 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 217651 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 199372 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 3831 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 190668 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 1319 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 619985 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 398766 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 221900 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 308113 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 10 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX 604 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX_old 2 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 1242 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2573 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 4 0.00% 0.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 21 11.48% 11.48% | 23 12.57% 24.04% | 19 10.38% 34.43% | 31 16.94% 51.37% | 22 12.02% 63.39% | 26 14.21% 77.60% | 20 10.93% 88.52% | 21 11.48% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 183 +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 39084 12.47% 12.47% | 38845 12.40% 24.87% | 39662 12.66% 37.53% | 38648 12.33% 49.87% | 38948 12.43% 62.30% | 39376 12.57% 74.86% | 39346 12.56% 87.42% | 39412 12.58% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 313321 +system.ruby.L2Cache_Controller.L1_GETS 402675 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 224636 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 15857 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 318841 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 6494 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 4974808 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 617805 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 617799 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 216590 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 200031 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 3820 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 188587 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 1247 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 617014 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 397247 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 220563 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_PUTX_old 309284 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 11 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX 544 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX_old 5 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 1161 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2646 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 5399 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8887 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 1319 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 1814 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 14293 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX_old 864 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 602549 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETS 16 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETX 22 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 2197 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 620658 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETS 70 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETX 61 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 6155 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 216395 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 199302 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 186852 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 2585 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 2573 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 1246 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 1242 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETS 2506 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETX 1362 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 291 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2164243 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 396259 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETS 12 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 13776 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 2506 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETS 1516 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETX 804 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_PUTX_old 310 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1208415 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 221897 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 10 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 132 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 72 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 992 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 5141 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8700 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 1247 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 1759 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 13853 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX_old 788 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 9 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 600145 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETS 23 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETX 21 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 2121 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 617799 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 4 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data_clean 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 4 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETS 48 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETX 73 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 6058 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 215422 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 199947 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 184776 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 2654 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 2646 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 1166 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 1161 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETS 2571 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETX 1408 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 278 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2181712 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 394672 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETS 7 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETX 6 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14929 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 2571 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETS 1372 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETX 722 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_PUTX_old 300 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1221486 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 220562 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 46 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 11 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 139 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 68 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 875 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 937127 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 619975 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 668 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 3309 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 1048 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 49 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 222 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 3 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 201 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 21 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement 8 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 942368 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 617003 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 583 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2761 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 953 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 59 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 235 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 15 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 211 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 24 0.00% 0.00% system.ruby.L2Cache_Controller.MT_SB.L1_PUTX 1 0.00% 0.00% system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 175 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 1097 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 1012 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 565004605..528acac96 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007434 # Number of seconds simulated -sim_ticks 7434347 # Number of ticks simulated -final_tick 7434347 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007450 # Number of seconds simulated +sim_ticks 7449950 # Number of ticks simulated +final_tick 7449950 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 60462 # Simulator tick rate (ticks/s) -host_mem_usage 481612 # Number of bytes of host memory used -host_seconds 122.96 # Real time elapsed on the host +host_tick_rate 57472 # Simulator tick rate (ticks/s) +host_mem_usage 537872 # Number of bytes of host memory used +host_seconds 129.63 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39396928 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39396928 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14155776 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14155776 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 615577 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 615577 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 221184 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 221184 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 5299312502 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 5299312502 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1904104826 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1904104826 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 7203417328 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 7203417328 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 615577 # Number of read requests accepted -system.mem_ctrls.writeReqs 221184 # Number of write requests accepted -system.mem_ctrls.readBursts 615577 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 221184 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 38921664 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 475264 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14074624 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39396928 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14155776 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 7426 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 1246 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39430656 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39430656 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14218432 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14218432 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 616104 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 616104 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 222163 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 222163 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 5292741025 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 5292741025 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1908527171 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1908527171 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 7201268196 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 7201268196 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 616105 # Number of read requests accepted +system.mem_ctrls.writeReqs 222163 # Number of write requests accepted +system.mem_ctrls.readBursts 616105 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 222163 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38949632 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 481088 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14133568 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39430720 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14218432 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 7517 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 1302 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76166 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 75916 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76401 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76284 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 75567 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76286 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 75866 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 75665 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 75571 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76259 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76117 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76093 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 75989 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76244 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 76092 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27493 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27659 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27618 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27743 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27329 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27461 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27226 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27387 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27477 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27606 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27738 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27573 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27439 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27783 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27594 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27627 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,53 +69,53 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 7434244 # Total gap between requests +system.mem_ctrls.totGap 7449899 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 615577 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 616105 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 221184 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 31005 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 21298 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 21020 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 21014 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 21010 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 20998 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 20995 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 20996 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 21008 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 21051 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 21087 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 21106 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 21092 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 21036 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 21043 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 20930 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 20829 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 20806 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 21402 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 23417 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 20537 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 20504 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 20662 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 21143 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 19571 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 18774 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 17341 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 14959 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 11156 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 6941 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 2864 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 556 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 222163 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 30549 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 21596 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 21192 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 21113 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 21031 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 21028 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 20998 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 21010 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 21064 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 21087 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 21110 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 21124 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 21122 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 21081 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 21079 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 20997 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 20881 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 20859 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 21404 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 23415 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 20541 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 20538 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 20723 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 21180 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 19536 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 18735 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 17250 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 14907 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 11091 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 6921 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 2899 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 527 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -131,48 +131,48 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1617 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1729 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 3115 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 4520 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 5913 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 7334 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 8308 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 9365 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 10303 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 11243 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 12929 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 44516 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 21633 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 13629 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 13641 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 13638 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 13639 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 13642 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1705 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 952 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 833 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 785 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 713 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 634 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 580 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 508 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 452 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 397 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 345 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1517 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1598 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2949 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 4414 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 5799 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 7205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 8259 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9290 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 10245 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 11149 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 13077 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 45268 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 22379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 13802 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 13611 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 13661 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 13631 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 13563 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1725 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 967 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 857 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 772 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 726 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 646 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 591 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 516 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 455 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 392 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 347 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 294 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 238 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 193 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 149 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 120 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 95 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 78 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 37 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 20 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 243 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 207 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 163 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 136 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 110 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 80 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 63 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 20 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 13 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -180,1234 +180,1246 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 217198 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 243.992818 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 202.467078 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 149.850896 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 27585 12.70% 12.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 89029 40.99% 53.69% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 57738 26.58% 80.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 26133 12.03% 92.31% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10701 4.93% 97.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4012 1.85% 99.08% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1375 0.63% 99.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 429 0.20% 99.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 196 0.09% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 217198 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13269 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 45.830432 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 16.164450 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 23 0.17% 0.17% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 33 0.25% 0.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 115 0.87% 1.29% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 4764 35.90% 37.19% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 1332 10.04% 47.23% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 205 1.54% 48.78% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 710 5.35% 54.13% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 5419 40.84% 94.97% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 323 2.43% 97.40% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 65 0.49% 97.89% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 134 1.01% 98.90% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 141 1.06% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 3 0.02% 99.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 1 0.01% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::160-167 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13269 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13269 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.573668 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.530150 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.283732 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 10393 78.33% 78.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 435 3.28% 81.60% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1077 8.12% 89.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 911 6.87% 96.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 245 1.85% 98.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 113 0.85% 99.28% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 39 0.29% 99.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 18 0.14% 99.71% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 19 0.14% 99.86% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 5 0.04% 99.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 1 0.01% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 6 0.05% 99.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 1 0.01% 99.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 1 0.01% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 3 0.02% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 1 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13269 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 69684050 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 81238919 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3040755 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 114.58 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 217927 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 243.578079 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 202.332515 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 149.225070 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 27531 12.63% 12.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 89928 41.27% 53.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 57630 26.44% 80.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 26331 12.08% 92.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10616 4.87% 97.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3910 1.79% 99.09% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1341 0.62% 99.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 442 0.20% 99.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 198 0.09% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 217927 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13336 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 45.632648 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 42.604910 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 16.181876 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 22 0.16% 0.16% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 23 0.17% 0.34% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 102 0.76% 1.10% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 4874 36.55% 37.65% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 1383 10.37% 48.02% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 197 1.48% 49.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 688 5.16% 54.66% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 5373 40.29% 94.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 322 2.41% 97.36% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 76 0.57% 97.93% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 142 1.06% 99.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 129 0.97% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::104-111 1 0.01% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 2 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::144-151 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::168-175 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 13336 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13336 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.559463 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.517273 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.258100 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 10504 78.76% 78.76% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 437 3.28% 82.04% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1076 8.07% 90.11% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 871 6.53% 96.64% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 245 1.84% 98.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 96 0.72% 99.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 44 0.33% 99.53% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 27 0.20% 99.73% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 16 0.12% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 6 0.04% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 4 0.03% 99.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 4 0.03% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 3 0.02% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13336 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 70095683 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 81658855 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3042940 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 115.18 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 133.58 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 5235.38 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1893.19 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 5299.31 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1904.10 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 134.18 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 5228.17 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1897.14 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 5292.75 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1908.53 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 55.69 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 40.90 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 14.79 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 20.94 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 27.75 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 397850 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 213011 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 65.42 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 96.85 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 8.88 # Average gap between requests -system.mem_ctrls.pageHitRate 73.77 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1640640960 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 911467200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7583122560 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2278088064 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 485166240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 5062396176 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 16183800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 17977065000 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 2420.131050 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 130 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 248040 # Time in different power states +system.mem_ctrls.busUtil 55.67 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 40.85 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 14.82 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 20.89 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 27.79 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 397267 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 214223 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 65.28 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 96.99 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 8.89 # Average gap between requests +system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1646182440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 914545800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7588501440 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2287554048 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 486183360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5073054948 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 16157400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 18012179436 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2419.796272 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 63 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 248560 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 7179981 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7195067 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 485166240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 160523856 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 4316043600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 4961733696 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.968979 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 7180064 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 248040 # Time in different power states +system.mem_ctrls_1.refreshEnergy 486183360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 160860384 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4325091600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 4972135344 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.968984 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7195116 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 248560 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 99085 # number of read accesses completed -system.cpu0.num_writes 54827 # number of write accesses completed -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 55173 # number of write accesses completed -system.cpu2.num_reads 99662 # number of read accesses completed -system.cpu2.num_writes 55209 # number of write accesses completed +system.cpu0.num_reads 99288 # number of read accesses completed +system.cpu0.num_writes 55258 # number of write accesses completed +system.cpu1.num_reads 99200 # number of read accesses completed +system.cpu1.num_writes 55136 # number of write accesses completed +system.cpu2.num_reads 100001 # number of read accesses completed +system.cpu2.num_writes 55818 # number of write accesses completed system.cpu3.num_reads 99361 # number of read accesses completed -system.cpu3.num_writes 55448 # number of write accesses completed -system.cpu4.num_reads 99249 # number of read accesses completed -system.cpu4.num_writes 55511 # number of write accesses completed -system.cpu5.num_reads 99199 # number of read accesses completed -system.cpu5.num_writes 55584 # number of write accesses completed -system.cpu6.num_reads 99773 # number of read accesses completed -system.cpu6.num_writes 55692 # number of write accesses completed -system.cpu7.num_reads 99764 # number of read accesses completed -system.cpu7.num_writes 55297 # number of write accesses completed +system.cpu3.num_writes 55505 # number of write accesses completed +system.cpu4.num_reads 98943 # number of read accesses completed +system.cpu4.num_writes 55417 # number of write accesses completed +system.cpu5.num_reads 99536 # number of read accesses completed +system.cpu5.num_writes 55539 # number of write accesses completed +system.cpu6.num_reads 99984 # number of read accesses completed +system.cpu6.num_writes 55224 # number of write accesses completed +system.cpu7.num_reads 99513 # number of read accesses completed +system.cpu7.num_writes 55026 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 627101 -system.ruby.outstanding_req_hist::mean 15.998452 -system.ruby.outstanding_req_hist::gmean 15.997188 -system.ruby.outstanding_req_hist::stdev 0.125833 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 27 0.00% 0.02% | 626970 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 627101 +system.ruby.outstanding_req_hist::samples 627405 +system.ruby.outstanding_req_hist::mean 15.998457 +system.ruby.outstanding_req_hist::gmean 15.997194 +system.ruby.outstanding_req_hist::stdev 0.125784 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 24 0.00% 0.02% | 627277 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 627405 system.ruby.latency_hist::bucket_size 2048 system.ruby.latency_hist::max_bucket 20479 -system.ruby.latency_hist::samples 626973 -system.ruby.latency_hist::mean 1517.423723 -system.ruby.latency_hist::gmean 1021.259356 -system.ruby.latency_hist::stdev 1496.123234 -system.ruby.latency_hist | 474274 75.65% 75.65% | 109211 17.42% 93.06% | 31636 5.05% 98.11% | 9009 1.44% 99.55% | 2159 0.34% 99.89% | 565 0.09% 99.98% | 99 0.02% 100.00% | 20 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 626973 +system.ruby.latency_hist::samples 627277 +system.ruby.latency_hist::mean 1519.910775 +system.ruby.latency_hist::gmean 1025.504888 +system.ruby.latency_hist::stdev 1490.760460 +system.ruby.latency_hist | 473792 75.53% 75.53% | 110236 17.57% 93.11% | 31414 5.01% 98.11% | 9061 1.44% 99.56% | 2199 0.35% 99.91% | 446 0.07% 99.98% | 106 0.02% 100.00% | 13 0.00% 100.00% | 8 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.latency_hist::total 627277 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 124 +system.ruby.hit_latency_hist::samples 82 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 124 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 124 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 82 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 82 system.ruby.miss_latency_hist::bucket_size 2048 system.ruby.miss_latency_hist::max_bucket 20479 -system.ruby.miss_latency_hist::samples 626849 -system.ruby.miss_latency_hist::mean 1517.723299 -system.ruby.miss_latency_hist::gmean 1022.437850 -system.ruby.miss_latency_hist::stdev 1496.119562 -system.ruby.miss_latency_hist | 474150 75.64% 75.64% | 109211 17.42% 93.06% | 31636 5.05% 98.11% | 9009 1.44% 99.55% | 2159 0.34% 99.89% | 565 0.09% 99.98% | 99 0.02% 100.00% | 20 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626849 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78032 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78046 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 627195 +system.ruby.miss_latency_hist::mean 1520.109097 +system.ruby.miss_latency_hist::gmean 1026.287427 +system.ruby.miss_latency_hist::stdev 1490.756998 +system.ruby.miss_latency_hist | 473710 75.53% 75.53% | 110236 17.58% 93.10% | 31414 5.01% 98.11% | 9061 1.44% 99.56% | 2199 0.35% 99.91% | 446 0.07% 99.98% | 106 0.02% 100.00% | 13 0.00% 100.00% | 8 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.miss_latency_hist::total 627195 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 8 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78523 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78531 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 16 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78433 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78449 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 15 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78250 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78265 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78349 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78366 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 11 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78767 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78778 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 19 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78457 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78476 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 13 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78410 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78423 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Dcache.demand_hits 13 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78422 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78435 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Dcache.demand_hits 8 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78231 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78239 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Dcache.demand_hits 21 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78251 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78272 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 9 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78469 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78478 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78547 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78559 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 7 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78282 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78289 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78376 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78388 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 11 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78287 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78298 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l2_cntrl0.L2cache.demand_hits 4590 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 622265 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 626855 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 4554 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 622644 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 627198 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers00.percent_links_utilized 5.774438 -system.ruby.network.routers00.msg_count.Request_Control::0 78032 -system.ruby.network.routers00.msg_count.Response_Data::2 76681 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 516 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 1695 -system.ruby.network.routers00.msg_count.Response_Control::2 596 -system.ruby.network.routers00.msg_count.Writeback_Data::2 76954 -system.ruby.network.routers00.msg_count.Writeback_Control::0 155996 -system.ruby.network.routers00.msg_count.Forwarded_Control::0 860 -system.ruby.network.routers00.msg_count.Invalidate_Control::0 240 -system.ruby.network.routers00.msg_count.Unblock_Control::2 78829 -system.ruby.network.routers00.msg_bytes.Request_Control::0 624256 -system.ruby.network.routers00.msg_bytes.Response_Data::2 5521032 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2 37152 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2 122040 -system.ruby.network.routers00.msg_bytes.Response_Control::2 4768 -system.ruby.network.routers00.msg_bytes.Writeback_Data::2 5540688 -system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1247968 -system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6880 -system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1920 -system.ruby.network.routers00.msg_bytes.Unblock_Control::2 630632 -system.ruby.network.routers01.percent_links_utilized 5.804161 -system.ruby.network.routers01.msg_count.Request_Control::0 78433 -system.ruby.network.routers01.msg_count.Response_Data::2 76986 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 599 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 1726 -system.ruby.network.routers01.msg_count.Response_Control::2 622 -system.ruby.network.routers01.msg_count.Writeback_Data::2 77339 -system.ruby.network.routers01.msg_count.Writeback_Control::0 156756 -system.ruby.network.routers01.msg_count.Forwarded_Control::0 880 -system.ruby.network.routers01.msg_count.Invalidate_Control::0 243 -system.ruby.network.routers01.msg_count.Unblock_Control::2 79225 -system.ruby.network.routers01.msg_bytes.Request_Control::0 627464 -system.ruby.network.routers01.msg_bytes.Response_Data::2 5542992 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 43128 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 124272 -system.ruby.network.routers01.msg_bytes.Response_Control::2 4976 -system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5568408 -system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1254048 -system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 7040 -system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1944 -system.ruby.network.routers01.msg_bytes.Unblock_Control::2 633800 -system.ruby.network.routers02.percent_links_utilized 5.796696 -system.ruby.network.routers02.msg_count.Request_Control::0 78349 -system.ruby.network.routers02.msg_count.Response_Data::2 76918 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 586 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 1696 -system.ruby.network.routers02.msg_count.Response_Control::2 585 -system.ruby.network.routers02.msg_count.Writeback_Data::2 77247 -system.ruby.network.routers02.msg_count.Writeback_Control::0 156587 -system.ruby.network.routers02.msg_count.Forwarded_Control::0 854 -system.ruby.network.routers02.msg_count.Invalidate_Control::0 208 -system.ruby.network.routers02.msg_count.Unblock_Control::2 79180 -system.ruby.network.routers02.msg_bytes.Request_Control::0 626792 -system.ruby.network.routers02.msg_bytes.Response_Data::2 5538096 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 42192 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 122112 -system.ruby.network.routers02.msg_bytes.Response_Control::2 4680 -system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5561784 -system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1252696 -system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 6832 -system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 1664 -system.ruby.network.routers02.msg_bytes.Unblock_Control::2 633440 -system.ruby.network.routers03.percent_links_utilized 5.805984 -system.ruby.network.routers03.msg_count.Request_Control::0 78457 -system.ruby.network.routers03.msg_count.Response_Data::2 77073 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2 549 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::2 1649 -system.ruby.network.routers03.msg_count.Response_Control::2 588 -system.ruby.network.routers03.msg_count.Writeback_Data::2 77443 -system.ruby.network.routers03.msg_count.Writeback_Control::0 156836 -system.ruby.network.routers03.msg_count.Forwarded_Control::0 815 -system.ruby.network.routers03.msg_count.Invalidate_Control::0 215 -system.ruby.network.routers03.msg_count.Unblock_Control::2 79211 -system.ruby.network.routers03.msg_bytes.Request_Control::0 627656 -system.ruby.network.routers03.msg_bytes.Response_Data::2 5549256 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2 39528 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2 118728 -system.ruby.network.routers03.msg_bytes.Response_Control::2 4704 -system.ruby.network.routers03.msg_bytes.Writeback_Data::2 5575896 -system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1254688 -system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 6520 -system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 1720 -system.ruby.network.routers03.msg_bytes.Unblock_Control::2 633688 -system.ruby.network.routers04.percent_links_utilized 5.804017 -system.ruby.network.routers04.msg_count.Request_Control::0 78422 -system.ruby.network.routers04.msg_count.Response_Data::2 77045 +system.ruby.network.routers00.percent_links_utilized 5.796257 +system.ruby.network.routers00.msg_count.Request_Control::0 78523 +system.ruby.network.routers00.msg_count.Response_Data::2 77115 +system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 555 +system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 1638 +system.ruby.network.routers00.msg_count.Response_Control::2 616 +system.ruby.network.routers00.msg_count.Writeback_Data::2 77458 +system.ruby.network.routers00.msg_count.Writeback_Control::0 156930 +system.ruby.network.routers00.msg_count.Forwarded_Control::0 788 +system.ruby.network.routers00.msg_count.Invalidate_Control::0 227 +system.ruby.network.routers00.msg_count.Unblock_Control::2 79295 +system.ruby.network.routers00.msg_bytes.Request_Control::0 628184 +system.ruby.network.routers00.msg_bytes.Response_Data::2 5552280 +system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2 39960 +system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2 117936 +system.ruby.network.routers00.msg_bytes.Response_Control::2 4928 +system.ruby.network.routers00.msg_bytes.Writeback_Data::2 5576976 +system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1255440 +system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6304 +system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1816 +system.ruby.network.routers00.msg_bytes.Unblock_Control::2 634360 +system.ruby.network.routers01.percent_links_utilized 5.779197 +system.ruby.network.routers01.msg_count.Request_Control::0 78250 +system.ruby.network.routers01.msg_count.Response_Data::2 76912 +system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 550 +system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 1630 +system.ruby.network.routers01.msg_count.Response_Control::2 579 +system.ruby.network.routers01.msg_count.Writeback_Data::2 77234 +system.ruby.network.routers01.msg_count.Writeback_Control::0 156381 +system.ruby.network.routers01.msg_count.Forwarded_Control::0 846 +system.ruby.network.routers01.msg_count.Invalidate_Control::0 219 +system.ruby.network.routers01.msg_count.Unblock_Control::2 78980 +system.ruby.network.routers01.msg_bytes.Request_Control::0 626000 +system.ruby.network.routers01.msg_bytes.Response_Data::2 5537664 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 39600 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 117360 +system.ruby.network.routers01.msg_bytes.Response_Control::2 4632 +system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5560848 +system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1251048 +system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 6768 +system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1752 +system.ruby.network.routers01.msg_bytes.Unblock_Control::2 631840 +system.ruby.network.routers02.percent_links_utilized 5.815458 +system.ruby.network.routers02.msg_count.Request_Control::0 78767 +system.ruby.network.routers02.msg_count.Response_Data::2 77430 +system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 527 +system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 1612 +system.ruby.network.routers02.msg_count.Response_Control::2 638 +system.ruby.network.routers02.msg_count.Writeback_Data::2 77722 +system.ruby.network.routers02.msg_count.Writeback_Control::0 157422 +system.ruby.network.routers02.msg_count.Forwarded_Control::0 803 +system.ruby.network.routers02.msg_count.Invalidate_Control::0 265 +system.ruby.network.routers02.msg_count.Unblock_Control::2 79484 +system.ruby.network.routers02.msg_bytes.Request_Control::0 630136 +system.ruby.network.routers02.msg_bytes.Response_Data::2 5574960 +system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 37944 +system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 116064 +system.ruby.network.routers02.msg_bytes.Response_Control::2 5104 +system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5595984 +system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1259376 +system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 6424 +system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 2120 +system.ruby.network.routers02.msg_bytes.Unblock_Control::2 635872 +system.ruby.network.routers03.percent_links_utilized 5.790428 +system.ruby.network.routers03.msg_count.Request_Control::0 78410 +system.ruby.network.routers03.msg_count.Response_Data::2 77031 +system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2 564 +system.ruby.network.routers03.msg_count.ResponseLocal_Data::2 1654 +system.ruby.network.routers03.msg_count.Response_Control::2 571 +system.ruby.network.routers03.msg_count.Writeback_Data::2 77374 +system.ruby.network.routers03.msg_count.Writeback_Control::0 156720 +system.ruby.network.routers03.msg_count.Forwarded_Control::0 843 +system.ruby.network.routers03.msg_count.Invalidate_Control::0 212 +system.ruby.network.routers03.msg_count.Unblock_Control::2 79173 +system.ruby.network.routers03.msg_bytes.Request_Control::0 627280 +system.ruby.network.routers03.msg_bytes.Response_Data::2 5546232 +system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2 40608 +system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2 119088 +system.ruby.network.routers03.msg_bytes.Response_Control::2 4568 +system.ruby.network.routers03.msg_bytes.Writeback_Data::2 5570928 +system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1253760 +system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 6744 +system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 1696 +system.ruby.network.routers03.msg_bytes.Unblock_Control::2 633384 +system.ruby.network.routers04.percent_links_utilized 5.775314 +system.ruby.network.routers04.msg_count.Request_Control::0 78231 +system.ruby.network.routers04.msg_count.Response_Data::2 76802 system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2 587 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 1621 -system.ruby.network.routers04.msg_count.Response_Control::2 576 -system.ruby.network.routers04.msg_count.Writeback_Data::2 77413 -system.ruby.network.routers04.msg_count.Writeback_Control::0 156754 -system.ruby.network.routers04.msg_count.Forwarded_Control::0 834 -system.ruby.network.routers04.msg_count.Invalidate_Control::0 211 -system.ruby.network.routers04.msg_count.Unblock_Control::2 79172 -system.ruby.network.routers04.msg_bytes.Request_Control::0 627376 -system.ruby.network.routers04.msg_bytes.Response_Data::2 5547240 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 1643 +system.ruby.network.routers04.msg_count.Response_Control::2 584 +system.ruby.network.routers04.msg_count.Writeback_Data::2 77171 +system.ruby.network.routers04.msg_count.Writeback_Control::0 156352 +system.ruby.network.routers04.msg_count.Forwarded_Control::0 803 +system.ruby.network.routers04.msg_count.Invalidate_Control::0 217 +system.ruby.network.routers04.msg_count.Unblock_Control::2 79018 +system.ruby.network.routers04.msg_bytes.Request_Control::0 625848 +system.ruby.network.routers04.msg_bytes.Response_Data::2 5529744 system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 42264 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 116712 -system.ruby.network.routers04.msg_bytes.Response_Control::2 4608 -system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5573736 -system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1254032 -system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 6672 -system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 1688 -system.ruby.network.routers04.msg_bytes.Unblock_Control::2 633376 -system.ruby.network.routers05.percent_links_utilized 5.789597 -system.ruby.network.routers05.msg_count.Request_Control::0 78251 -system.ruby.network.routers05.msg_count.Response_Data::2 76821 -system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2 550 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::2 1691 -system.ruby.network.routers05.msg_count.Response_Control::2 607 -system.ruby.network.routers05.msg_count.Writeback_Data::2 77197 -system.ruby.network.routers05.msg_count.Writeback_Control::0 156420 -system.ruby.network.routers05.msg_count.Forwarded_Control::0 814 -system.ruby.network.routers05.msg_count.Invalidate_Control::0 209 -system.ruby.network.routers05.msg_count.Unblock_Control::2 79043 -system.ruby.network.routers05.msg_bytes.Request_Control::0 626008 -system.ruby.network.routers05.msg_bytes.Response_Data::2 5531112 -system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2 39600 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2 121752 -system.ruby.network.routers05.msg_bytes.Response_Control::2 4856 -system.ruby.network.routers05.msg_bytes.Writeback_Data::2 5558184 -system.ruby.network.routers05.msg_bytes.Writeback_Control::0 1251360 -system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 6512 -system.ruby.network.routers05.msg_bytes.Invalidate_Control::0 1672 -system.ruby.network.routers05.msg_bytes.Unblock_Control::2 632344 -system.ruby.network.routers06.percent_links_utilized 5.812424 -system.ruby.network.routers06.msg_count.Request_Control::0 78547 -system.ruby.network.routers06.msg_count.Response_Data::2 77110 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2 615 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::2 1646 -system.ruby.network.routers06.msg_count.Response_Control::2 582 -system.ruby.network.routers06.msg_count.Writeback_Data::2 77518 -system.ruby.network.routers06.msg_count.Writeback_Control::0 156993 -system.ruby.network.routers06.msg_count.Forwarded_Control::0 827 -system.ruby.network.routers06.msg_count.Invalidate_Control::0 218 -system.ruby.network.routers06.msg_count.Unblock_Control::2 79295 -system.ruby.network.routers06.msg_bytes.Request_Control::0 628376 -system.ruby.network.routers06.msg_bytes.Response_Data::2 5551920 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2 44280 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2 118512 -system.ruby.network.routers06.msg_bytes.Response_Control::2 4656 -system.ruby.network.routers06.msg_bytes.Writeback_Data::2 5581296 -system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1255944 -system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 6616 -system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 1744 -system.ruby.network.routers06.msg_bytes.Unblock_Control::2 634360 -system.ruby.network.routers07.percent_links_utilized 5.797977 -system.ruby.network.routers07.msg_count.Request_Control::0 78376 -system.ruby.network.routers07.msg_count.Response_Data::2 76937 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2 588 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::2 1652 -system.ruby.network.routers07.msg_count.Response_Control::2 614 -system.ruby.network.routers07.msg_count.Writeback_Data::2 77308 -system.ruby.network.routers07.msg_count.Writeback_Control::0 156628 -system.ruby.network.routers07.msg_count.Forwarded_Control::0 804 -system.ruby.network.routers07.msg_count.Invalidate_Control::0 253 -system.ruby.network.routers07.msg_count.Unblock_Control::2 79127 -system.ruby.network.routers07.msg_bytes.Request_Control::0 627008 -system.ruby.network.routers07.msg_bytes.Response_Data::2 5539464 -system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2 42336 -system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2 118944 -system.ruby.network.routers07.msg_bytes.Response_Control::2 4912 -system.ruby.network.routers07.msg_bytes.Writeback_Data::2 5566176 -system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1253024 -system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 6432 -system.ruby.network.routers07.msg_bytes.Invalidate_Control::0 2024 -system.ruby.network.routers07.msg_bytes.Unblock_Control::2 633016 -system.ruby.network.routers08.percent_links_utilized 76.920347 -system.ruby.network.routers08.msg_count.Request_Control::0 626855 -system.ruby.network.routers08.msg_count.Request_Control::1 615577 -system.ruby.network.routers08.msg_count.Response_Data::2 1231146 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2 4590 -system.ruby.network.routers08.msg_count.Response_Control::2 1176 -system.ruby.network.routers08.msg_count.Writeback_Data::2 839603 -system.ruby.network.routers08.msg_count.Writeback_Control::0 1252958 -system.ruby.network.routers08.msg_count.Writeback_Control::1 442374 -system.ruby.network.routers08.msg_count.Forwarded_Control::0 6688 -system.ruby.network.routers08.msg_count.Invalidate_Control::0 1787 -system.ruby.network.routers08.msg_count.Unblock_Control::2 1248641 -system.ruby.network.routers08.msg_bytes.Request_Control::0 5014840 -system.ruby.network.routers08.msg_bytes.Request_Control::1 4924616 -system.ruby.network.routers08.msg_bytes.Response_Data::2 88642512 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 330480 -system.ruby.network.routers08.msg_bytes.Response_Control::2 9408 -system.ruby.network.routers08.msg_bytes.Writeback_Data::2 60451416 -system.ruby.network.routers08.msg_bytes.Writeback_Control::0 10023664 -system.ruby.network.routers08.msg_bytes.Writeback_Control::1 3538992 -system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 53504 -system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 14296 -system.ruby.network.routers08.msg_bytes.Unblock_Control::2 9989128 -system.ruby.network.routers09.percent_links_utilized 30.952174 -system.ruby.network.routers09.msg_count.Request_Control::1 615577 -system.ruby.network.routers09.msg_count.Response_Data::2 615577 -system.ruby.network.routers09.msg_count.Writeback_Data::2 221184 -system.ruby.network.routers09.msg_count.Writeback_Control::1 442380 -system.ruby.network.routers09.msg_count.Unblock_Control::2 615562 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-system.ruby.LD.miss_latency_hist | 305445 75.66% 75.66% | 70250 17.40% 93.06% | 20367 5.04% 98.10% | 5840 1.45% 99.55% | 1389 0.34% 99.89% | 361 0.09% 99.98% | 65 0.02% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 403732 +system.ruby.LD.miss_latency_hist::samples 403139 +system.ruby.LD.miss_latency_hist::mean 1518.594289 +system.ruby.LD.miss_latency_hist::gmean 1024.321431 +system.ruby.LD.miss_latency_hist::stdev 1489.266409 +system.ruby.LD.miss_latency_hist | 304442 75.52% 75.52% | 71031 17.62% 93.14% | 20112 4.99% 98.13% | 5774 1.43% 99.56% | 1417 0.35% 99.91% | 283 0.07% 99.98% | 64 0.02% 100.00% | 9 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 403139 system.ruby.ST.latency_hist::bucket_size 2048 system.ruby.ST.latency_hist::max_bucket 20479 -system.ruby.ST.latency_hist::samples 223143 -system.ruby.ST.latency_hist::mean 1521.208472 -system.ruby.ST.latency_hist::gmean 1027.577825 -system.ruby.ST.latency_hist::stdev 1494.533357 -system.ruby.ST.latency_hist | 168731 75.62% 75.62% | 38961 17.46% 93.08% | 11269 5.05% 98.13% | 3169 1.42% 99.55% | 770 0.35% 99.89% | 204 0.09% 99.98% | 34 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223143 +system.ruby.ST.latency_hist::samples 224071 +system.ruby.ST.latency_hist::mean 1522.732915 +system.ruby.ST.latency_hist::gmean 1029.431875 +system.ruby.ST.latency_hist::stdev 1493.436472 +system.ruby.ST.latency_hist | 169283 75.55% 75.55% | 39205 17.50% 93.05% | 11302 5.04% 98.09% | 3287 1.47% 99.56% | 782 0.35% 99.91% | 163 0.07% 99.98% | 42 0.02% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 224071 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 26 +system.ruby.ST.hit_latency_hist::samples 15 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 26 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 26 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 15 system.ruby.ST.miss_latency_hist::bucket_size 2048 system.ruby.ST.miss_latency_hist::max_bucket 20479 -system.ruby.ST.miss_latency_hist::samples 223117 -system.ruby.ST.miss_latency_hist::mean 1521.385390 -system.ruby.ST.miss_latency_hist::gmean 1028.276933 -system.ruby.ST.miss_latency_hist::stdev 1494.530566 -system.ruby.ST.miss_latency_hist | 168705 75.61% 75.61% | 38961 17.46% 93.07% | 11269 5.05% 98.13% | 3169 1.42% 99.55% | 770 0.35% 99.89% | 204 0.09% 99.98% | 34 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223117 -system.ruby.Directory_Controller.GETX 221210 0.00% 0.00% -system.ruby.Directory_Controller.GETS 394374 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 221085 0.00% 0.00% -system.ruby.Directory_Controller.PUTO_SHARERS 105 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 143614 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 250750 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 221198 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 221184 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 615577 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 221184 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 78802 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 143619 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 220913 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 142401 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 250755 0.00% 0.00% -system.ruby.Directory_Controller.S.Memory_Ack 105 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 221085 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTO_SHARERS 105 0.00% 0.00% -system.ruby.Directory_Controller.IS.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 143614 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 143619 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Ack 100 0.00% 0.00% -system.ruby.Directory_Controller.SS.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 250750 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 250755 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 221198 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 221203 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 66 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 221079 0.00% 0.00% -system.ruby.Directory_Controller.MIS.Dirty_Writeback 105 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50428 12.48% 12.48% | 50682 12.55% 25.03% | 50615 12.53% 37.56% | 50552 12.51% 50.08% | 50377 12.47% 62.55% | 50216 12.43% 74.98% | 50557 12.52% 87.49% | 50520 12.51% 100.00% -system.ruby.L1Cache_Controller.Load::total 403947 -system.ruby.L1Cache_Controller.Store | 27645 12.39% 12.39% | 27771 12.44% 24.83% | 27753 12.44% 37.27% | 27971 12.53% 49.80% | 28068 12.58% 62.38% | 28075 12.58% 74.96% | 28004 12.55% 87.50% | 27887 12.50% 100.00% -system.ruby.L1Cache_Controller.Store::total 223174 -system.ruby.L1Cache_Controller.L1_Replacement | 9437024 12.51% 12.51% | 9428542 12.50% 25.01% | 9430070 12.50% 37.51% | 9427922 12.50% 50.01% | 9423979 12.49% 62.50% | 9433022 12.51% 75.01% | 9422446 12.49% 87.50% | 9430776 12.50% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 75433781 -system.ruby.L1Cache_Controller.Fwd_GETX | 160 12.60% 12.60% | 161 12.68% 25.28% | 194 15.28% 40.55% | 145 11.42% 51.97% | 163 12.83% 64.80% | 138 10.87% 75.67% | 160 12.60% 88.27% | 149 11.73% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1270 -system.ruby.L1Cache_Controller.Fwd_GETS | 733 12.79% 12.79% | 762 13.29% 26.08% | 712 12.42% 38.50% | 692 12.07% 50.58% | 706 12.32% 62.89% | 717 12.51% 75.40% | 715 12.47% 87.88% | 695 12.12% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 5732 -system.ruby.L1Cache_Controller.Inv | 240 13.36% 13.36% | 243 13.52% 26.88% | 208 11.57% 38.45% | 215 11.96% 50.42% | 211 11.74% 62.16% | 209 11.63% 73.79% | 218 12.13% 85.92% | 253 14.08% 100.00% -system.ruby.L1Cache_Controller.Inv::total 1797 -system.ruby.L1Cache_Controller.Ack | 356 11.97% 11.97% | 379 12.75% 24.72% | 377 12.68% 37.40% | 373 12.55% 49.95% | 365 12.28% 62.23% | 398 13.39% 75.61% | 364 12.24% 87.86% | 361 12.14% 100.00% -system.ruby.L1Cache_Controller.Ack::total 2973 -system.ruby.L1Cache_Controller.Data | 50238 12.49% 12.49% | 50469 12.55% 25.04% | 50418 12.54% 37.57% | 50300 12.51% 50.08% | 50156 12.47% 62.55% | 49994 12.43% 74.98% | 50340 12.52% 87.50% | 50293 12.50% 100.00% -system.ruby.L1Cache_Controller.Data::total 402208 -system.ruby.L1Cache_Controller.Exclusive_Data | 27794 12.37% 12.37% | 27962 12.45% 24.82% | 27928 12.43% 37.25% | 28156 12.53% 49.79% | 28263 12.58% 62.37% | 28254 12.58% 74.94% | 28204 12.56% 87.50% | 28080 12.50% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 224641 -system.ruby.L1Cache_Controller.Writeback_Ack | 665 12.82% 12.82% | 665 12.82% 25.64% | 683 13.16% 38.80% | 624 12.03% 50.83% | 614 11.84% 62.66% | 679 13.09% 75.75% | 631 12.16% 87.91% | 627 12.09% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 5188 -system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77086 12.44% 12.44% | 77469 12.51% 24.95% | 77398 12.49% 37.44% | 77574 12.52% 49.97% | 77552 12.52% 62.49% | 77313 12.48% 74.97% | 77638 12.53% 87.50% | 77435 12.50% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 619465 -system.ruby.L1Cache_Controller.Writeback_Nack | 247 13.53% 13.53% | 243 13.31% 26.83% | 211 11.56% 38.39% | 220 12.05% 50.44% | 211 11.56% 61.99% | 217 11.88% 73.88% | 226 12.38% 86.25% | 251 13.75% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 1826 -system.ruby.L1Cache_Controller.All_acks | 27633 12.38% 12.38% | 27766 12.44% 24.83% | 27743 12.43% 37.26% | 27965 12.53% 49.80% | 28063 12.58% 62.38% | 28062 12.58% 74.95% | 28003 12.55% 87.50% | 27882 12.50% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 223117 -system.ruby.L1Cache_Controller.Use_Timeout | 27792 12.37% 12.37% | 27962 12.45% 24.82% | 27928 12.43% 37.25% | 28155 12.53% 49.79% | 28263 12.58% 62.37% | 28254 12.58% 74.94% | 28204 12.56% 87.50% | 28079 12.50% 100.00% -system.ruby.L1Cache_Controller.Use_Timeout::total 224637 -system.ruby.L1Cache_Controller.I.Load | 50399 12.48% 12.48% | 50665 12.55% 25.03% | 50603 12.53% 37.57% | 50491 12.51% 50.07% | 50359 12.47% 62.54% | 50188 12.43% 74.97% | 50544 12.52% 87.49% | 50494 12.51% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 403743 -system.ruby.L1Cache_Controller.I.Store | 27633 12.39% 12.39% | 27766 12.45% 24.83% | 27743 12.43% 37.27% | 27964 12.53% 49.80% | 28062 12.58% 62.38% | 28062 12.58% 74.95% | 27999 12.55% 87.50% | 27879 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 223108 -system.ruby.L1Cache_Controller.I.L1_Replacement | 48 11.03% 11.03% | 61 14.02% 25.06% | 58 13.33% 38.39% | 46 10.57% 48.97% | 52 11.95% 60.92% | 51 11.72% 72.64% | 54 12.41% 85.06% | 65 14.94% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 435 -system.ruby.L1Cache_Controller.S.Load | 6 11.76% 11.76% | 6 11.76% 23.53% | 5 9.80% 33.33% | 6 11.76% 45.10% | 6 11.76% 56.86% | 11 21.57% 78.43% | 6 11.76% 90.20% | 5 9.80% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 51 -system.ruby.L1Cache_Controller.S.Store | 0 0.00% 0.00% | 2 12.50% 12.50% | 3 18.75% 31.25% | 2 12.50% 43.75% | 1 6.25% 50.00% | 1 6.25% 56.25% | 4 25.00% 81.25% | 3 18.75% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 16 -system.ruby.L1Cache_Controller.S.L1_Replacement | 50228 12.49% 12.49% | 50453 12.55% 25.04% | 50408 12.54% 37.57% | 50291 12.51% 50.08% | 50143 12.47% 62.55% | 49984 12.43% 74.98% | 50328 12.52% 87.50% | 50277 12.50% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 402112 -system.ruby.L1Cache_Controller.S.Fwd_GETS | 45 11.94% 11.94% | 60 15.92% 27.85% | 56 14.85% 42.71% | 42 11.14% 53.85% | 40 10.61% 64.46% | 39 10.34% 74.80% | 55 14.59% 89.39% | 40 10.61% 100.00% -system.ruby.L1Cache_Controller.S.Fwd_GETS::total 377 -system.ruby.L1Cache_Controller.S.Inv | 9 12.50% 12.50% | 12 16.67% 29.17% | 6 8.33% 37.50% | 5 6.94% 44.44% | 12 16.67% 61.11% | 8 11.11% 72.22% | 7 9.72% 81.94% | 13 18.06% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 72 -system.ruby.L1Cache_Controller.M.L1_Replacement | 160 10.53% 10.53% | 195 12.83% 23.36% | 185 12.17% 35.53% | 191 12.57% 48.09% | 199 13.09% 61.18% | 192 12.63% 73.82% | 200 13.16% 86.97% | 198 13.03% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 1520 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 465 10.98% 10.98% | 530 12.51% 23.49% | 698 16.48% 39.98% | 505 11.92% 51.90% | 529 12.49% 64.39% | 418 9.87% 74.26% | 568 13.41% 87.67% | 522 12.33% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 4235 -system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 4 -system.ruby.L1Cache_Controller.M_W.Use_Timeout | 161 10.56% 10.56% | 196 12.86% 23.43% | 185 12.14% 35.56% | 191 12.53% 48.10% | 200 13.12% 61.22% | 192 12.60% 73.82% | 201 13.19% 87.01% | 198 12.99% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1524 -system.ruby.L1Cache_Controller.MM.Load | 1 7.69% 7.69% | 2 15.38% 23.08% | 3 23.08% 46.15% | 3 23.08% 69.23% | 0 0.00% 69.23% | 2 15.38% 84.62% | 0 0.00% 84.62% | 2 15.38% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 13 -system.ruby.L1Cache_Controller.MM.Store | 2 18.18% 18.18% | 0 0.00% 18.18% | 4 36.36% 54.55% | 3 27.27% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 11 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 27592 12.39% 12.39% | 27718 12.44% 24.83% | 27691 12.43% 37.26% | 27923 12.54% 49.80% | 28023 12.58% 62.38% | 28019 12.58% 74.96% | 27957 12.55% 87.51% | 27829 12.49% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222752 -system.ruby.L1Cache_Controller.MM.Fwd_GETX | 12 9.92% 9.92% | 20 16.53% 26.45% | 26 21.49% 47.93% | 11 9.09% 57.02% | 13 10.74% 67.77% | 8 6.61% 74.38% | 16 13.22% 87.60% | 15 12.40% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 121 -system.ruby.L1Cache_Controller.MM.Fwd_GETS | 26 10.92% 10.92% | 28 11.76% 22.69% | 26 10.92% 33.61% | 30 12.61% 46.22% | 26 10.92% 57.14% | 35 14.71% 71.85% | 30 12.61% 84.45% | 37 15.55% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 238 -system.ruby.L1Cache_Controller.MM_W.Load | 3 8.82% 8.82% | 5 14.71% 23.53% | 3 8.82% 32.35% | 6 17.65% 50.00% | 3 8.82% 58.82% | 6 17.65% 76.47% | 5 14.71% 91.18% | 3 8.82% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 34 -system.ruby.L1Cache_Controller.MM_W.Store | 2 13.33% 13.33% | 3 20.00% 33.33% | 2 13.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 1 6.67% 80.00% | 1 6.67% 86.67% | 2 13.33% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 15 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 613663 12.48% 12.48% | 608323 12.37% 24.85% | 616946 12.54% 37.39% | 613237 12.47% 49.86% | 617680 12.56% 62.42% | 618886 12.58% 75.01% | 616731 12.54% 87.55% | 612440 12.45% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4917906 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 15 16.67% 16.67% | 9 10.00% 26.67% | 17 18.89% 45.56% | 3 3.33% 48.89% | 8 8.89% 57.78% | 13 14.44% 72.22% | 18 20.00% 92.22% | 7 7.78% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 90 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 18 8.18% 8.18% | 34 15.45% 23.64% | 35 15.91% 39.55% | 19 8.64% 48.18% | 25 11.36% 59.55% | 28 12.73% 72.27% | 28 12.73% 85.00% | 33 15.00% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 220 -system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27631 12.38% 12.38% | 27766 12.44% 24.83% | 27743 12.43% 37.26% | 27964 12.53% 49.80% | 28063 12.58% 62.38% | 28062 12.58% 74.95% | 28003 12.55% 87.50% | 27881 12.50% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 223113 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 3100083 12.39% 12.39% | 3100594 12.39% 24.78% | 3114295 12.44% 37.22% | 3131272 12.51% 49.73% | 3172501 12.68% 62.41% | 3140503 12.55% 74.95% | 3129364 12.50% 87.46% | 3139161 12.54% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 25027773 -system.ruby.L1Cache_Controller.IM.Ack | 130 11.00% 11.00% | 152 12.86% 23.86% | 136 11.51% 35.36% | 148 12.52% 47.88% | 143 12.10% 59.98% | 166 14.04% 74.03% | 155 13.11% 87.14% | 152 12.86% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1182 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27633 12.39% 12.39% | 27764 12.44% 24.83% | 27740 12.43% 37.26% | 27963 12.53% 49.80% | 28062 12.58% 62.38% | 28061 12.58% 74.95% | 27999 12.55% 87.50% | 27879 12.50% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 223101 -system.ruby.L1Cache_Controller.SM.L1_Replacement | 0 0.00% 0.00% | 577 21.47% 21.47% | 301 11.20% 32.66% | 296 11.01% 43.68% | 399 14.84% 58.52% | 0 0.00% 58.52% | 838 31.18% 89.69% | 277 10.31% 100.00% -system.ruby.L1Cache_Controller.SM.L1_Replacement::total 2688 -system.ruby.L1Cache_Controller.SM.Exclusive_Data | 0 0.00% 0.00% | 2 12.50% 12.50% | 3 18.75% 31.25% | 2 12.50% 43.75% | 1 6.25% 50.00% | 1 6.25% 56.25% | 4 25.00% 81.25% | 3 18.75% 100.00% -system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 16 -system.ruby.L1Cache_Controller.OM.L1_Replacement | 21719 12.56% 12.56% | 21417 12.39% 24.95% | 21539 12.46% 37.42% | 21504 12.44% 49.86% | 22297 12.90% 62.76% | 21631 12.51% 75.27% | 21846 12.64% 87.91% | 20903 12.09% 100.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement::total 172856 -system.ruby.L1Cache_Controller.OM.Ack | 226 12.62% 12.62% | 227 12.67% 25.29% | 241 13.46% 38.75% | 225 12.56% 51.31% | 222 12.40% 63.71% | 232 12.95% 76.66% | 209 11.67% 88.33% | 209 11.67% 100.00% -system.ruby.L1Cache_Controller.OM.Ack::total 1791 -system.ruby.L1Cache_Controller.OM.All_acks | 27633 12.38% 12.38% | 27766 12.44% 24.83% | 27743 12.43% 37.26% | 27965 12.53% 49.80% | 28063 12.58% 62.38% | 28062 12.58% 74.95% | 28003 12.55% 87.50% | 27882 12.50% 100.00% -system.ruby.L1Cache_Controller.OM.All_acks::total 223117 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 5623066 12.58% 12.58% | 5618674 12.57% 25.16% | 5597949 12.53% 37.69% | 5582657 12.49% 50.18% | 5532156 12.38% 62.56% | 5573338 12.47% 75.04% | 5574560 12.48% 87.51% | 5579104 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44681504 -system.ruby.L1Cache_Controller.IS.Data | 50238 12.49% 12.49% | 50469 12.55% 25.04% | 50418 12.54% 37.57% | 50300 12.51% 50.08% | 50156 12.47% 62.55% | 49994 12.43% 74.98% | 50340 12.52% 87.50% | 50293 12.50% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 402208 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 161 10.56% 10.56% | 196 12.86% 23.43% | 185 12.14% 35.56% | 191 12.53% 48.10% | 200 13.12% 61.22% | 192 12.60% 73.82% | 201 13.19% 87.01% | 198 12.99% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1524 -system.ruby.L1Cache_Controller.SI.Load | 17 18.09% 18.09% | 2 2.13% 20.21% | 1 1.06% 21.28% | 46 48.94% 70.21% | 3 3.19% 73.40% | 8 8.51% 81.91% | 1 1.06% 82.98% | 16 17.02% 100.00% -system.ruby.L1Cache_Controller.SI.Load::total 94 -system.ruby.L1Cache_Controller.SI.Store | 1 6.25% 6.25% | 0 0.00% 6.25% | 0 0.00% 6.25% | 1 6.25% 12.50% | 1 6.25% 18.75% | 10 62.50% 81.25% | 0 0.00% 81.25% | 3 18.75% 100.00% -system.ruby.L1Cache_Controller.SI.Store::total 16 -system.ruby.L1Cache_Controller.SI.Fwd_GETS | 393 13.54% 13.54% | 384 13.23% 26.77% | 337 11.61% 38.39% | 357 12.30% 50.69% | 382 13.16% 63.85% | 357 12.30% 76.15% | 346 11.92% 88.08% | 346 11.92% 100.00% -system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2902 -system.ruby.L1Cache_Controller.SI.Inv | 231 13.39% 13.39% | 231 13.39% 26.78% | 202 11.71% 38.49% | 210 12.17% 50.67% | 199 11.54% 62.20% | 201 11.65% 73.86% | 211 12.23% 86.09% | 240 13.91% 100.00% -system.ruby.L1Cache_Controller.SI.Inv::total 1725 -system.ruby.L1Cache_Controller.SI.Writeback_Ack | 663 12.81% 12.81% | 663 12.81% 25.61% | 681 13.15% 38.77% | 621 12.00% 50.76% | 614 11.86% 62.62% | 678 13.10% 75.72% | 630 12.17% 87.89% | 627 12.11% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5177 -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49334 12.48% 12.48% | 49558 12.54% 25.02% | 49523 12.53% 37.55% | 49460 12.52% 50.07% | 49330 12.48% 62.55% | 49103 12.42% 74.98% | 49485 12.52% 87.50% | 49409 12.50% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 395202 -system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Load::total 1 -system.ruby.L1Cache_Controller.OI.Fwd_GETX | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 4 -system.ruby.L1Cache_Controller.OI.Fwd_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 42.86% 42.86% | 3 42.86% 85.71% | 1 14.29% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 7 -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 250 12.60% 12.60% | 256 12.90% 25.50% | 257 12.95% 38.46% | 243 12.25% 50.71% | 233 11.74% 62.45% | 254 12.80% 75.25% | 253 12.75% 88.00% | 238 12.00% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1984 -system.ruby.L1Cache_Controller.OI.Writeback_Nack | 18 16.82% 16.82% | 13 12.15% 28.97% | 11 10.28% 39.25% | 13 12.15% 51.40% | 12 11.21% 62.62% | 16 14.95% 77.57% | 13 12.15% 89.72% | 11 10.28% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 107 -system.ruby.L1Cache_Controller.MI.Load | 2 18.18% 18.18% | 2 18.18% 36.36% | 0 0.00% 36.36% | 0 0.00% 36.36% | 6 54.55% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 11 -system.ruby.L1Cache_Controller.MI.Store | 7 87.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MI.Store::total 8 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 131 12.51% 12.51% | 131 12.51% 25.02% | 150 14.33% 39.35% | 130 12.42% 51.77% | 139 13.28% 65.04% | 116 11.08% 76.12% | 123 11.75% 87.87% | 127 12.13% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1047 -system.ruby.L1Cache_Controller.MI.Fwd_GETS | 251 12.63% 12.63% | 256 12.88% 25.50% | 258 12.98% 38.48% | 244 12.27% 50.75% | 233 11.72% 62.47% | 255 12.83% 75.30% | 253 12.73% 88.03% | 238 11.97% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1988 -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27370 12.37% 12.37% | 27525 12.44% 24.81% | 27467 12.42% 37.23% | 27740 12.54% 49.77% | 27850 12.59% 62.36% | 27840 12.58% 74.94% | 27780 12.56% 87.50% | 27661 12.50% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 221233 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 2 18.18% 18.18% | 2 18.18% 36.36% | 2 18.18% 54.55% | 3 27.27% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 11 -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 132 12.62% 12.62% | 130 12.43% 25.05% | 151 14.44% 39.48% | 131 12.52% 52.01% | 139 13.29% 65.30% | 116 11.09% 76.39% | 120 11.47% 87.86% | 127 12.14% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1046 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 229 13.32% 13.32% | 230 13.38% 26.70% | 200 11.63% 38.34% | 207 12.04% 50.38% | 199 11.58% 61.95% | 201 11.69% 73.65% | 213 12.39% 86.04% | 240 13.96% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1719 -system.ruby.L2Cache_Controller.L1_GETS 504171 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 275912 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTO 107 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 259606 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 476434 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS 25911 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 221202 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 615574 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 395202 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 223217 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 221184 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 408438 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 224639 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 691372 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 394374 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 218066 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETS 3279 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETX 1785 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 391942 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS 3260 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETS 2226 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETX 1172 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 222279 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTS 1711 0.00% 0.00% +system.ruby.ST.miss_latency_hist::samples 224056 +system.ruby.ST.miss_latency_hist::mean 1522.834657 +system.ruby.ST.miss_latency_hist::gmean 1029.834307 +system.ruby.ST.miss_latency_hist::stdev 1493.434693 +system.ruby.ST.miss_latency_hist | 169268 75.55% 75.55% | 39205 17.50% 93.05% | 11302 5.04% 98.09% | 3287 1.47% 99.56% | 782 0.35% 99.91% | 163 0.07% 99.98% | 42 0.02% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 224056 +system.ruby.Directory_Controller.GETX 222195 0.00% 0.00% +system.ruby.Directory_Controller.GETS 393916 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 222083 0.00% 0.00% +system.ruby.Directory_Controller.PUTO_SHARERS 88 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 143328 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 250580 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 222184 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 222163 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 616104 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 222163 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 80051 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 143331 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 221891 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 142138 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 250585 0.00% 0.00% +system.ruby.Directory_Controller.S.Memory_Ack 88 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 222083 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTO_SHARERS 88 0.00% 0.00% +system.ruby.Directory_Controller.IS.GETX 2 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 143328 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 143331 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Ack 114 0.00% 0.00% +system.ruby.Directory_Controller.SS.GETX 4 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 250580 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 250584 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 222184 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 222189 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 70 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 222075 0.00% 0.00% +system.ruby.Directory_Controller.MIS.Dirty_Writeback 88 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50337 12.48% 12.48% | 50334 12.48% 24.96% | 50658 12.56% 37.52% | 50226 12.45% 49.98% | 50303 12.47% 62.45% | 50420 12.50% 74.95% | 50532 12.53% 87.48% | 50481 12.52% 100.00% +system.ruby.L1Cache_Controller.Load::total 403291 +system.ruby.L1Cache_Controller.Store | 28208 12.59% 12.59% | 27932 12.46% 25.05% | 28122 12.55% 37.60% | 28217 12.59% 50.19% | 27953 12.47% 62.66% | 28062 12.52% 75.19% | 27780 12.40% 87.58% | 27829 12.42% 100.00% +system.ruby.L1Cache_Controller.Store::total 224103 +system.ruby.L1Cache_Controller.L1_Replacement | 9443995 12.50% 12.50% | 9453005 12.51% 25.00% | 9433466 12.48% 37.49% | 9447264 12.50% 49.99% | 9453992 12.51% 62.50% | 9447610 12.50% 75.00% | 9447185 12.50% 87.50% | 9448753 12.50% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 75575270 +system.ruby.L1Cache_Controller.Fwd_GETX | 172 13.43% 13.43% | 152 11.87% 25.29% | 173 13.51% 38.80% | 175 13.66% 52.46% | 143 11.16% 63.62% | 143 11.16% 74.79% | 173 13.51% 88.29% | 150 11.71% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1281 +system.ruby.L1Cache_Controller.Fwd_GETS | 662 11.73% 11.73% | 742 13.15% 24.88% | 690 12.23% 37.10% | 726 12.86% 49.96% | 704 12.47% 62.44% | 735 13.02% 75.46% | 695 12.31% 87.77% | 690 12.23% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 5644 +system.ruby.L1Cache_Controller.Inv | 227 12.74% 12.74% | 219 12.29% 25.03% | 265 14.87% 39.90% | 212 11.90% 51.80% | 217 12.18% 63.97% | 227 12.74% 76.71% | 205 11.50% 88.22% | 210 11.78% 100.00% +system.ruby.L1Cache_Controller.Inv::total 1782 +system.ruby.L1Cache_Controller.Ack | 389 13.23% 13.23% | 360 12.24% 25.48% | 373 12.69% 38.16% | 359 12.21% 50.37% | 367 12.48% 62.86% | 348 11.84% 74.69% | 379 12.89% 87.59% | 365 12.41% 100.00% +system.ruby.L1Cache_Controller.Ack::total 2940 +system.ruby.L1Cache_Controller.Data | 50111 12.48% 12.48% | 50127 12.48% 24.96% | 50476 12.57% 37.53% | 49986 12.45% 49.98% | 50074 12.47% 62.45% | 50206 12.50% 74.96% | 50292 12.52% 87.48% | 50265 12.52% 100.00% +system.ruby.L1Cache_Controller.Data::total 401537 +system.ruby.L1Cache_Controller.Exclusive_Data | 28409 12.59% 12.59% | 28119 12.46% 25.05% | 28290 12.54% 37.59% | 28420 12.59% 50.18% | 28155 12.48% 62.66% | 28261 12.52% 75.18% | 27986 12.40% 87.58% | 28018 12.42% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 225658 +system.ruby.L1Cache_Controller.Writeback_Ack | 641 12.65% 12.65% | 619 12.22% 24.87% | 587 11.58% 36.45% | 628 12.39% 48.85% | 671 13.24% 62.09% | 695 13.72% 75.80% | 609 12.02% 87.82% | 617 12.18% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 5067 +system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77592 12.52% 12.52% | 77349 12.48% 24.99% | 77854 12.56% 37.55% | 77513 12.50% 50.06% | 77289 12.47% 62.53% | 77502 12.50% 75.03% | 77405 12.49% 87.51% | 77395 12.49% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 619899 +system.ruby.L1Cache_Controller.Writeback_Nack | 231 12.62% 12.62% | 221 12.08% 24.70% | 270 14.75% 39.45% | 217 11.86% 51.31% | 215 11.75% 63.06% | 239 13.06% 76.12% | 208 11.37% 87.49% | 229 12.51% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 1830 +system.ruby.L1Cache_Controller.All_acks | 28205 12.59% 12.59% | 27927 12.46% 25.05% | 28121 12.55% 37.60% | 28205 12.59% 50.19% | 27950 12.47% 62.67% | 28061 12.52% 75.19% | 27773 12.40% 87.59% | 27814 12.41% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 224056 +system.ruby.L1Cache_Controller.Use_Timeout | 28409 12.59% 12.59% | 28119 12.46% 25.05% | 28289 12.54% 37.59% | 28420 12.59% 50.18% | 28153 12.48% 62.66% | 28260 12.52% 75.18% | 27986 12.40% 87.58% | 28018 12.42% 100.00% +system.ruby.L1Cache_Controller.Use_Timeout::total 225654 +system.ruby.L1Cache_Controller.I.Load | 50316 12.48% 12.48% | 50322 12.48% 24.96% | 50646 12.56% 37.52% | 50205 12.45% 49.98% | 50279 12.47% 62.45% | 50408 12.50% 74.95% | 50508 12.53% 87.48% | 50472 12.52% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 403156 +system.ruby.L1Cache_Controller.I.Store | 28202 12.59% 12.59% | 27928 12.47% 25.05% | 28118 12.55% 37.60% | 28202 12.59% 50.19% | 27949 12.47% 62.67% | 28059 12.52% 75.19% | 27773 12.40% 87.59% | 27813 12.41% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 224044 +system.ruby.L1Cache_Controller.I.L1_Replacement | 60 12.63% 12.63% | 69 14.53% 27.16% | 62 13.05% 40.21% | 57 12.00% 52.21% | 56 11.79% 64.00% | 50 10.53% 74.53% | 62 13.05% 87.58% | 59 12.42% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 475 +system.ruby.L1Cache_Controller.S.Load | 3 9.68% 9.68% | 4 12.90% 22.58% | 3 9.68% 32.26% | 8 25.81% 58.06% | 3 9.68% 67.74% | 3 9.68% 77.42% | 3 9.68% 87.10% | 4 12.90% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 31 +system.ruby.L1Cache_Controller.S.Store | 5 26.32% 26.32% | 0 0.00% 26.32% | 3 15.79% 42.11% | 3 15.79% 57.89% | 3 15.79% 73.68% | 2 10.53% 84.21% | 1 5.26% 89.47% | 2 10.53% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 19 +system.ruby.L1Cache_Controller.S.L1_Replacement | 50098 12.48% 12.48% | 50115 12.48% 24.96% | 50464 12.57% 37.53% | 49973 12.45% 49.98% | 50061 12.47% 62.45% | 50192 12.50% 74.95% | 50285 12.53% 87.48% | 50259 12.52% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 401447 +system.ruby.L1Cache_Controller.S.Fwd_GETS | 39 10.92% 10.92% | 61 17.09% 28.01% | 35 9.80% 37.82% | 49 13.73% 51.54% | 47 13.17% 64.71% | 45 12.61% 77.31% | 46 12.89% 90.20% | 35 9.80% 100.00% +system.ruby.L1Cache_Controller.S.Fwd_GETS::total 357 +system.ruby.L1Cache_Controller.S.Inv | 7 10.29% 10.29% | 12 17.65% 27.94% | 8 11.76% 39.71% | 10 14.71% 54.41% | 10 14.71% 69.12% | 11 16.18% 85.29% | 6 8.82% 94.12% | 4 5.88% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 68 +system.ruby.L1Cache_Controller.O.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 57.14% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 7 +system.ruby.L1Cache_Controller.M.L1_Replacement | 202 12.69% 12.69% | 192 12.06% 24.75% | 165 10.36% 35.11% | 215 13.51% 48.62% | 204 12.81% 61.43% | 199 12.50% 73.93% | 211 13.25% 87.19% | 204 12.81% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 1592 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 3 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 57.14% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 7 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 548 12.10% 12.10% | 971 21.44% 33.54% | 579 12.78% 46.32% | 280 6.18% 52.51% | 482 10.64% 63.15% | 351 7.75% 70.90% | 809 17.86% 88.76% | 509 11.24% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 4529 +system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 4 80.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 5 +system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 50.00% 50.00% | 0 0.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 8 +system.ruby.L1Cache_Controller.M_W.Use_Timeout | 204 12.73% 12.73% | 192 11.99% 24.72% | 169 10.55% 35.27% | 215 13.42% 48.69% | 205 12.80% 61.49% | 200 12.48% 73.97% | 213 13.30% 87.27% | 204 12.73% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1602 +system.ruby.L1Cache_Controller.MM.Load | 2 16.67% 16.67% | 1 8.33% 25.00% | 3 25.00% 50.00% | 1 8.33% 58.33% | 1 8.33% 66.67% | 2 16.67% 83.33% | 1 8.33% 91.67% | 1 8.33% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 12 +system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 4 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 28154 12.59% 12.59% | 27870 12.46% 25.05% | 28065 12.55% 37.60% | 28158 12.59% 50.19% | 27902 12.48% 62.67% | 28022 12.53% 75.19% | 27717 12.39% 87.59% | 27759 12.41% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 223647 +system.ruby.L1Cache_Controller.MM.Fwd_GETX | 15 10.49% 10.49% | 20 13.99% 24.48% | 17 11.89% 36.36% | 16 11.19% 47.55% | 14 9.79% 57.34% | 10 6.99% 64.34% | 25 17.48% 81.82% | 26 18.18% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 143 +system.ruby.L1Cache_Controller.MM.Fwd_GETS | 36 13.79% 13.79% | 37 14.18% 27.97% | 37 14.18% 42.15% | 31 11.88% 54.02% | 32 12.26% 66.28% | 28 10.73% 77.01% | 31 11.88% 88.89% | 29 11.11% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 261 +system.ruby.L1Cache_Controller.MM_W.Load | 2 8.33% 8.33% | 6 25.00% 33.33% | 4 16.67% 50.00% | 3 12.50% 62.50% | 4 16.67% 79.17% | 3 12.50% 91.67% | 0 0.00% 91.67% | 2 8.33% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 24 +system.ruby.L1Cache_Controller.MM_W.Store | 1 9.09% 9.09% | 3 27.27% 36.36% | 1 9.09% 45.45% | 0 0.00% 45.45% | 0 0.00% 45.45% | 1 9.09% 54.55% | 2 18.18% 72.73% | 3 27.27% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 11 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 618517 12.51% 12.51% | 616680 12.47% 24.98% | 619593 12.53% 37.52% | 616079 12.46% 49.98% | 621287 12.57% 62.55% | 617144 12.48% 75.03% | 615748 12.45% 87.48% | 618786 12.52% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4943834 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 16 13.56% 13.56% | 17 14.41% 27.97% | 24 20.34% 48.31% | 20 16.95% 65.25% | 11 9.32% 74.58% | 8 6.78% 81.36% | 17 14.41% 95.76% | 5 4.24% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 118 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 26 10.20% 10.20% | 31 12.16% 22.35% | 32 12.55% 34.90% | 38 14.90% 49.80% | 31 12.16% 61.96% | 46 18.04% 80.00% | 26 10.20% 90.20% | 25 9.80% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 255 +system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 28205 12.59% 12.59% | 27927 12.46% 25.05% | 28120 12.55% 37.60% | 28205 12.59% 50.19% | 27948 12.47% 62.67% | 28060 12.52% 75.19% | 27773 12.40% 87.59% | 27814 12.41% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 224052 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 3149997 12.52% 12.52% | 3186048 12.66% 25.18% | 3123041 12.41% 37.60% | 3135752 12.46% 50.06% | 3137292 12.47% 62.53% | 3156543 12.55% 75.07% | 3113373 12.37% 87.45% | 3158021 12.55% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 25160067 +system.ruby.L1Cache_Controller.IM.Ack | 153 13.21% 13.21% | 144 12.44% 25.65% | 157 13.56% 39.21% | 146 12.61% 51.81% | 136 11.74% 63.56% | 131 11.31% 74.87% | 149 12.87% 87.74% | 142 12.26% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1158 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 28200 12.59% 12.59% | 27927 12.47% 25.05% | 28118 12.55% 37.60% | 28202 12.59% 50.19% | 27947 12.47% 62.67% | 28059 12.52% 75.19% | 27772 12.40% 87.59% | 27812 12.41% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 224037 +system.ruby.L1Cache_Controller.SM.L1_Replacement | 798 28.74% 28.74% | 0 0.00% 28.74% | 138 4.97% 33.71% | 597 21.50% 55.20% | 695 25.03% 80.23% | 276 9.94% 90.17% | 135 4.86% 95.03% | 138 4.97% 100.00% +system.ruby.L1Cache_Controller.SM.L1_Replacement::total 2777 +system.ruby.L1Cache_Controller.SM.Exclusive_Data | 5 26.32% 26.32% | 0 0.00% 26.32% | 3 15.79% 42.11% | 3 15.79% 57.89% | 3 15.79% 73.68% | 2 10.53% 84.21% | 1 5.26% 89.47% | 2 10.53% 100.00% +system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 19 +system.ruby.L1Cache_Controller.OM.L1_Replacement | 22088 12.82% 12.82% | 21719 12.61% 25.43% | 21701 12.60% 38.02% | 20594 11.95% 49.98% | 21388 12.41% 62.39% | 21743 12.62% 75.01% | 21703 12.60% 87.61% | 21346 12.39% 100.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement::total 172282 +system.ruby.L1Cache_Controller.OM.Ack | 236 13.24% 13.24% | 216 12.12% 25.36% | 216 12.12% 37.49% | 213 11.95% 49.44% | 231 12.96% 62.40% | 217 12.18% 74.58% | 230 12.91% 87.49% | 223 12.51% 100.00% +system.ruby.L1Cache_Controller.OM.Ack::total 1782 +system.ruby.L1Cache_Controller.OM.All_acks | 28205 12.59% 12.59% | 27927 12.46% 25.05% | 28121 12.55% 37.60% | 28205 12.59% 50.19% | 27950 12.47% 62.67% | 28061 12.52% 75.19% | 27773 12.40% 87.59% | 27814 12.41% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks::total 224056 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 5573533 12.48% 12.48% | 5549341 12.42% 24.90% | 5589654 12.51% 37.42% | 5595559 12.53% 49.95% | 5594624 12.53% 62.47% | 5573090 12.48% 74.95% | 5617140 12.58% 87.53% | 5571672 12.47% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44664613 +system.ruby.L1Cache_Controller.IS.Data | 50111 12.48% 12.48% | 50127 12.48% 24.96% | 50476 12.57% 37.53% | 49986 12.45% 49.98% | 50074 12.47% 62.45% | 50206 12.50% 74.96% | 50292 12.52% 87.48% | 50265 12.52% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 401537 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 204 12.73% 12.73% | 192 11.99% 24.72% | 169 10.55% 35.27% | 215 13.42% 48.69% | 205 12.80% 61.49% | 200 12.48% 73.97% | 213 13.30% 87.27% | 204 12.73% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1602 +system.ruby.L1Cache_Controller.SI.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 4.00% 4.00% | 9 18.00% 22.00% | 16 32.00% 54.00% | 3 6.00% 60.00% | 18 36.00% 96.00% | 2 4.00% 100.00% +system.ruby.L1Cache_Controller.SI.Load::total 50 +system.ruby.L1Cache_Controller.SI.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 78.57% 78.57% | 1 7.14% 85.71% | 0 0.00% 85.71% | 2 14.29% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SI.Store::total 14 +system.ruby.L1Cache_Controller.SI.Fwd_GETS | 359 12.43% 12.43% | 363 12.56% 24.99% | 353 12.22% 37.21% | 354 12.25% 49.46% | 367 12.70% 62.17% | 374 12.95% 75.11% | 351 12.15% 87.26% | 368 12.74% 100.00% +system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2889 +system.ruby.L1Cache_Controller.SI.Inv | 220 12.84% 12.84% | 207 12.08% 24.91% | 257 14.99% 39.91% | 202 11.79% 51.69% | 207 12.08% 63.77% | 216 12.60% 76.37% | 199 11.61% 87.98% | 206 12.02% 100.00% +system.ruby.L1Cache_Controller.SI.Inv::total 1714 +system.ruby.L1Cache_Controller.SI.Writeback_Ack | 639 12.63% 12.63% | 618 12.22% 24.85% | 587 11.60% 36.45% | 627 12.39% 48.84% | 670 13.24% 62.09% | 694 13.72% 75.81% | 607 12.00% 87.80% | 617 12.20% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5059 +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49238 12.48% 12.48% | 49289 12.49% 24.96% | 49620 12.57% 37.54% | 49140 12.45% 49.99% | 49183 12.46% 62.45% | 49282 12.49% 74.94% | 49477 12.54% 87.47% | 49432 12.53% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 394661 +system.ruby.L1Cache_Controller.OI.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 3 +system.ruby.L1Cache_Controller.OI.Fwd_GETS | 1 11.11% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 1 11.11% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 9 +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 201 10.79% 10.79% | 249 13.37% 24.17% | 227 12.19% 36.36% | 252 13.53% 49.89% | 225 12.08% 61.98% | 240 12.89% 74.87% | 235 12.62% 87.49% | 233 12.51% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1862 +system.ruby.L1Cache_Controller.OI.Writeback_Nack | 12 9.76% 9.76% | 15 12.20% 21.95% | 13 10.57% 32.52% | 16 13.01% 45.53% | 9 7.32% 52.85% | 24 19.51% 72.36% | 11 8.94% 81.30% | 23 18.70% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 123 +system.ruby.L1Cache_Controller.MI.Load | 14 77.78% 77.78% | 1 5.56% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 1 5.56% 88.89% | 2 11.11% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 18 +system.ruby.L1Cache_Controller.MI.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 9.09% 9.09% | 10 90.91% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 11 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 135 13.38% 13.38% | 115 11.40% 24.78% | 132 13.08% 37.86% | 138 13.68% 51.54% | 118 11.69% 63.23% | 123 12.19% 75.42% | 129 12.78% 88.21% | 119 11.79% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1009 +system.ruby.L1Cache_Controller.MI.Fwd_GETS | 201 10.82% 10.82% | 249 13.40% 24.22% | 223 12.00% 36.22% | 253 13.62% 49.84% | 224 12.06% 61.89% | 240 12.92% 74.81% | 235 12.65% 87.46% | 233 12.54% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1858 +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 28019 12.60% 12.60% | 27696 12.46% 25.06% | 27875 12.54% 37.59% | 27982 12.58% 50.18% | 27763 12.49% 62.66% | 27857 12.53% 75.19% | 27562 12.39% 87.58% | 27611 12.42% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 222365 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 2 25.00% 25.00% | 1 12.50% 37.50% | 0 0.00% 37.50% | 1 12.50% 50.00% | 1 12.50% 62.50% | 1 12.50% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 8 +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 134 13.25% 13.25% | 115 11.37% 24.63% | 132 13.06% 37.69% | 139 13.75% 51.43% | 118 11.67% 63.11% | 123 12.17% 75.27% | 131 12.96% 88.23% | 119 11.77% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1011 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 219 12.83% 12.83% | 206 12.07% 24.90% | 257 15.06% 39.95% | 201 11.78% 51.73% | 206 12.07% 63.80% | 215 12.60% 76.39% | 197 11.54% 87.93% | 206 12.07% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1707 +system.ruby.L2Cache_Controller.L1_GETS 503138 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 276686 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTO 151 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 258242 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS_only 474368 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS 25708 0.00% 0.00% +system.ruby.L2Cache_Controller.All_Acks 222189 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 616104 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 394660 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 224227 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Ack 222163 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 407610 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 225655 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 688531 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 393916 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 219009 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_GETS 3246 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_GETX 1771 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 391425 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS 3236 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETS 2126 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETX 1155 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTX 223374 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTS 1701 0.00% 0.00% system.ruby.L2Cache_Controller.ILOX.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTO 107 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTX 107 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETX 4 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1877 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 108 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 9 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS 2539 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1344 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 391315 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_GETS 7 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_GETX 6 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTO 124 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTX 123 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETS 8 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 6 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1734 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 126 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 5 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS 2480 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETX 1391 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 390802 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_GETS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_GETX 3 0.00% 0.00% system.ruby.L2Cache_Controller.OLSX.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1766 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS 14 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L2_Replacement 105 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETS 19 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETX 8 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3262 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS 29 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L2_Replacement 2529 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1286 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 733 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_PUTX 4 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_PUTS 3 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 221085 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_GETS 16 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1506 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 107 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.Unblock 108 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 63 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 22 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 51 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4580 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 40 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1877 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.Unblock 9 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.L1_PUTS 181 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.Unblock 29 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.L2_Replacement 216 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_GETS 182 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_GETX 38 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_PUTS 12129 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3260 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETS 17001 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETX 8674 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 391942 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L1_GETS 85 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L1_GETX 48 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.Unblock 3262 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L2_Replacement 23310 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETS 53 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETX 13 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.Unblock 1766 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L2_Replacement 9523 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 36 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.Unblock 14 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 30 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETS 5974 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETX 3491 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1648 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTS 55 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 221233 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.Unblock 1046 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_GETS 334 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_GETX 125 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28471 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS 247 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.Unblock 3279 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 52 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1647 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS 16 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L2_Replacement 88 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_GETS 17 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_GETX 18 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3252 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS 21 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L2_Replacement 2446 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1341 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 707 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_PUTS 5 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 222083 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETS 26 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETX 12 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 15 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1699 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 124 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.Unblock 126 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 19 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 20 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 59 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4363 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 74 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1738 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.Unblock 7 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.L1_PUTS 89 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.Unblock 21 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.L2_Replacement 141 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_GETS 65 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_GETX 121 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_PUTS 11842 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3236 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETS 15784 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETX 9344 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 391424 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L1_GETS 45 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L1_GETX 72 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.Unblock 3252 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L2_Replacement 22439 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETS 62 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETX 48 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_PUTS 4 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.Unblock 1647 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L2_Replacement 8842 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L1_PUTS_only 16 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 57 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.Unblock 16 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 111 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETS 6740 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETX 3780 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1295 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTS 64 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 222365 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.Unblock 1009 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_GETS 203 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_GETX 132 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28304 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_PUTS 196 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.Unblock 3246 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTO 6 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 21 0.00% 0.00% system.ruby.L2Cache_Controller.IFLOX.Unblock 1 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 6 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 176 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 102 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 31904 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 233 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Unblock 1988 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1410 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 66 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 27 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.Unblock 6 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 52 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only 27 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 4 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETS 48391 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETX 25584 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_PUTS 7638 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 394372 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 394365 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETS 21742 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETX 11283 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 219409 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_GETS 259 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_GETX 100 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 29748 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 186 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.Data 1793 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETS 5594 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETX 2911 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTX 103 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16081 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS 139 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 221202 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 221200 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 733 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 42 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.Unblock 2539 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 31218 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETX 8 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1286 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L2_Replacement 11948 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.Unblock 7 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 44 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.Unblock 19 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.L2_Replacement 93 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETS 522 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETX 392 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 221079 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 326 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 105 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 3 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 257 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 116 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 29762 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 228 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Unblock 1865 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1417 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 71 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 12 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.Unblock 8 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 31 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only 17 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 2 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETS 48250 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETX 25028 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_PUTS 7780 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data 393915 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Unblock 393909 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETS 21787 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETX 10598 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.Data 220400 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_GETS 223 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_GETX 169 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 28869 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 213 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.Data 1789 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETS 5607 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETX 2837 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTX 93 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16064 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTS 153 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.All_Acks 222189 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 222185 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_GETS 16 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 707 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 81 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 49 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTS 24 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.Unblock 2480 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 28825 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_GETS 30 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_GETX 9 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1341 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L2_Replacement 12721 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 10 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.Unblock 6 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.L2_Replacement 14 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 25 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.Unblock 17 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.L2_Replacement 19 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETS 802 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETX 291 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.Writeback_Ack 222075 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 217 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 88 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index f687bc41a..3f1fbe27c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.005861 # Number of seconds simulated -sim_ticks 5861055 # Number of ticks simulated -final_tick 5861055 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.005821 # Number of seconds simulated +sim_ticks 5821182 # Number of ticks simulated +final_tick 5821182 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 95295 # Simulator tick rate (ticks/s) -host_mem_usage 485672 # Number of bytes of host memory used -host_seconds 61.50 # Real time elapsed on the host +host_tick_rate 68014 # Simulator tick rate (ticks/s) +host_mem_usage 539140 # Number of bytes of host memory used +host_seconds 85.59 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765312 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39765312 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 15548160 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 15548160 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 621333 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 621333 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 242940 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 242940 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 6784667948 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 6784667948 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 2652792031 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 2652792031 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 9437459979 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 9437459979 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 621339 # Number of read requests accepted -system.mem_ctrls.writeReqs 242940 # Number of write requests accepted -system.mem_ctrls.readBursts 621339 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 242940 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39153536 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 612160 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 15348928 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39765696 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 15548160 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 9565 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 3089 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39830912 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39830912 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 15373376 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 15373376 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 622358 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 622358 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 240209 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 240209 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 6842409669 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 6842409669 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 2640937184 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 2640937184 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 9483346853 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 9483346853 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 622368 # Number of read requests accepted +system.mem_ctrls.writeReqs 240209 # Number of write requests accepted +system.mem_ctrls.readBursts 622368 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 240209 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 39210944 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 620416 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 15175936 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39831552 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 15373376 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 9694 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 3049 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76254 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76617 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76129 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 77015 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76504 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76352 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76489 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 76414 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76983 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76321 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76515 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76522 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 77021 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76398 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76334 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 76577 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 29636 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 29880 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 29803 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 30173 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 29938 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 30411 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 29999 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 29987 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 29953 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 29528 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 29532 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 29603 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 29785 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 29746 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 29543 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 29434 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,53 +69,53 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5861029 # Total gap between requests +system.mem_ctrls.totGap 5821160 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 621339 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 622368 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 242940 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 9448 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 13046 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 16459 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 19563 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 24246 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 30435 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 36606 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 40256 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 38769 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 34745 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 30104 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 27475 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 26332 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 25691 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 24671 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 23610 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 22181 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 20983 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 19870 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 19241 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 18435 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 17866 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 16962 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 15619 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 13591 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 10815 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 7536 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 4396 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 1996 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 660 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 148 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 19 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 240209 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 8340 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 11906 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 15620 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 18559 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 22953 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 29117 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 35827 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 40200 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 40426 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 36509 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 31650 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 28573 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 27266 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 26251 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 25235 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 24021 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 22472 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 20919 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 19841 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 19049 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 18234 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 17567 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 16593 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 15420 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 13597 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 10982 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 7856 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 4648 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 2127 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 716 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 185 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 15 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -131,1004 +131,991 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 73 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 151 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 586 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 1517 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2905 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 4724 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 6770 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8830 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 11052 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 13013 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 14849 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 16609 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 15329 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 15883 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 16471 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 16826 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 16956 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 17389 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 9252 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 7590 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 6450 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 5313 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 4590 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 3886 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 3409 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 2927 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 2474 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 2164 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 1800 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 1622 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 1458 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 1210 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 1075 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 934 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 800 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 700 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 609 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 543 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 426 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 388 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 170 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 52 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 26 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 145 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 507 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 1367 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2635 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 4148 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 6053 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 7858 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9893 # What write queue length does an incoming req see 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+system.mem_ctrls.wrQLenPdf::35 7255 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 6262 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 5386 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 4562 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 4004 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 3425 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 3067 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 2622 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 2219 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 2015 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 1837 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 1650 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 1349 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 1177 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 1078 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 952 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 768 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 624 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 554 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 456 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 249 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 81 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 12 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 250748 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 217.354922 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 175.083790 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 148.722121 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 50160 20.00% 20.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 107083 42.71% 62.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 54285 21.65% 84.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 23329 9.30% 93.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 9881 3.94% 97.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3756 1.50% 99.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1424 0.57% 99.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 540 0.22% 99.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 290 0.12% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 250748 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 14683 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 41.663420 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 37.948654 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 17.513815 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 305 2.08% 2.08% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 32 0.22% 2.30% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 27 0.18% 2.48% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 3189 21.72% 24.20% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 6160 41.95% 66.15% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 1671 11.38% 77.53% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 181 1.23% 78.76% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 914 6.22% 84.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 1223 8.33% 93.32% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 546 3.72% 97.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 109 0.74% 97.78% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 91 0.62% 98.40% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 107 0.73% 99.13% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::104-111 71 0.48% 99.61% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::112-119 20 0.14% 99.75% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 25 0.17% 99.92% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::128-135 9 0.06% 99.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::136-143 2 0.01% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::144-151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 14683 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 14683 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.333651 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.292472 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.288313 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13340 90.85% 90.85% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 298 2.03% 92.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 249 1.70% 94.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 199 1.36% 95.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 179 1.22% 97.15% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 145 0.99% 98.14% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 82 0.56% 98.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 86 0.59% 99.28% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 47 0.32% 99.60% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 28 0.19% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 10 0.07% 99.86% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 9 0.06% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 5 0.03% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 1 0.01% 99.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 4 0.03% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 14683 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 62104397 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 73728103 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3058870 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 101.52 # Average queueing delay per DRAM burst +system.mem_ctrls.wrQLenPdf::62 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 249951 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 217.586583 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 175.307455 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 148.799547 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 49763 19.91% 19.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 106960 42.79% 62.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 53993 21.60% 84.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 23277 9.31% 93.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 9836 3.94% 97.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3899 1.56% 99.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1418 0.57% 99.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 526 0.21% 99.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 279 0.11% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 249951 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 14538 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 42.137914 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 38.248629 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 18.048368 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 307 2.11% 2.11% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 22 0.15% 2.26% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 34 0.23% 2.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 3134 21.56% 24.05% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 5983 41.15% 65.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 1658 11.40% 76.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 202 1.39% 78.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 833 5.73% 83.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 1284 8.83% 92.56% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 590 4.06% 96.62% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 132 0.91% 97.53% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 100 0.69% 98.22% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-103 121 0.83% 99.05% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::104-111 64 0.44% 99.49% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 33 0.23% 99.72% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::120-127 26 0.18% 99.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-135 8 0.06% 99.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::136-143 4 0.03% 99.98% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::144-151 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::152-159 2 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 14538 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 14538 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.310634 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.272693 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.237976 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13255 91.17% 91.17% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 312 2.15% 93.32% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 225 1.55% 94.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 219 1.51% 96.38% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 170 1.17% 97.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 124 0.85% 98.40% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 76 0.52% 98.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 56 0.39% 99.31% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 38 0.26% 99.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 29 0.20% 99.77% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 13 0.09% 99.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 10 0.07% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 6 0.04% 99.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 2 0.01% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 14538 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 62772430 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 74413179 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3063355 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 102.46 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 120.52 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 6680.29 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 2618.80 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 6784.73 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 2652.79 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 121.46 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 6735.91 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 2607.02 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 6842.52 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 2640.94 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 72.65 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 52.19 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 20.46 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 15.37 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 30.05 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 366603 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 234242 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 59.92 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.66 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 6.78 # Average gap between requests -system.mem_ctrls.pageHitRate 70.55 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1894029480 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 1052238600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7627626240 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2483809920 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 382437120 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 3990635208 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 12680400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 17443456968 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 2979.039670 # Core power per rank (mW) +system.mem_ctrls.busUtil 72.99 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 52.62 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 20.37 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 15.56 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 30.72 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 367791 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 232046 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 60.03 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.84 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 6.75 # Average gap between requests +system.mem_ctrls.pageHitRate 70.58 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1887996600 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1048887000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7639681920 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2456438400 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 379894320 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3964067964 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 12588600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 17389554804 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2989.744313 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 195520 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 194220 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 5659868 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 5622174 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 382437120 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 126534528 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3402195600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3911167248 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.968375 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5659812 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 195520 # Time in different power states +system.mem_ctrls_1.refreshEnergy 379894320 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 125693208 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3379575600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3885163128 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.968356 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5622182 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 194220 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 98982 # number of read accesses completed -system.cpu0.num_writes 55308 # number of write accesses completed -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 55392 # number of write accesses completed -system.cpu2.num_reads 99114 # number of read accesses completed -system.cpu2.num_writes 55497 # number of write accesses completed -system.cpu3.num_reads 99168 # number of read accesses completed -system.cpu3.num_writes 55352 # number of write accesses completed -system.cpu4.num_reads 99493 # number of read accesses completed -system.cpu4.num_writes 54983 # number of write accesses completed -system.cpu5.num_reads 99075 # number of read accesses completed -system.cpu5.num_writes 55346 # number of write accesses completed -system.cpu6.num_reads 99096 # number of read accesses completed -system.cpu6.num_writes 54949 # number of write accesses completed -system.cpu7.num_reads 99018 # number of read accesses completed -system.cpu7.num_writes 54930 # number of write accesses completed +system.cpu0.num_reads 99759 # number of read accesses completed +system.cpu0.num_writes 55062 # number of write accesses completed +system.cpu1.num_reads 99676 # number of read accesses completed +system.cpu1.num_writes 56012 # number of write accesses completed +system.cpu2.num_reads 99760 # number of read accesses completed +system.cpu2.num_writes 55397 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55911 # number of write accesses completed +system.cpu4.num_reads 99280 # number of read accesses completed +system.cpu4.num_writes 54878 # number of write accesses completed +system.cpu5.num_reads 99419 # number of read accesses completed +system.cpu5.num_writes 55605 # number of write accesses completed +system.cpu6.num_reads 99512 # number of read accesses completed +system.cpu6.num_writes 55332 # number of write accesses completed +system.cpu7.num_reads 99101 # number of read accesses completed +system.cpu7.num_writes 55293 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 625828 -system.ruby.outstanding_req_hist::mean 15.998460 -system.ruby.outstanding_req_hist::gmean 15.997194 -system.ruby.outstanding_req_hist::stdev 0.125917 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 20 0.00% 0.02% | 625704 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 625828 +system.ruby.outstanding_req_hist::samples 626798 +system.ruby.outstanding_req_hist::mean 15.998464 +system.ruby.outstanding_req_hist::gmean 15.997200 +system.ruby.outstanding_req_hist::stdev 0.125813 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 19 0.00% 0.02% | 626675 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 626798 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 625700 -system.ruby.latency_hist::mean 1198.832377 -system.ruby.latency_hist::gmean 899.836581 -system.ruby.latency_hist::stdev 764.001734 -system.ruby.latency_hist | 168514 26.93% 26.93% | 119446 19.09% 46.02% | 111629 17.84% 63.86% | 119695 19.13% 82.99% | 84495 13.50% 96.50% | 20461 3.27% 99.77% | 1425 0.23% 99.99% | 34 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 625700 +system.ruby.latency_hist::samples 626670 +system.ruby.latency_hist::mean 1188.866103 +system.ruby.latency_hist::gmean 895.172071 +system.ruby.latency_hist::stdev 753.817957 +system.ruby.latency_hist | 168975 26.96% 26.96% | 120052 19.16% 46.12% | 115384 18.41% 64.53% | 120399 19.21% 83.75% | 82434 13.15% 96.90% | 18213 2.91% 99.81% | 1198 0.19% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 626670 system.ruby.hit_latency_hist::bucket_size 512 system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 2941 -system.ruby.hit_latency_hist::mean 1072.636858 -system.ruby.hit_latency_hist::gmean 541.560950 -system.ruby.hit_latency_hist::stdev 789.424392 -system.ruby.hit_latency_hist | 996 33.87% 33.87% | 480 16.32% 50.19% | 522 17.75% 67.94% | 531 18.06% 85.99% | 338 11.49% 97.48% | 68 2.31% 99.80% | 6 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2941 +system.ruby.hit_latency_hist::samples 2921 +system.ruby.hit_latency_hist::mean 1087.767203 +system.ruby.hit_latency_hist::gmean 544.065854 +system.ruby.hit_latency_hist::stdev 803.453196 +system.ruby.hit_latency_hist | 965 33.04% 33.04% | 498 17.05% 50.09% | 495 16.95% 67.03% | 523 17.90% 84.94% | 350 11.98% 96.92% | 84 2.88% 99.79% | 6 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 2921 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 622759 -system.ruby.miss_latency_hist::mean 1199.428339 -system.ruby.miss_latency_hist::gmean 901.996890 -system.ruby.miss_latency_hist::stdev 763.830861 -system.ruby.miss_latency_hist | 167518 26.90% 26.90% | 118966 19.10% 46.00% | 111107 17.84% 63.84% | 119164 19.13% 82.98% | 84157 13.51% 96.49% | 20393 3.27% 99.77% | 1419 0.23% 99.99% | 34 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 622759 -system.ruby.L1Cache.incomplete_times 1274 -system.ruby.Directory.incomplete_times 621482 +system.ruby.miss_latency_hist::samples 623749 +system.ruby.miss_latency_hist::mean 1189.339547 +system.ruby.miss_latency_hist::gmean 897.261928 +system.ruby.miss_latency_hist::stdev 753.546605 +system.ruby.miss_latency_hist | 168010 26.94% 26.94% | 119554 19.17% 46.10% | 114889 18.42% 64.52% | 119876 19.22% 83.74% | 82084 13.16% 96.90% | 18129 2.91% 99.81% | 1192 0.19% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 623749 +system.ruby.L1Cache.incomplete_times 1208 +system.ruby.Directory.incomplete_times 622538 system.ruby.l1_cntrl0.L1Dcache.demand_hits 27 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78075 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78102 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78497 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78524 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 24 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78760 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78784 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78630 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78649 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 24 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78362 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78386 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 16 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78235 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78251 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 23 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78022 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78045 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78633 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78653 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Dcache.demand_hits 25 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78196 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78221 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Dcache.demand_hits 22 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78239 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78261 # Number of cache demand accesses system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Dcache.demand_hits 23 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78073 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78096 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78117 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78137 # Number of cache demand accesses system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 18 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78070 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78088 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 26 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78165 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78191 # Number of cache demand accesses system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 23 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 77974 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77997 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 31 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 77991 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78022 # Number of cache demand accesses system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l2_cntrl0.L2cache.demand_hits 1865 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 623660 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 625525 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 1849 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 624657 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 626506 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers00.percent_links_utilized 9.730987 -system.ruby.network.routers00.msg_count.Request_Control::1 78075 -system.ruby.network.routers00.msg_count.Response_Data::4 79609 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 237 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 185 -system.ruby.network.routers00.msg_count.Response_Control::4 87 -system.ruby.network.routers00.msg_count.Writeback_Data::4 84294 -system.ruby.network.routers00.msg_count.Broadcast_Control::1 625529 -system.ruby.network.routers00.msg_count.Persistent_Control::3 98738 -system.ruby.network.routers00.msg_bytes.Request_Control::1 624600 -system.ruby.network.routers00.msg_bytes.Response_Data::4 5731848 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 17064 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 13320 -system.ruby.network.routers00.msg_bytes.Response_Control::4 696 -system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6069168 -system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5004232 -system.ruby.network.routers00.msg_bytes.Persistent_Control::3 789904 -system.ruby.network.routers01.percent_links_utilized 9.789650 -system.ruby.network.routers01.msg_count.Request_Control::1 78759 -system.ruby.network.routers01.msg_count.Response_Data::4 80279 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 250 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 170 -system.ruby.network.routers01.msg_count.Response_Control::4 88 -system.ruby.network.routers01.msg_count.Writeback_Data::4 85066 -system.ruby.network.routers01.msg_count.Broadcast_Control::1 625528 -system.ruby.network.routers01.msg_count.Persistent_Control::3 98848 -system.ruby.network.routers01.msg_bytes.Request_Control::1 630072 -system.ruby.network.routers01.msg_bytes.Response_Data::4 5780088 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 18000 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 12240 -system.ruby.network.routers01.msg_bytes.Response_Control::4 704 -system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6124752 -system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5004224 -system.ruby.network.routers01.msg_bytes.Persistent_Control::3 790784 -system.ruby.network.routers02.percent_links_utilized 9.754677 -system.ruby.network.routers02.msg_count.Request_Control::1 78362 -system.ruby.network.routers02.msg_count.Response_Data::4 79837 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 249 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 172 -system.ruby.network.routers02.msg_count.Response_Control::4 97 -system.ruby.network.routers02.msg_count.Writeback_Data::4 84646 -system.ruby.network.routers02.msg_count.Broadcast_Control::1 625529 -system.ruby.network.routers02.msg_count.Persistent_Control::3 98784 -system.ruby.network.routers02.msg_bytes.Request_Control::1 626896 -system.ruby.network.routers02.msg_bytes.Response_Data::4 5748264 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 17928 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 12384 -system.ruby.network.routers02.msg_bytes.Response_Control::4 776 -system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6094512 -system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5004232 -system.ruby.network.routers02.msg_bytes.Persistent_Control::3 790272 -system.ruby.network.routers03.percent_links_utilized 9.724713 -system.ruby.network.routers03.msg_count.Request_Control::1 78022 -system.ruby.network.routers03.msg_count.Response_Data::4 79535 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 229 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 170 -system.ruby.network.routers03.msg_count.Response_Control::4 85 -system.ruby.network.routers03.msg_count.Writeback_Data::4 84220 -system.ruby.network.routers03.msg_count.Broadcast_Control::1 625530 -system.ruby.network.routers03.msg_count.Persistent_Control::3 98860 -system.ruby.network.routers03.msg_bytes.Request_Control::1 624176 -system.ruby.network.routers03.msg_bytes.Response_Data::4 5726520 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 16488 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 12240 -system.ruby.network.routers03.msg_bytes.Response_Control::4 680 -system.ruby.network.routers03.msg_bytes.Writeback_Data::4 6063840 -system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5004240 -system.ruby.network.routers03.msg_bytes.Persistent_Control::3 790880 -system.ruby.network.routers04.percent_links_utilized 9.738865 -system.ruby.network.routers04.msg_count.Request_Control::1 78196 -system.ruby.network.routers04.msg_count.Response_Data::4 79670 -system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 267 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 159 +system.ruby.network.routers00.percent_links_utilized 9.725168 +system.ruby.network.routers00.msg_count.Request_Control::1 78497 +system.ruby.network.routers00.msg_count.Response_Data::4 79591 +system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 246 +system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 169 +system.ruby.network.routers00.msg_count.Response_Control::4 82 +system.ruby.network.routers00.msg_count.Writeback_Data::4 83784 +system.ruby.network.routers00.msg_count.Broadcast_Control::1 626506 +system.ruby.network.routers00.msg_count.Persistent_Control::3 85284 +system.ruby.network.routers00.msg_bytes.Request_Control::1 627976 +system.ruby.network.routers00.msg_bytes.Response_Data::4 5730552 +system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 17712 +system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 12168 +system.ruby.network.routers00.msg_bytes.Response_Control::4 656 +system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6032448 +system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5012048 +system.ruby.network.routers00.msg_bytes.Persistent_Control::3 682272 +system.ruby.network.routers01.percent_links_utilized 9.743292 +system.ruby.network.routers01.msg_count.Request_Control::1 78630 +system.ruby.network.routers01.msg_count.Response_Data::4 79741 +system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 243 +system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 183 +system.ruby.network.routers01.msg_count.Response_Control::4 89 +system.ruby.network.routers01.msg_count.Writeback_Data::4 84044 +system.ruby.network.routers01.msg_count.Broadcast_Control::1 626506 +system.ruby.network.routers01.msg_count.Persistent_Control::3 85575 +system.ruby.network.routers01.msg_bytes.Request_Control::1 629040 +system.ruby.network.routers01.msg_bytes.Response_Data::4 5741352 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 17496 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 13176 +system.ruby.network.routers01.msg_bytes.Response_Control::4 712 +system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6051168 +system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5012048 +system.ruby.network.routers01.msg_bytes.Persistent_Control::3 684600 +system.ruby.network.routers02.percent_links_utilized 9.698052 +system.ruby.network.routers02.msg_count.Request_Control::1 78235 +system.ruby.network.routers02.msg_count.Response_Data::4 79292 +system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 212 +system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 153 +system.ruby.network.routers02.msg_count.Response_Control::4 90 +system.ruby.network.routers02.msg_count.Writeback_Data::4 83460 +system.ruby.network.routers02.msg_count.Broadcast_Control::1 626506 +system.ruby.network.routers02.msg_count.Persistent_Control::3 85281 +system.ruby.network.routers02.msg_bytes.Request_Control::1 625880 +system.ruby.network.routers02.msg_bytes.Response_Data::4 5709024 +system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 15264 +system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 11016 +system.ruby.network.routers02.msg_bytes.Response_Control::4 720 +system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6009120 +system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5012048 +system.ruby.network.routers02.msg_bytes.Persistent_Control::3 682248 +system.ruby.network.routers03.percent_links_utilized 9.723184 +system.ruby.network.routers03.msg_count.Request_Control::1 78633 +system.ruby.network.routers03.msg_count.Response_Data::4 79727 +system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 236 +system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 157 +system.ruby.network.routers03.msg_count.Response_Control::4 80 +system.ruby.network.routers03.msg_count.Writeback_Data::4 83634 +system.ruby.network.routers03.msg_count.Broadcast_Control::1 626506 +system.ruby.network.routers03.msg_count.Persistent_Control::3 85013 +system.ruby.network.routers03.msg_bytes.Request_Control::1 629064 +system.ruby.network.routers03.msg_bytes.Response_Data::4 5740344 +system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 16992 +system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 11304 +system.ruby.network.routers03.msg_bytes.Response_Control::4 640 +system.ruby.network.routers03.msg_bytes.Writeback_Data::4 6021648 +system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5012048 +system.ruby.network.routers03.msg_bytes.Persistent_Control::3 680104 +system.ruby.network.routers04.percent_links_utilized 9.701672 +system.ruby.network.routers04.msg_count.Request_Control::1 78239 +system.ruby.network.routers04.msg_count.Response_Data::4 79311 +system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 248 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 172 system.ruby.network.routers04.msg_count.Response_Control::4 83 -system.ruby.network.routers04.msg_count.Writeback_Data::4 84421 -system.ruby.network.routers04.msg_count.Broadcast_Control::1 625529 -system.ruby.network.routers04.msg_count.Persistent_Control::3 98740 -system.ruby.network.routers04.msg_bytes.Request_Control::1 625568 -system.ruby.network.routers04.msg_bytes.Response_Data::4 5736240 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 19224 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 11448 +system.ruby.network.routers04.msg_count.Writeback_Data::4 83490 +system.ruby.network.routers04.msg_count.Broadcast_Control::1 626506 +system.ruby.network.routers04.msg_count.Persistent_Control::3 85191 +system.ruby.network.routers04.msg_bytes.Request_Control::1 625912 +system.ruby.network.routers04.msg_bytes.Response_Data::4 5710392 +system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 17856 +system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 12384 system.ruby.network.routers04.msg_bytes.Response_Control::4 664 -system.ruby.network.routers04.msg_bytes.Writeback_Data::4 6078312 -system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5004232 -system.ruby.network.routers04.msg_bytes.Persistent_Control::3 789920 -system.ruby.network.routers05.percent_links_utilized 9.728150 -system.ruby.network.routers05.msg_count.Request_Control::1 78072 -system.ruby.network.routers05.msg_count.Response_Data::4 79633 +system.ruby.network.routers04.msg_bytes.Writeback_Data::4 6011280 +system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5012048 +system.ruby.network.routers04.msg_bytes.Persistent_Control::3 681528 +system.ruby.network.routers05.percent_links_utilized 9.689342 +system.ruby.network.routers05.msg_count.Request_Control::1 78117 +system.ruby.network.routers05.msg_count.Response_Data::4 79097 system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 245 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 155 -system.ruby.network.routers05.msg_count.Response_Control::4 96 -system.ruby.network.routers05.msg_count.Writeback_Data::4 84222 -system.ruby.network.routers05.msg_count.Broadcast_Control::1 625529 -system.ruby.network.routers05.msg_count.Persistent_Control::3 98698 -system.ruby.network.routers05.msg_bytes.Request_Control::1 624576 -system.ruby.network.routers05.msg_bytes.Response_Data::4 5733576 +system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 174 +system.ruby.network.routers05.msg_count.Response_Control::4 89 +system.ruby.network.routers05.msg_count.Writeback_Data::4 83390 +system.ruby.network.routers05.msg_count.Broadcast_Control::1 626506 +system.ruby.network.routers05.msg_count.Persistent_Control::3 85271 +system.ruby.network.routers05.msg_bytes.Request_Control::1 624936 +system.ruby.network.routers05.msg_bytes.Response_Data::4 5694984 system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 17640 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 11160 -system.ruby.network.routers05.msg_bytes.Response_Control::4 768 -system.ruby.network.routers05.msg_bytes.Writeback_Data::4 6063984 -system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5004232 -system.ruby.network.routers05.msg_bytes.Persistent_Control::3 789584 -system.ruby.network.routers06.percent_links_utilized 9.728291 -system.ruby.network.routers06.msg_count.Request_Control::1 78070 -system.ruby.network.routers06.msg_count.Response_Data::4 79475 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 256 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 173 -system.ruby.network.routers06.msg_count.Response_Control::4 79 -system.ruby.network.routers06.msg_count.Writeback_Data::4 84364 -system.ruby.network.routers06.msg_count.Writeback_Control::4 2 -system.ruby.network.routers06.msg_count.Broadcast_Control::1 625529 -system.ruby.network.routers06.msg_count.Persistent_Control::3 98630 -system.ruby.network.routers06.msg_bytes.Request_Control::1 624560 -system.ruby.network.routers06.msg_bytes.Response_Data::4 5722200 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 18432 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 12456 -system.ruby.network.routers06.msg_bytes.Response_Control::4 632 -system.ruby.network.routers06.msg_bytes.Writeback_Data::4 6074208 -system.ruby.network.routers06.msg_bytes.Writeback_Control::4 16 -system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5004232 -system.ruby.network.routers06.msg_bytes.Persistent_Control::3 789040 -system.ruby.network.routers07.percent_links_utilized 9.723996 -system.ruby.network.routers07.msg_count.Request_Control::1 77974 -system.ruby.network.routers07.msg_count.Response_Data::4 79528 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 227 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 168 -system.ruby.network.routers07.msg_count.Response_Control::4 93 -system.ruby.network.routers07.msg_count.Writeback_Data::4 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-system.ruby.network.routers08.msg_count.Request_Control::2 623660 -system.ruby.network.routers08.msg_count.Response_Data::4 8086 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1868 -system.ruby.network.routers08.msg_count.Response_Control::4 685 -system.ruby.network.routers08.msg_count.Writeback_Data::4 860995 -system.ruby.network.routers08.msg_count.Writeback_Control::4 379214 -system.ruby.network.routers08.msg_count.Persistent_Control::3 87802 -system.ruby.network.routers08.msg_bytes.Request_Control::1 5004200 -system.ruby.network.routers08.msg_bytes.Request_Control::2 4989280 -system.ruby.network.routers08.msg_bytes.Response_Data::4 582192 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 134496 -system.ruby.network.routers08.msg_bytes.Response_Control::4 5480 -system.ruby.network.routers08.msg_bytes.Writeback_Data::4 61991640 -system.ruby.network.routers08.msg_bytes.Writeback_Control::4 3033712 -system.ruby.network.routers08.msg_bytes.Persistent_Control::3 702416 -system.ruby.network.routers09.percent_links_utilized 37.857719 -system.ruby.network.routers09.msg_count.Request_Control::2 623660 -system.ruby.network.routers09.msg_count.Response_Data::4 628501 -system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 92 -system.ruby.network.routers09.msg_count.Response_Control::4 5 -system.ruby.network.routers09.msg_count.Writeback_Data::4 236381 -system.ruby.network.routers09.msg_count.Writeback_Control::4 379217 -system.ruby.network.routers09.msg_count.Persistent_Control::3 87802 -system.ruby.network.routers09.msg_bytes.Request_Control::2 4989280 -system.ruby.network.routers09.msg_bytes.Response_Data::4 45252072 -system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 6624 -system.ruby.network.routers09.msg_bytes.Response_Control::4 40 -system.ruby.network.routers09.msg_bytes.Writeback_Data::4 17019432 -system.ruby.network.routers09.msg_bytes.Writeback_Control::4 3033736 -system.ruby.network.routers09.msg_bytes.Persistent_Control::3 702416 -system.ruby.network.routers10.percent_links_utilized 17.516576 -system.ruby.network.routers10.msg_count.Request_Control::1 625525 -system.ruby.network.routers10.msg_count.Request_Control::2 623660 -system.ruby.network.routers10.msg_count.Response_Data::4 637077 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1960 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 676 -system.ruby.network.routers10.msg_count.Response_Control::4 699 -system.ruby.network.routers10.msg_count.Writeback_Data::4 886410 -system.ruby.network.routers10.msg_count.Writeback_Control::4 379217 -system.ruby.network.routers10.msg_count.Broadcast_Control::1 4378710 -system.ruby.network.routers10.msg_count.Persistent_Control::3 790218 -system.ruby.network.routers10.msg_bytes.Request_Control::1 5004200 -system.ruby.network.routers10.msg_bytes.Request_Control::2 4989280 -system.ruby.network.routers10.msg_bytes.Response_Data::4 45869544 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 141120 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 48672 -system.ruby.network.routers10.msg_bytes.Response_Control::4 5592 -system.ruby.network.routers10.msg_bytes.Writeback_Data::4 63821520 -system.ruby.network.routers10.msg_bytes.Writeback_Control::4 3033736 -system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35029680 -system.ruby.network.routers10.msg_bytes.Persistent_Control::3 6321744 -system.ruby.network.msg_count.Request_Control 3747560 -system.ruby.network.msg_count.Response_Data 1911230 -system.ruby.network.msg_count.ResponseL2hit_Data 5880 -system.ruby.network.msg_count.ResponseLocal_Data 2028 -system.ruby.network.msg_count.Response_Control 2097 -system.ruby.network.msg_count.Writeback_Data 2659229 -system.ruby.network.msg_count.Writeback_Control 1137652 -system.ruby.network.msg_count.Broadcast_Control 9382942 -system.ruby.network.msg_count.Persistent_Control 1756040 -system.ruby.network.msg_byte.Request_Control 29980480 -system.ruby.network.msg_byte.Response_Data 137608560 -system.ruby.network.msg_byte.ResponseL2hit_Data 423360 -system.ruby.network.msg_byte.ResponseLocal_Data 146016 -system.ruby.network.msg_byte.Response_Control 16776 -system.ruby.network.msg_byte.Writeback_Data 191464488 -system.ruby.network.msg_byte.Writeback_Control 9101216 -system.ruby.network.msg_byte.Broadcast_Control 75063536 -system.ruby.network.msg_byte.Persistent_Control 14048320 -system.ruby.network.routers00.throttle0.link_utilization 11.725534 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 78644 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 224 -system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4 91 -system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4 3177 -system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1 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12240 +system.ruby.network.routers06.msg_bytes.Response_Control::4 760 +system.ruby.network.routers06.msg_bytes.Writeback_Data::4 5994864 +system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5012056 +system.ruby.network.routers06.msg_bytes.Persistent_Control::3 681208 +system.ruby.network.routers07.percent_links_utilized 9.674577 +system.ruby.network.routers07.msg_count.Request_Control::1 77991 +system.ruby.network.routers07.msg_count.Response_Data::4 78988 +system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 249 +system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 164 +system.ruby.network.routers07.msg_count.Response_Control::4 70 +system.ruby.network.routers07.msg_count.Writeback_Data::4 83160 +system.ruby.network.routers07.msg_count.Broadcast_Control::1 626506 +system.ruby.network.routers07.msg_count.Persistent_Control::3 85083 +system.ruby.network.routers07.msg_bytes.Request_Control::1 623928 +system.ruby.network.routers07.msg_bytes.Response_Data::4 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+system.ruby.network.msg_byte.Writeback_Control 9191400 +system.ruby.network.msg_byte.Broadcast_Control 75180728 +system.ruby.network.msg_byte.Persistent_Control 12121760 +system.ruby.network.routers00.throttle0.link_utilization 11.686424 +system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 78837 +system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 233 +system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4 89 +system.ruby.network.routers00.throttle0.msg_count.Response_Control::4 3 +system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4 2708 +system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1 548009 +system.ruby.network.routers00.throttle0.msg_count.Persistent_Control::3 75761 +system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::4 5676264 +system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::4 16776 +system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::4 6408 +system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::4 24 +system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Data::4 194976 +system.ruby.network.routers00.throttle0.msg_bytes.Broadcast_Control::1 4384072 +system.ruby.network.routers00.throttle0.msg_bytes.Persistent_Control::3 606088 +system.ruby.network.routers00.throttle1.link_utilization 7.763913 +system.ruby.network.routers00.throttle1.msg_count.Request_Control::1 78497 +system.ruby.network.routers00.throttle1.msg_count.Response_Data::4 754 system.ruby.network.routers00.throttle1.msg_count.ResponseL2hit_Data::4 13 -system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::4 94 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::4 87 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::4 81117 -system.ruby.network.routers00.throttle1.msg_count.Broadcast_Control::1 78075 -system.ruby.network.routers00.throttle1.msg_count.Persistent_Control::3 10936 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-system.ruby.network.routers09.throttle0.msg_count.Writeback_Control::4 379215 -system.ruby.network.routers09.throttle0.msg_count.Persistent_Control::3 87802 -system.ruby.network.routers09.throttle0.msg_bytes.Request_Control::2 4989280 -system.ruby.network.routers09.throttle0.msg_bytes.Response_Data::4 516384 -system.ruby.network.routers09.throttle0.msg_bytes.ResponseL2hit_Data::4 6624 -system.ruby.network.routers09.throttle0.msg_bytes.Response_Control::4 24 -system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Data::4 16998336 -system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Control::4 3033720 -system.ruby.network.routers09.throttle0.msg_bytes.Persistent_Control::3 702416 -system.ruby.network.routers09.throttle1.link_utilization 47.726894 -system.ruby.network.routers09.throttle1.msg_count.Response_Data::4 621329 +system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Data::4 199512 +system.ruby.network.routers01.throttle0.msg_bytes.Broadcast_Control::1 4383008 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-system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 3213 -system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 547168 -system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 76820 -system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5680800 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 16776 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 5688 -system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 231336 -system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4377344 -system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 614560 -system.ruby.network.routers10.throttle3.link_utilization 11.624929 -system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 78592 -system.ruby.network.routers10.throttle3.msg_count.ResponseL2hit_Data::4 220 -system.ruby.network.routers10.throttle3.msg_count.ResponseLocal_Data::4 82 -system.ruby.network.routers10.throttle3.msg_count.Response_Control::4 3 -system.ruby.network.routers10.throttle3.msg_count.Writeback_Data::4 3154 -system.ruby.network.routers10.throttle3.msg_count.Broadcast_Control::1 547508 -system.ruby.network.routers10.throttle3.msg_count.Persistent_Control::3 76744 -system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::4 5658624 -system.ruby.network.routers10.throttle3.msg_bytes.ResponseL2hit_Data::4 15840 -system.ruby.network.routers10.throttle3.msg_bytes.ResponseLocal_Data::4 5904 -system.ruby.network.routers10.throttle3.msg_bytes.Response_Control::4 24 -system.ruby.network.routers10.throttle3.msg_bytes.Writeback_Data::4 227088 -system.ruby.network.routers10.throttle3.msg_bytes.Broadcast_Control::1 4380064 -system.ruby.network.routers10.throttle3.msg_bytes.Persistent_Control::3 613952 -system.ruby.network.routers10.throttle4.link_utilization 11.638280 -system.ruby.network.routers10.throttle4.msg_count.Response_Data::4 78703 -system.ruby.network.routers10.throttle4.msg_count.ResponseL2hit_Data::4 258 -system.ruby.network.routers10.throttle4.msg_count.ResponseLocal_Data::4 84 -system.ruby.network.routers10.throttle4.msg_count.Response_Control::4 2 -system.ruby.network.routers10.throttle4.msg_count.Writeback_Data::4 3183 -system.ruby.network.routers10.throttle4.msg_count.Broadcast_Control::1 547334 -system.ruby.network.routers10.throttle4.msg_count.Persistent_Control::3 76864 -system.ruby.network.routers10.throttle4.msg_bytes.Response_Data::4 5666616 -system.ruby.network.routers10.throttle4.msg_bytes.ResponseL2hit_Data::4 18576 -system.ruby.network.routers10.throttle4.msg_bytes.ResponseLocal_Data::4 6048 -system.ruby.network.routers10.throttle4.msg_bytes.Response_Control::4 16 -system.ruby.network.routers10.throttle4.msg_bytes.Writeback_Data::4 229176 -system.ruby.network.routers10.throttle4.msg_bytes.Broadcast_Control::1 4378672 -system.ruby.network.routers10.throttle4.msg_bytes.Persistent_Control::3 614912 -system.ruby.network.routers10.throttle5.link_utilization 11.630082 -system.ruby.network.routers10.throttle5.msg_count.Response_Data::4 78646 -system.ruby.network.routers10.throttle5.msg_count.ResponseL2hit_Data::4 235 -system.ruby.network.routers10.throttle5.msg_count.ResponseLocal_Data::4 74 -system.ruby.network.routers10.throttle5.msg_count.Writeback_Data::4 3148 -system.ruby.network.routers10.throttle5.msg_count.Broadcast_Control::1 547458 -system.ruby.network.routers10.throttle5.msg_count.Persistent_Control::3 76906 -system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::4 5662512 -system.ruby.network.routers10.throttle5.msg_bytes.ResponseL2hit_Data::4 16920 -system.ruby.network.routers10.throttle5.msg_bytes.ResponseLocal_Data::4 5328 -system.ruby.network.routers10.throttle5.msg_bytes.Writeback_Data::4 226656 -system.ruby.network.routers10.throttle5.msg_bytes.Broadcast_Control::1 4379664 -system.ruby.network.routers10.throttle5.msg_bytes.Persistent_Control::3 615248 -system.ruby.network.routers10.throttle6.link_utilization 11.631404 -system.ruby.network.routers10.throttle6.msg_count.Response_Data::4 78558 -system.ruby.network.routers10.throttle6.msg_count.ResponseL2hit_Data::4 241 -system.ruby.network.routers10.throttle6.msg_count.ResponseLocal_Data::4 99 -system.ruby.network.routers10.throttle6.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle6.msg_count.Writeback_Data::4 3215 -system.ruby.network.routers10.throttle6.msg_count.Writeback_Control::4 1 -system.ruby.network.routers10.throttle6.msg_count.Broadcast_Control::1 547460 -system.ruby.network.routers10.throttle6.msg_count.Persistent_Control::3 76974 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::4 5656176 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseL2hit_Data::4 17352 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseLocal_Data::4 7128 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle6.msg_bytes.Writeback_Data::4 231480 -system.ruby.network.routers10.throttle6.msg_bytes.Writeback_Control::4 8 -system.ruby.network.routers10.throttle6.msg_bytes.Broadcast_Control::1 4379680 -system.ruby.network.routers10.throttle6.msg_bytes.Persistent_Control::3 615792 -system.ruby.network.routers10.throttle7.link_utilization 11.624230 -system.ruby.network.routers10.throttle7.msg_count.Response_Data::4 78541 -system.ruby.network.routers10.throttle7.msg_count.ResponseL2hit_Data::4 218 -system.ruby.network.routers10.throttle7.msg_count.ResponseLocal_Data::4 84 -system.ruby.network.routers10.throttle7.msg_count.Response_Control::4 4 -system.ruby.network.routers10.throttle7.msg_count.Writeback_Data::4 3197 -system.ruby.network.routers10.throttle7.msg_count.Writeback_Control::4 1 -system.ruby.network.routers10.throttle7.msg_count.Broadcast_Control::1 547556 -system.ruby.network.routers10.throttle7.msg_count.Persistent_Control::3 76684 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::4 5654952 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseL2hit_Data::4 15696 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseLocal_Data::4 6048 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::4 32 -system.ruby.network.routers10.throttle7.msg_bytes.Writeback_Data::4 230184 -system.ruby.network.routers10.throttle7.msg_bytes.Writeback_Control::4 8 -system.ruby.network.routers10.throttle7.msg_bytes.Broadcast_Control::1 4380448 -system.ruby.network.routers10.throttle7.msg_bytes.Persistent_Control::3 613472 -system.ruby.network.routers10.throttle8.link_utilization 54.063432 -system.ruby.network.routers10.throttle8.msg_count.Request_Control::1 625525 -system.ruby.network.routers10.throttle8.msg_count.Response_Control::4 683 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::4 624819 -system.ruby.network.routers10.throttle8.msg_count.Persistent_Control::3 87802 -system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::1 5004200 -system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::4 5464 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::4 44986968 -system.ruby.network.routers10.throttle8.msg_bytes.Persistent_Control::3 702416 -system.ruby.network.routers10.throttle9.link_utilization 27.988545 -system.ruby.network.routers10.throttle9.msg_count.Request_Control::2 623660 -system.ruby.network.routers10.throttle9.msg_count.Response_Data::4 7172 -system.ruby.network.routers10.throttle9.msg_count.ResponseL2hit_Data::4 92 -system.ruby.network.routers10.throttle9.msg_count.Response_Control::4 3 -system.ruby.network.routers10.throttle9.msg_count.Writeback_Data::4 236088 -system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::4 379215 -system.ruby.network.routers10.throttle9.msg_count.Persistent_Control::3 87802 -system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::2 4989280 -system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::4 516384 -system.ruby.network.routers10.throttle9.msg_bytes.ResponseL2hit_Data::4 6624 -system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::4 24 -system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::4 16998336 -system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::4 3033720 -system.ruby.network.routers10.throttle9.msg_bytes.Persistent_Control::3 702416 +system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Data::4 199512 +system.ruby.network.routers10.throttle1.msg_bytes.Broadcast_Control::1 4383008 +system.ruby.network.routers10.throttle1.msg_bytes.Persistent_Control::3 527576 +system.ruby.network.routers10.throttle2.link_utilization 11.581316 +system.ruby.network.routers10.throttle2.msg_count.Response_Data::4 78577 +system.ruby.network.routers10.throttle2.msg_count.ResponseL2hit_Data::4 204 +system.ruby.network.routers10.throttle2.msg_count.ResponseLocal_Data::4 80 +system.ruby.network.routers10.throttle2.msg_count.Response_Control::4 3 +system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 2675 +system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 548271 +system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 66241 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5657544 +system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 14688 +system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 5760 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Control::4 24 +system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 192600 +system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4386168 +system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 529928 +system.ruby.network.routers10.throttle3.link_utilization 11.604061 +system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 78977 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+system.ruby.network.routers10.throttle9.link_utilization 27.908945 +system.ruby.network.routers10.throttle9.msg_count.Request_Control::2 624656 +system.ruby.network.routers10.throttle9.msg_count.Response_Data::4 5419 +system.ruby.network.routers10.throttle9.msg_count.ResponseL2hit_Data::4 72 +system.ruby.network.routers10.throttle9.msg_count.Response_Control::4 4 +system.ruby.network.routers10.throttle9.msg_count.Writeback_Data::4 235161 +system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::4 382975 +system.ruby.network.routers10.throttle9.msg_count.Persistent_Control::3 75761 +system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::2 4997248 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::4 390168 +system.ruby.network.routers10.throttle9.msg_bytes.ResponseL2hit_Data::4 5184 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::4 32 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::4 16931592 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::4 3063800 +system.ruby.network.routers10.throttle9.msg_bytes.Persistent_Control::3 606088 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 402553 -system.ruby.LD.latency_hist::mean 1197.730421 -system.ruby.LD.latency_hist::gmean 898.603771 -system.ruby.LD.latency_hist::stdev 763.969042 -system.ruby.LD.latency_hist | 108616 26.98% 26.98% | 76986 19.12% 46.11% | 71722 17.82% 63.92% | 76938 19.11% 83.04% | 54198 13.46% 96.50% | 13154 3.27% 99.77% | 917 0.23% 99.99% | 22 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 402553 +system.ruby.LD.latency_hist::samples 402549 +system.ruby.LD.latency_hist::mean 1187.783604 +system.ruby.LD.latency_hist::gmean 893.795136 +system.ruby.LD.latency_hist::stdev 754.111329 +system.ruby.LD.latency_hist | 108868 27.04% 27.04% | 77028 19.14% 46.18% | 74115 18.41% 64.59% | 77143 19.16% 83.75% | 52941 13.15% 96.91% | 11655 2.90% 99.80% | 788 0.20% 100.00% | 11 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 402549 system.ruby.LD.hit_latency_hist::bucket_size 512 system.ruby.LD.hit_latency_hist::max_bucket 5119 -system.ruby.LD.hit_latency_hist::samples 1907 -system.ruby.LD.hit_latency_hist::mean 1060.063975 -system.ruby.LD.hit_latency_hist::gmean 515.481436 -system.ruby.LD.hit_latency_hist::stdev 783.939123 -system.ruby.LD.hit_latency_hist | 650 34.08% 34.08% | 313 16.41% 50.50% | 343 17.99% 68.48% | 352 18.46% 86.94% | 203 10.64% 97.59% | 43 2.25% 99.84% | 3 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 1907 +system.ruby.LD.hit_latency_hist::samples 1873 +system.ruby.LD.hit_latency_hist::mean 1072.943940 +system.ruby.LD.hit_latency_hist::gmean 523.579188 +system.ruby.LD.hit_latency_hist::stdev 799.898512 +system.ruby.LD.hit_latency_hist | 635 33.90% 33.90% | 314 16.76% 50.67% | 306 16.34% 67.00% | 351 18.74% 85.74% | 219 11.69% 97.44% | 44 2.35% 99.79% | 4 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 1873 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 400646 -system.ruby.LD.miss_latency_hist::mean 1198.385687 -system.ruby.LD.miss_latency_hist::gmean 900.983925 -system.ruby.LD.miss_latency_hist::stdev 763.814413 -system.ruby.LD.miss_latency_hist | 107966 26.95% 26.95% | 76673 19.14% 46.09% | 71379 17.82% 63.90% | 76586 19.12% 83.02% | 53995 13.48% 96.49% | 13111 3.27% 99.77% | 914 0.23% 99.99% | 22 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 400646 +system.ruby.LD.miss_latency_hist::samples 400676 +system.ruby.LD.miss_latency_hist::mean 1188.320433 +system.ruby.LD.miss_latency_hist::gmean 896.032349 +system.ruby.LD.miss_latency_hist::stdev 753.850741 +system.ruby.LD.miss_latency_hist | 108233 27.01% 27.01% | 76714 19.15% 46.16% | 73809 18.42% 64.58% | 76792 19.17% 83.75% | 52722 13.16% 96.90% | 11611 2.90% 99.80% | 784 0.20% 100.00% | 11 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 400676 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223147 -system.ruby.ST.latency_hist::mean 1200.820284 -system.ruby.ST.latency_hist::gmean 902.064826 -system.ruby.ST.latency_hist::stdev 764.058400 -system.ruby.ST.latency_hist | 59898 26.84% 26.84% | 42460 19.03% 45.87% | 39907 17.88% 63.75% | 42757 19.16% 82.91% | 30297 13.58% 96.49% | 7307 3.27% 99.77% | 508 0.23% 99.99% | 12 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223147 +system.ruby.ST.latency_hist::samples 224121 +system.ruby.ST.latency_hist::mean 1190.810406 +system.ruby.ST.latency_hist::gmean 897.650544 +system.ruby.ST.latency_hist::stdev 753.288515 +system.ruby.ST.latency_hist | 60107 26.82% 26.82% | 43024 19.20% 46.02% | 41269 18.41% 64.43% | 43256 19.30% 83.73% | 29493 13.16% 96.89% | 6558 2.93% 99.82% | 410 0.18% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 224121 system.ruby.ST.hit_latency_hist::bucket_size 512 system.ruby.ST.hit_latency_hist::max_bucket 5119 -system.ruby.ST.hit_latency_hist::samples 1034 -system.ruby.ST.hit_latency_hist::mean 1095.824952 -system.ruby.ST.hit_latency_hist::gmean 593.169094 -system.ruby.ST.hit_latency_hist::stdev 799.304714 -system.ruby.ST.hit_latency_hist | 346 33.46% 33.46% | 167 16.15% 49.61% | 179 17.31% 66.92% | 179 17.31% 84.24% | 135 13.06% 97.29% | 25 2.42% 99.71% | 3 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 1034 +system.ruby.ST.hit_latency_hist::samples 1048 +system.ruby.ST.hit_latency_hist::mean 1114.259542 +system.ruby.ST.hit_latency_hist::gmean 582.696896 +system.ruby.ST.hit_latency_hist::stdev 809.474121 +system.ruby.ST.hit_latency_hist | 330 31.49% 31.49% | 184 17.56% 49.05% | 189 18.03% 67.08% | 172 16.41% 83.49% | 131 12.50% 95.99% | 40 3.82% 99.81% | 2 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 1048 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 222113 -system.ruby.ST.miss_latency_hist::mean 1201.309068 -system.ruby.ST.miss_latency_hist::gmean 903.826951 -system.ruby.ST.miss_latency_hist::stdev 763.858649 -system.ruby.ST.miss_latency_hist | 59552 26.81% 26.81% | 42293 19.04% 45.85% | 39728 17.89% 63.74% | 42578 19.17% 82.91% | 30162 13.58% 96.49% | 7282 3.28% 99.77% | 505 0.23% 99.99% | 12 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 222113 +system.ruby.ST.miss_latency_hist::samples 223073 +system.ruby.ST.miss_latency_hist::mean 1191.170043 +system.ruby.ST.miss_latency_hist::gmean 899.474694 +system.ruby.ST.miss_latency_hist::stdev 752.998243 +system.ruby.ST.miss_latency_hist | 59777 26.80% 26.80% | 42840 19.20% 46.00% | 41080 18.42% 64.42% | 43084 19.31% 83.73% | 29362 13.16% 96.89% | 6518 2.92% 99.82% | 408 0.18% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 223073 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 187 +system.ruby.L1Cache.hit_mach_latency_hist::samples 181 system.ruby.L1Cache.hit_mach_latency_hist::mean 2 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 2 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 187 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 187 +system.ruby.L1Cache.hit_mach_latency_hist::gmean 2.000000 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 181 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 181 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 1274 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1137.938776 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 742.704975 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 774.705868 -system.ruby.L1Cache.miss_mach_latency_hist | 360 28.26% 28.26% | 260 20.41% 48.67% | 251 19.70% 68.37% | 206 16.17% 84.54% | 148 11.62% 96.15% | 45 3.53% 99.69% | 4 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 1274 +system.ruby.L1Cache.miss_mach_latency_hist::samples 1208 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1138.897351 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 755.701841 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 765.191756 +system.ruby.L1Cache.miss_mach_latency_hist | 353 29.22% 29.22% | 218 18.05% 47.27% | 246 20.36% 67.63% | 213 17.63% 85.26% | 142 11.75% 97.02% | 32 2.65% 99.67% | 4 0.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 1208 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 512 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L2Cache.hit_mach_latency_hist::samples 2754 -system.ruby.L2Cache.hit_mach_latency_hist::mean 1145.334423 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 792.182169 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 763.134229 -system.ruby.L2Cache.hit_mach_latency_hist | 809 29.38% 29.38% | 480 17.43% 46.80% | 522 18.95% 65.76% | 531 19.28% 85.04% | 338 12.27% 97.31% | 68 2.47% 99.78% | 6 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 2754 +system.ruby.L2Cache.hit_mach_latency_hist::samples 2740 +system.ruby.L2Cache.hit_mach_latency_hist::mean 1159.491241 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 787.913705 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 777.910979 +system.ruby.L2Cache.hit_mach_latency_hist | 784 28.61% 28.61% | 498 18.18% 46.79% | 495 18.07% 64.85% | 523 19.09% 83.94% | 350 12.77% 96.72% | 84 3.07% 99.78% | 6 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 2740 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 621485 -system.ruby.Directory.miss_mach_latency_hist::mean 1199.554388 -system.ruby.Directory.miss_mach_latency_hist::gmean 902.356250 -system.ruby.Directory.miss_mach_latency_hist::stdev 763.803957 -system.ruby.Directory.miss_mach_latency_hist | 167158 26.90% 26.90% | 118706 19.10% 46.00% | 110856 17.84% 63.83% | 118958 19.14% 82.98% | 84009 13.52% 96.49% | 20348 3.27% 99.77% | 1415 0.23% 99.99% | 34 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 621485 +system.ruby.Directory.miss_mach_latency_hist::samples 622541 +system.ruby.Directory.miss_mach_latency_hist::mean 1189.437427 +system.ruby.Directory.miss_mach_latency_hist::gmean 897.560922 +system.ruby.Directory.miss_mach_latency_hist::stdev 753.521175 +system.ruby.Directory.miss_mach_latency_hist | 167657 26.93% 26.93% | 119336 19.17% 46.10% | 114643 18.42% 64.52% | 119663 19.22% 83.74% | 81942 13.16% 96.90% | 18097 2.91% 99.81% | 1188 0.19% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 622541 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 3 @@ -1154,451 +1141,447 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion | system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 3 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 141 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 123 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 141 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 141 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2.000000 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 123 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 123 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 810 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1148.616049 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 750.657657 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 779.125924 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 224 27.65% 27.65% | 172 21.23% 48.89% | 153 18.89% 67.78% | 128 15.80% 83.58% | 106 13.09% 96.67% | 24 2.96% 99.63% | 3 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 810 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 763 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1134.049803 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 747.970071 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 769.263081 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 224 29.36% 29.36% | 143 18.74% 48.10% | 151 19.79% 67.89% | 131 17.17% 85.06% | 89 11.66% 96.72% | 23 3.01% 99.74% | 2 0.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 763 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1766 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1144.541336 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 803.018182 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 753.048599 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 509 28.82% 28.82% | 313 17.72% 46.55% | 343 19.42% 65.97% | 352 19.93% 85.90% | 203 11.49% 97.40% | 43 2.43% 99.83% | 3 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1766 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1750 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1148.216000 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 774.336775 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 773.632611 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 512 29.26% 29.26% | 314 17.94% 47.20% | 306 17.49% 64.69% | 351 20.06% 84.74% | 219 12.51% 97.26% | 44 2.51% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1750 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 399836 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1198.486512 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 901.317161 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 763.780785 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 107742 26.95% 26.95% | 76501 19.13% 46.08% | 71226 17.81% 63.89% | 76458 19.12% 83.02% | 53889 13.48% 96.49% | 13087 3.27% 99.77% | 911 0.23% 99.99% | 22 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 399836 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 399913 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1188.423977 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 896.341171 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 753.818281 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 108009 27.01% 27.01% | 76571 19.15% 46.16% | 73658 18.42% 64.57% | 76661 19.17% 83.74% | 52633 13.16% 96.90% | 11588 2.90% 99.80% | 782 0.20% 100.00% | 11 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 399913 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 46 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 58 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2.000000 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 46 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 58 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 58 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 464 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1119.299569 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 729.023445 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 767.409492 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 136 29.31% 29.31% | 88 18.97% 48.28% | 98 21.12% 69.40% | 78 16.81% 86.21% | 42 9.05% 95.26% | 21 4.53% 99.78% | 1 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 464 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 445 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1147.208989 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 769.145243 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 758.950513 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 129 28.99% 28.99% | 75 16.85% 45.84% | 95 21.35% 67.19% | 82 18.43% 85.62% | 53 11.91% 97.53% | 9 2.02% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 445 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 988 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1146.752024 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 773.176325 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 781.220856 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 300 30.36% 30.36% | 167 16.90% 47.27% | 179 18.12% 65.38% | 179 18.12% 83.50% | 135 13.66% 97.17% | 25 2.53% 99.70% | 3 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 988 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 990 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1179.422222 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 812.498260 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 785.413197 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 272 27.47% 27.47% | 184 18.59% 46.06% | 189 19.09% 65.15% | 172 17.37% 82.53% | 131 13.23% 95.76% | 40 4.04% 99.80% | 2 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 990 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221649 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1201.480747 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 904.233709 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 763.843702 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 59416 26.81% 26.81% | 42205 19.04% 45.85% | 39630 17.88% 63.73% | 42500 19.17% 82.90% | 30120 13.59% 96.49% | 7261 3.28% 99.77% | 504 0.23% 99.99% | 12 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221649 -system.ruby.Directory_Controller.GETX 237776 0.00% 0.00% -system.ruby.Directory_Controller.GETS 429309 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 44122 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 43680 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 324 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 243004 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 548 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 377814 0.00% 0.00% -system.ruby.Directory_Controller.Tokens 130 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 793 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 621328 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 242939 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 220131 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 396984 0.00% 0.00% -system.ruby.Directory_Controller.O.Lockdown 3690 0.00% 0.00% -system.ruby.Directory_Controller.O.Data_All_Tokens 60 0.00% 0.00% -system.ruby.Directory_Controller.O.Tokens 4 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 785 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 2197 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 3978 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 17299 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 324 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 242616 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 548 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 377404 0.00% 0.00% -system.ruby.Directory_Controller.NO.Tokens 123 0.00% 0.00% -system.ruby.Directory_Controller.L.GETX 123 0.00% 0.00% -system.ruby.Directory_Controller.L.GETS 247 0.00% 0.00% -system.ruby.Directory_Controller.L.Lockdown 395 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 43680 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_All_Tokens 294 0.00% 0.00% -system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 410 0.00% 0.00% -system.ruby.Directory_Controller.L.Tokens 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 70 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 121 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Lockdown 124 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Data_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Tokens 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Ack_All_Tokens 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 242815 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETX 34 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETS 64 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Lockdown 12 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Ack_All_Tokens 6 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Data 4224 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Ack 124 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETX 495 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETS 954 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Lockdown 35 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 22567 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETX 14726 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETS 26961 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 22567 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 594537 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50092 12.44% 12.44% | 50720 12.60% 25.04% | 50362 12.51% 37.55% | 50243 12.48% 50.03% | 50550 12.56% 62.59% | 50015 12.42% 75.01% | 50346 12.51% 87.52% | 50237 12.48% 100.00% -system.ruby.L1Cache_Controller.Load::total 402565 -system.ruby.L1Cache_Controller.Store | 28010 12.55% 12.55% | 28064 12.58% 25.13% | 28024 12.56% 37.69% | 27802 12.46% 50.14% | 27671 12.40% 62.54% | 28081 12.58% 75.13% | 27742 12.43% 87.56% | 27760 12.44% 100.00% -system.ruby.L1Cache_Controller.Store::total 223154 -system.ruby.L1Cache_Controller.L1_Replacement | 1468380 12.49% 12.49% | 1481332 12.60% 25.08% | 1472761 12.52% 37.61% | 1468524 12.49% 50.09% | 1470130 12.50% 62.59% | 1467500 12.48% 75.07% | 1468017 12.48% 87.55% | 1463638 12.45% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 11760282 -system.ruby.L1Cache_Controller.Data_Shared | 197 12.64% 12.64% | 195 12.52% 25.16% | 194 12.45% 37.61% | 178 11.42% 49.04% | 190 12.20% 61.23% | 196 12.58% 73.81% | 203 13.03% 86.84% | 205 13.16% 100.00% -system.ruby.L1Cache_Controller.Data_Shared::total 1558 -system.ruby.L1Cache_Controller.Data_Owner | 28 9.69% 9.69% | 43 14.88% 24.57% | 30 10.38% 34.95% | 39 13.49% 48.44% | 33 11.42% 59.86% | 38 13.15% 73.01% | 33 11.42% 84.43% | 45 15.57% 100.00% -system.ruby.L1Cache_Controller.Data_Owner::total 289 -system.ruby.L1Cache_Controller.Data_All_Tokens | 81911 12.48% 12.48% | 82621 12.59% 25.08% | 82201 12.53% 37.61% | 81831 12.47% 50.08% | 82005 12.50% 62.58% | 81869 12.48% 75.05% | 81876 12.48% 87.53% | 81790 12.47% 100.00% -system.ruby.L1Cache_Controller.Data_All_Tokens::total 656104 -system.ruby.L1Cache_Controller.Ack | 0 0.00% 0.00% | 2 16.67% 16.67% | 0 0.00% 16.67% | 3 25.00% 41.67% | 1 8.33% 50.00% | 0 0.00% 50.00% | 2 16.67% 66.67% | 4 33.33% 100.00% -system.ruby.L1Cache_Controller.Ack::total 12 -system.ruby.L1Cache_Controller.Ack_All_Tokens | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 222628 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1191.257915 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 899.756167 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 752.985446 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 59648 26.79% 26.79% | 42765 19.21% 46.00% | 40985 18.41% 64.41% | 43002 19.32% 83.73% | 29309 13.17% 96.89% | 6509 2.92% 99.82% | 406 0.18% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 222628 +system.ruby.Directory_Controller.GETX 239460 0.00% 0.00% +system.ruby.Directory_Controller.GETS 428967 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 38034 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 37727 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 321 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 240316 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 543 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 381575 0.00% 0.00% +system.ruby.Directory_Controller.Tokens 112 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 797 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 622354 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 240209 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 220941 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 397128 0.00% 0.00% +system.ruby.Directory_Controller.O.Lockdown 3790 0.00% 0.00% +system.ruby.Directory_Controller.O.Data_All_Tokens 54 0.00% 0.00% +system.ruby.Directory_Controller.O.Tokens 10 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 794 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 2346 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 3933 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 16200 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 320 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 239889 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 543 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 381172 0.00% 0.00% +system.ruby.Directory_Controller.NO.Tokens 100 0.00% 0.00% +system.ruby.Directory_Controller.L.GETX 121 0.00% 0.00% +system.ruby.Directory_Controller.L.GETS 186 0.00% 0.00% +system.ruby.Directory_Controller.L.Lockdown 271 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 37725 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_Owner 1 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_All_Tokens 344 0.00% 0.00% +system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 403 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 57 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 112 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Lockdown 106 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Data_All_Tokens 29 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Tokens 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Ack_All_Tokens 1 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Data 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 240103 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETX 159 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETS 140 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Lockdown 11 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Data 4297 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Ack 106 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETX 500 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETS 898 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Lockdown 24 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 17632 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETX 15336 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETS 26570 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 17632 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 600423 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50682 12.59% 12.59% | 50375 12.51% 25.10% | 50329 12.50% 37.61% | 50270 12.49% 50.09% | 50502 12.55% 62.64% | 50212 12.47% 75.11% | 50142 12.46% 87.57% | 50051 12.43% 100.00% +system.ruby.L1Cache_Controller.Load::total 402563 +system.ruby.L1Cache_Controller.Store | 27842 12.42% 12.42% | 28274 12.62% 25.04% | 27922 12.46% 37.50% | 28383 12.66% 50.16% | 27759 12.39% 62.55% | 27925 12.46% 75.01% | 28049 12.51% 87.52% | 27971 12.48% 100.00% +system.ruby.L1Cache_Controller.Store::total 224125 +system.ruby.L1Cache_Controller.L1_Replacement | 1479559 12.54% 12.54% | 1480747 12.55% 25.09% | 1474669 12.50% 37.59% | 1479770 12.54% 50.13% | 1471682 12.47% 62.61% | 1470820 12.47% 75.07% | 1470605 12.46% 87.54% | 1470089 12.46% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 11797941 +system.ruby.L1Cache_Controller.Data_Shared | 200 13.10% 13.10% | 183 11.98% 25.08% | 165 10.81% 35.89% | 194 12.70% 48.59% | 206 13.49% 62.08% | 197 12.90% 74.98% | 182 11.92% 86.90% | 200 13.10% 100.00% +system.ruby.L1Cache_Controller.Data_Shared::total 1527 +system.ruby.L1Cache_Controller.Data_Owner | 30 10.20% 10.20% | 29 9.86% 20.07% | 31 10.54% 30.61% | 36 12.24% 42.86% | 45 15.31% 58.16% | 39 13.27% 71.43% | 42 14.29% 85.71% | 42 14.29% 100.00% +system.ruby.L1Cache_Controller.Data_Owner::total 294 +system.ruby.L1Cache_Controller.Data_All_Tokens | 81637 12.54% 12.54% | 81865 12.57% 25.11% | 81340 12.49% 37.60% | 81615 12.53% 50.13% | 81335 12.49% 62.62% | 81198 12.47% 75.09% | 81224 12.47% 87.56% | 81006 12.44% 100.00% +system.ruby.L1Cache_Controller.Data_All_Tokens::total 651220 +system.ruby.L1Cache_Controller.Ack | 2 18.18% 18.18% | 2 18.18% 36.36% | 3 27.27% 63.64% | 0 0.00% 63.64% | 0 0.00% 63.64% | 1 9.09% 72.73% | 2 18.18% 90.91% | 1 9.09% 100.00% +system.ruby.L1Cache_Controller.Ack::total 11 +system.ruby.L1Cache_Controller.Ack_All_Tokens | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Ack_All_Tokens::total 3 -system.ruby.L1Cache_Controller.Transient_Local_GETX | 195106 12.49% 12.49% | 195050 12.49% 24.98% | 195093 12.49% 37.47% | 195313 12.51% 49.98% | 195440 12.51% 62.49% | 195030 12.49% 74.98% | 195367 12.51% 87.49% | 195357 12.51% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1561756 -system.ruby.L1Cache_Controller.Transient_Local_GETS | 352347 12.51% 12.51% | 351718 12.49% 24.99% | 352073 12.50% 37.49% | 352195 12.50% 50.00% | 351891 12.49% 62.49% | 352426 12.51% 75.00% | 352090 12.50% 87.50% | 352196 12.50% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2816936 -system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 4 -system.ruby.L1Cache_Controller.Persistent_GETX | 13616 12.50% 12.50% | 13644 12.52% 25.02% | 13615 12.50% 37.52% | 13572 12.46% 49.97% | 13607 12.49% 62.46% | 13620 12.50% 74.96% | 13688 12.56% 87.53% | 13592 12.47% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETX::total 108954 -system.ruby.L1Cache_Controller.Persistent_GETS | 24975 12.49% 12.49% | 24920 12.47% 24.96% | 24971 12.49% 37.45% | 24992 12.50% 49.96% | 25025 12.52% 62.48% | 25035 12.52% 75.00% | 25004 12.51% 87.51% | 24964 12.49% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETS::total 199886 -system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 3 -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 49211 12.50% 12.50% | 49238 12.51% 25.01% | 49216 12.50% 37.52% | 49238 12.51% 50.03% | 49170 12.49% 62.52% | 49145 12.49% 75.01% | 49110 12.48% 87.49% | 49245 12.51% 100.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 393573 -system.ruby.L1Cache_Controller.Request_Timeout | 33208 12.52% 12.52% | 33841 12.76% 25.27% | 33107 12.48% 37.75% | 32943 12.42% 50.17% | 33071 12.47% 62.64% | 33150 12.50% 75.14% | 33269 12.54% 87.68% | 32690 12.32% 100.00% -system.ruby.L1Cache_Controller.Request_Timeout::total 265279 -system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 5 5.95% 5.95% | 11 13.10% 19.05% | 8 9.52% 28.57% | 9 10.71% 39.29% | 15 17.86% 57.14% | 10 11.90% 69.05% | 10 11.90% 80.95% | 16 19.05% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 84 -system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 9 7.26% 7.26% | 6 4.84% 12.10% | 13 10.48% 22.58% | 12 9.68% 32.26% | 24 19.35% 51.61% | 23 18.55% 70.16% | 18 14.52% 84.68% | 19 15.32% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 124 -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 77853 12.48% 12.48% | 78535 12.59% 25.08% | 78143 12.53% 37.60% | 77810 12.48% 50.08% | 77949 12.50% 62.58% | 77828 12.48% 75.06% | 77835 12.48% 87.54% | 77726 12.46% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 623679 -system.ruby.L1Cache_Controller.NP.Load | 50055 12.44% 12.44% | 50685 12.60% 25.04% | 50318 12.51% 37.55% | 50200 12.48% 50.03% | 50501 12.55% 62.59% | 49984 12.43% 75.01% | 50303 12.51% 87.52% | 50198 12.48% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 402244 -system.ruby.L1Cache_Controller.NP.Store | 27993 12.55% 12.55% | 28040 12.57% 25.13% | 28001 12.56% 37.68% | 27785 12.46% 50.14% | 27658 12.40% 62.54% | 28065 12.58% 75.13% | 27732 12.44% 87.56% | 27741 12.44% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 223015 -system.ruby.L1Cache_Controller.NP.Data_Shared | 14 11.86% 11.86% | 17 14.41% 26.27% | 16 13.56% 39.83% | 13 11.02% 50.85% | 8 6.78% 57.63% | 14 11.86% 69.49% | 17 14.41% 83.90% | 19 16.10% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Shared::total 118 -system.ruby.L1Cache_Controller.NP.Data_Owner | 6 6.38% 6.38% | 15 15.96% 22.34% | 12 12.77% 35.11% | 12 12.77% 47.87% | 8 8.51% 56.38% | 12 12.77% 69.15% | 11 11.70% 80.85% | 18 19.15% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Owner::total 94 -system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 4014 12.52% 12.52% | 4049 12.63% 25.15% | 4005 12.49% 37.64% | 3980 12.41% 50.05% | 3998 12.47% 62.52% | 3995 12.46% 74.98% | 4003 12.48% 87.46% | 4021 12.54% 100.00% -system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 32065 -system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 2 40.00% 100.00% -system.ruby.L1Cache_Controller.NP.Ack::total 5 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194672 12.49% 12.49% | 194611 12.49% 24.98% | 194621 12.49% 37.47% | 194855 12.51% 49.98% | 195006 12.52% 62.49% | 194570 12.49% 74.98% | 194932 12.51% 87.49% | 194889 12.51% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1558156 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 351505 12.51% 12.51% | 350885 12.49% 24.99% | 351223 12.50% 37.49% | 351366 12.50% 49.99% | 351081 12.49% 62.49% | 351596 12.51% 75.00% | 351307 12.50% 87.50% | 351400 12.50% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2810363 -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 43131 12.51% 12.51% | 43109 12.51% 25.02% | 43069 12.50% 37.52% | 43054 12.49% 50.01% | 43044 12.49% 62.50% | 43094 12.50% 75.00% | 43053 12.49% 87.49% | 43119 12.51% 100.00% -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 344673 -system.ruby.L1Cache_Controller.I.Load | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 1 -system.ruby.L1Cache_Controller.I.L1_Replacement | 84 12.37% 12.37% | 83 12.22% 24.59% | 95 13.99% 38.59% | 78 11.49% 50.07% | 80 11.78% 61.86% | 95 13.99% 75.85% | 77 11.34% 87.19% | 87 12.81% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 679 -system.ruby.L1Cache_Controller.I.Data_All_Tokens | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 3 -system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.S.L1_Replacement | 202 12.72% 12.72% | 192 12.09% 24.81% | 201 12.66% 37.47% | 180 11.34% 48.80% | 203 12.78% 61.59% | 202 12.72% 74.31% | 204 12.85% 87.15% | 204 12.85% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1588 -system.ruby.L1Cache_Controller.S.Data_Shared | 1 6.25% 6.25% | 1 6.25% 12.50% | 2 12.50% 25.00% | 4 25.00% 50.00% | 1 6.25% 56.25% | 0 0.00% 56.25% | 4 25.00% 81.25% | 3 18.75% 100.00% -system.ruby.L1Cache_Controller.S.Data_Shared::total 16 -system.ruby.L1Cache_Controller.S.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETX | 196232 12.51% 12.51% | 195799 12.48% 24.99% | 196154 12.51% 37.50% | 195687 12.48% 49.98% | 196316 12.52% 62.49% | 196150 12.51% 75.00% | 196028 12.50% 87.50% | 196103 12.50% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1568469 +system.ruby.L1Cache_Controller.Transient_Local_GETS | 351777 12.49% 12.49% | 352077 12.50% 24.99% | 352116 12.50% 37.48% | 352186 12.50% 49.99% | 351951 12.49% 62.48% | 352239 12.50% 74.98% | 352314 12.51% 87.49% | 352412 12.51% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2817072 +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 1 +system.ruby.L1Cache_Controller.Persistent_GETX | 11862 12.44% 12.44% | 11847 12.42% 24.86% | 11952 12.53% 37.39% | 11999 12.58% 49.97% | 11950 12.53% 62.49% | 11869 12.44% 74.94% | 11944 12.52% 87.46% | 11962 12.54% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETX::total 95385 +system.ruby.L1Cache_Controller.Persistent_GETS | 21376 12.51% 12.51% | 21244 12.43% 24.95% | 21303 12.47% 37.41% | 21384 12.52% 49.93% | 21354 12.50% 62.43% | 21395 12.52% 74.95% | 21385 12.52% 87.47% | 21409 12.53% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETS::total 170850 +system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 1 +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 42523 12.51% 12.51% | 42669 12.56% 25.07% | 42506 12.51% 37.57% | 42378 12.47% 50.04% | 42457 12.49% 62.54% | 42497 12.50% 75.04% | 42432 12.49% 87.53% | 42390 12.47% 100.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 339852 +system.ruby.L1Cache_Controller.Request_Timeout | 32684 12.55% 12.55% | 33861 13.00% 25.55% | 32124 12.33% 37.89% | 31734 12.19% 50.07% | 32267 12.39% 62.46% | 33153 12.73% 75.19% | 32442 12.46% 87.65% | 32169 12.35% 100.00% +system.ruby.L1Cache_Controller.Request_Timeout::total 260434 +system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 8 11.27% 11.27% | 9 12.68% 23.94% | 6 8.45% 32.39% | 10 14.08% 46.48% | 9 12.68% 59.15% | 13 18.31% 77.46% | 8 11.27% 88.73% | 8 11.27% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 71 +system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 17 15.45% 15.45% | 9 8.18% 23.64% | 12 10.91% 34.55% | 12 10.91% 45.45% | 12 10.91% 56.36% | 16 14.55% 70.91% | 13 11.82% 82.73% | 19 17.27% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 110 +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78263 12.53% 12.53% | 78422 12.55% 25.08% | 78036 12.49% 37.57% | 78402 12.55% 50.12% | 77999 12.49% 62.61% | 77876 12.47% 75.08% | 77945 12.48% 87.55% | 77747 12.45% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 624690 +system.ruby.L1Cache_Controller.NP.Load | 50641 12.59% 12.59% | 50346 12.51% 25.10% | 50307 12.51% 37.61% | 50235 12.49% 50.10% | 50465 12.54% 62.64% | 50181 12.47% 75.11% | 50103 12.45% 87.57% | 50012 12.43% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 402290 +system.ruby.L1Cache_Controller.NP.Store | 27827 12.42% 12.42% | 28259 12.62% 25.04% | 27909 12.46% 37.50% | 28369 12.67% 50.16% | 27742 12.39% 62.55% | 27906 12.46% 75.01% | 28031 12.51% 87.52% | 27951 12.48% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 223994 +system.ruby.L1Cache_Controller.NP.Data_Shared | 12 12.37% 12.37% | 13 13.40% 25.77% | 9 9.28% 35.05% | 11 11.34% 46.39% | 17 17.53% 63.92% | 13 13.40% 77.32% | 13 13.40% 90.72% | 9 9.28% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Shared::total 97 +system.ruby.L1Cache_Controller.NP.Data_Owner | 7 7.53% 7.53% | 9 9.68% 17.20% | 9 9.68% 26.88% | 12 12.90% 39.78% | 17 18.28% 58.06% | 10 10.75% 68.82% | 15 16.13% 84.95% | 14 15.05% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Owner::total 93 +system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 3330 12.69% 12.69% | 3406 12.98% 25.66% | 3272 12.47% 38.13% | 3177 12.10% 50.24% | 3300 12.57% 62.81% | 3285 12.52% 75.33% | 3247 12.37% 87.70% | 3229 12.30% 100.00% +system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 26246 +system.ruby.L1Cache_Controller.NP.Ack | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.NP.Ack::total 4 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 195766 12.51% 12.51% | 195334 12.48% 24.99% | 195705 12.51% 37.50% | 195249 12.48% 49.98% | 195873 12.52% 62.49% | 195671 12.50% 75.00% | 195587 12.50% 87.50% | 195671 12.50% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1564856 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 350998 12.49% 12.49% | 351273 12.50% 24.99% | 351329 12.50% 37.48% | 351358 12.50% 49.99% | 351184 12.49% 62.48% | 351458 12.50% 74.98% | 351554 12.51% 87.49% | 351604 12.51% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2810758 +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 37177 12.51% 12.51% | 37151 12.50% 25.00% | 37150 12.50% 37.50% | 37175 12.50% 50.00% | 37190 12.51% 62.51% | 37145 12.49% 75.01% | 37164 12.50% 87.51% | 37143 12.49% 100.00% +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 297295 +system.ruby.L1Cache_Controller.I.L1_Replacement | 77 11.83% 11.83% | 84 12.90% 24.73% | 86 13.21% 37.94% | 78 11.98% 49.92% | 83 12.75% 62.67% | 85 13.06% 75.73% | 91 13.98% 89.71% | 67 10.29% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 651 +system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 3 +system.ruby.L1Cache_Controller.I.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Persistent_GETS::total 3 +system.ruby.L1Cache_Controller.S.L1_Replacement | 210 13.21% 13.21% | 190 11.95% 25.16% | 180 11.32% 36.48% | 210 13.21% 49.69% | 206 12.96% 62.64% | 196 12.33% 74.97% | 187 11.76% 86.73% | 211 13.27% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1590 +system.ruby.L1Cache_Controller.S.Data_Shared | 5 25.00% 25.00% | 2 10.00% 35.00% | 0 0.00% 35.00% | 2 10.00% 45.00% | 2 10.00% 55.00% | 3 15.00% 70.00% | 1 5.00% 75.00% | 5 25.00% 100.00% +system.ruby.L1Cache_Controller.S.Data_Shared::total 20 +system.ruby.L1Cache_Controller.S.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.L1Cache_Controller.S.Data_Owner::total 1 -system.ruby.L1Cache_Controller.S.Data_All_Tokens | 1 9.09% 9.09% | 0 0.00% 9.09% | 1 9.09% 18.18% | 2 18.18% 36.36% | 2 18.18% 54.55% | 3 27.27% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% -system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 11 -system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 2 -system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 4 -system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETX::total 3 -system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 3 -system.ruby.L1Cache_Controller.O.L1_Replacement | 56 11.86% 11.86% | 64 13.56% 25.42% | 50 10.59% 36.02% | 70 14.83% 50.85% | 61 12.92% 63.77% | 57 12.08% 75.85% | 51 10.81% 86.65% | 63 13.35% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 472 -system.ruby.L1Cache_Controller.O.Data_All_Tokens | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 3 -system.ruby.L1Cache_Controller.O.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.S.Data_All_Tokens | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 5 +system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 3 +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 1 +system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Persistent_GETX::total 2 +system.ruby.L1Cache_Controller.S.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.S.Persistent_GETS::total 1 +system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 1 +system.ruby.L1Cache_Controller.O.L1_Replacement | 58 12.18% 12.18% | 57 11.97% 24.16% | 45 9.45% 33.61% | 63 13.24% 46.85% | 62 13.03% 59.87% | 56 11.76% 71.64% | 63 13.24% 84.87% | 72 15.13% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 476 +system.ruby.L1Cache_Controller.O.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 4 +system.ruby.L1Cache_Controller.O.Ack | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.O.Ack::total 1 -system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 2 -system.ruby.L1Cache_Controller.O.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Persistent_GETX::total 2 -system.ruby.L1Cache_Controller.O.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETX::total 2 +system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 1 +system.ruby.L1Cache_Controller.O.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.O.Persistent_GETS::total 1 -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 8 16.33% 16.33% | 8 16.33% 32.65% | 3 6.12% 38.78% | 7 14.29% 53.06% | 7 14.29% 67.35% | 5 10.20% 77.55% | 7 14.29% 91.84% | 4 8.16% 100.00% -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 49 -system.ruby.L1Cache_Controller.M.Load | 5 16.67% 16.67% | 3 10.00% 26.67% | 0 0.00% 26.67% | 6 20.00% 46.67% | 3 10.00% 56.67% | 5 16.67% 73.33% | 4 13.33% 86.67% | 4 13.33% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 30 -system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 28.57% 28.57% | 3 42.86% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 7 -system.ruby.L1Cache_Controller.M.L1_Replacement | 49776 12.44% 12.44% | 50403 12.60% 25.04% | 50051 12.51% 37.55% | 49936 12.48% 50.04% | 50218 12.55% 62.59% | 49702 12.42% 75.01% | 50042 12.51% 87.52% | 49911 12.48% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 400039 -system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 22 14.10% 14.10% | 21 13.46% 27.56% | 23 14.74% 42.31% | 18 11.54% 53.85% | 15 9.62% 63.46% | 15 9.62% 73.08% | 21 13.46% 86.54% | 21 13.46% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 156 -system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 35 12.24% 12.24% | 37 12.94% 25.17% | 32 11.19% 36.36% | 44 15.38% 51.75% | 40 13.99% 65.73% | 32 11.19% 76.92% | 29 10.14% 87.06% | 37 12.94% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 286 -system.ruby.L1Cache_Controller.M.Persistent_GETX | 7 10.61% 10.61% | 10 15.15% 25.76% | 9 13.64% 39.39% | 8 12.12% 51.52% | 12 18.18% 69.70% | 7 10.61% 80.30% | 6 9.09% 89.39% | 7 10.61% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETX::total 66 -system.ruby.L1Cache_Controller.M.Persistent_GETS | 15 16.48% 16.48% | 10 10.99% 27.47% | 17 18.68% 46.15% | 14 15.38% 61.54% | 7 7.69% 69.23% | 11 12.09% 81.32% | 9 9.89% 91.21% | 8 8.79% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETS::total 91 -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 294 12.03% 12.03% | 300 12.27% 24.30% | 315 12.89% 37.19% | 322 13.18% 50.37% | 304 12.44% 62.81% | 298 12.19% 75.00% | 316 12.93% 87.93% | 295 12.07% 100.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 2444 -system.ruby.L1Cache_Controller.MM.Load | 4 23.53% 23.53% | 2 11.76% 35.29% | 3 17.65% 52.94% | 1 5.88% 58.82% | 2 11.76% 70.59% | 1 5.88% 76.47% | 2 11.76% 88.24% | 2 11.76% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 17 -system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 4 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 27953 12.55% 12.55% | 28013 12.58% 25.13% | 27961 12.55% 37.68% | 27754 12.46% 50.14% | 27630 12.41% 62.55% | 28013 12.58% 75.13% | 27692 12.43% 87.56% | 27705 12.44% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222721 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 14 17.07% 17.07% | 8 9.76% 26.83% | 13 15.85% 42.68% | 7 8.54% 51.22% | 8 9.76% 60.98% | 15 18.29% 79.27% | 8 9.76% 89.02% | 9 10.98% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 82 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 23 15.33% 15.33% | 21 14.00% 29.33% | 25 16.67% 46.00% | 19 12.67% 58.67% | 10 6.67% 65.33% | 19 12.67% 78.00% | 16 10.67% 88.67% | 17 11.33% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 150 -system.ruby.L1Cache_Controller.MM.Persistent_GETX | 5 15.15% 15.15% | 1 3.03% 18.18% | 6 18.18% 36.36% | 4 12.12% 48.48% | 2 6.06% 54.55% | 8 24.24% 78.79% | 6 18.18% 96.97% | 1 3.03% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 33 -system.ruby.L1Cache_Controller.MM.Persistent_GETS | 6 8.57% 8.57% | 11 15.71% 24.29% | 8 11.43% 35.71% | 9 12.86% 48.57% | 9 12.86% 61.43% | 10 14.29% 75.71% | 6 8.57% 84.29% | 11 15.71% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 70 -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 152 11.86% 11.86% | 150 11.70% 23.56% | 155 12.09% 35.65% | 177 13.81% 49.45% | 183 14.27% 63.73% | 147 11.47% 75.20% | 173 13.49% 88.69% | 145 11.31% 100.00% -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 1282 -system.ruby.L1Cache_Controller.M_W.Load | 8 11.59% 11.59% | 10 14.49% 26.09% | 10 14.49% 40.58% | 5 7.25% 47.83% | 14 20.29% 68.12% | 7 10.14% 78.26% | 8 11.59% 89.86% | 7 10.14% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 69 -system.ruby.L1Cache_Controller.M_W.Store | 6 28.57% 28.57% | 2 9.52% 38.10% | 4 19.05% 57.14% | 1 4.76% 61.90% | 1 4.76% 66.67% | 2 9.52% 76.19% | 0 0.00% 76.19% | 5 23.81% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 21 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 361207 12.32% 12.32% | 368703 12.58% 24.90% | 366785 12.51% 37.41% | 366334 12.50% 49.91% | 368143 12.56% 62.47% | 365562 12.47% 74.94% | 366558 12.50% 87.44% | 368107 12.56% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2931399 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 57 12.08% 12.08% | 59 12.50% 24.58% | 64 13.56% 38.14% | 52 11.02% 49.15% | 55 11.65% 60.81% | 72 15.25% 76.06% | 57 12.08% 88.14% | 56 11.86% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 472 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 105 12.95% 12.95% | 101 12.45% 25.40% | 104 12.82% 38.22% | 106 13.07% 51.29% | 91 11.22% 62.52% | 110 13.56% 76.08% | 95 11.71% 87.79% | 99 12.21% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 811 -system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 1 2.13% 2.13% | 6 12.77% 14.89% | 5 10.64% 25.53% | 6 12.77% 38.30% | 12 25.53% 63.83% | 6 12.77% 76.60% | 4 8.51% 85.11% | 7 14.89% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 47 -system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 8 9.20% 9.20% | 4 4.60% 13.79% | 10 11.49% 25.29% | 8 9.20% 34.48% | 16 18.39% 52.87% | 13 14.94% 67.82% | 14 16.09% 83.91% | 14 16.09% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 87 -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 450 12.82% 12.82% | 461 13.13% 25.95% | 453 12.90% 38.85% | 452 12.87% 51.72% | 381 10.85% 62.57% | 401 11.42% 74.00% | 458 13.04% 87.04% | 455 12.96% 100.00% -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3511 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 1 2.08% 2.08% | 6 12.50% 14.58% | 5 10.42% 25.00% | 6 12.50% 37.50% | 12 25.00% 62.50% | 6 12.50% 75.00% | 4 8.33% 83.33% | 8 16.67% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 48 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 8 8.60% 8.60% | 5 5.38% 13.98% | 10 10.75% 24.73% | 10 10.75% 35.48% | 17 18.28% 53.76% | 13 13.98% 67.74% | 15 16.13% 83.87% | 15 16.13% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 93 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 49852 12.44% 12.44% | 50481 12.60% 25.04% | 50132 12.51% 37.56% | 50020 12.49% 50.04% | 50291 12.55% 62.60% | 49763 12.42% 75.02% | 50106 12.51% 87.52% | 49984 12.48% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 400629 -system.ruby.L1Cache_Controller.MM_W.Load | 2 8.00% 8.00% | 3 12.00% 20.00% | 2 8.00% 28.00% | 4 16.00% 44.00% | 3 12.00% 56.00% | 7 28.00% 84.00% | 3 12.00% 96.00% | 1 4.00% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 25 -system.ruby.L1Cache_Controller.MM_W.Store | 2 14.29% 14.29% | 3 21.43% 35.71% | 2 14.29% 50.00% | 3 21.43% 71.43% | 1 7.14% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00% +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 9 16.67% 16.67% | 2 3.70% 20.37% | 3 5.56% 25.93% | 9 16.67% 42.59% | 7 12.96% 55.56% | 8 14.81% 70.37% | 8 14.81% 85.19% | 8 14.81% 100.00% +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 54 +system.ruby.L1Cache_Controller.M.Load | 5 17.86% 17.86% | 4 14.29% 32.14% | 1 3.57% 35.71% | 2 7.14% 42.86% | 5 17.86% 60.71% | 1 3.57% 64.29% | 4 14.29% 78.57% | 6 21.43% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 28 +system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 37.50% 37.50% | 1 12.50% 50.00% | 0 0.00% 50.00% | 1 12.50% 62.50% | 1 12.50% 75.00% | 2 25.00% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 8 +system.ruby.L1Cache_Controller.M.L1_Replacement | 50355 12.59% 12.59% | 50070 12.52% 25.10% | 50054 12.51% 37.62% | 49943 12.48% 50.10% | 50172 12.54% 62.64% | 49895 12.47% 75.12% | 49825 12.46% 87.57% | 49715 12.43% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 400029 +system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 15 9.32% 9.32% | 25 15.53% 24.84% | 19 11.80% 36.65% | 21 13.04% 49.69% | 24 14.91% 64.60% | 23 14.29% 78.88% | 24 14.91% 93.79% | 10 6.21% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 161 +system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 36 12.63% 12.63% | 38 13.33% 25.96% | 24 8.42% 34.39% | 39 13.68% 48.07% | 36 12.63% 60.70% | 30 10.53% 71.23% | 38 13.33% 84.56% | 44 15.44% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 285 +system.ruby.L1Cache_Controller.M.Persistent_GETX | 11 16.42% 16.42% | 9 13.43% 29.85% | 10 14.93% 44.78% | 4 5.97% 50.75% | 8 11.94% 62.69% | 7 10.45% 73.13% | 11 16.42% 89.55% | 7 10.45% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETX::total 67 +system.ruby.L1Cache_Controller.M.Persistent_GETS | 17 13.82% 13.82% | 16 13.01% 26.83% | 18 14.63% 41.46% | 24 19.51% 60.98% | 15 12.20% 73.17% | 9 7.32% 80.49% | 10 8.13% 88.62% | 14 11.38% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETS::total 123 +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 274 12.00% 12.00% | 302 13.22% 25.22% | 296 12.96% 38.18% | 287 12.57% 50.74% | 274 12.00% 62.74% | 276 12.08% 74.82% | 270 11.82% 86.65% | 305 13.35% 100.00% +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 2284 +system.ruby.L1Cache_Controller.MM.Load | 1 6.67% 6.67% | 2 13.33% 20.00% | 1 6.67% 26.67% | 3 20.00% 46.67% | 2 13.33% 60.00% | 4 26.67% 86.67% | 0 0.00% 86.67% | 2 13.33% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 15 +system.ruby.L1Cache_Controller.MM.Store | 1 10.00% 10.00% | 2 20.00% 30.00% | 1 10.00% 40.00% | 0 0.00% 40.00% | 2 20.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 10 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 27793 12.42% 12.42% | 28225 12.62% 25.04% | 27866 12.46% 37.49% | 28335 12.66% 50.16% | 27712 12.39% 62.54% | 27881 12.46% 75.01% | 27995 12.51% 87.52% | 27922 12.48% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 223729 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 11 12.94% 12.94% | 15 17.65% 30.59% | 10 11.76% 42.35% | 10 11.76% 54.12% | 9 10.59% 64.71% | 15 17.65% 82.35% | 8 9.41% 91.76% | 7 8.24% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 85 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 18 13.14% 13.14% | 16 11.68% 24.82% | 19 13.87% 38.69% | 12 8.76% 47.45% | 16 11.68% 59.12% | 11 8.03% 67.15% | 25 18.25% 85.40% | 20 14.60% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 137 +system.ruby.L1Cache_Controller.MM.Persistent_GETX | 3 9.68% 9.68% | 3 9.68% 19.35% | 4 12.90% 32.26% | 7 22.58% 54.84% | 3 9.68% 64.52% | 5 16.13% 80.65% | 3 9.68% 90.32% | 3 9.68% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 31 +system.ruby.L1Cache_Controller.MM.Persistent_GETS | 4 8.16% 8.16% | 5 10.20% 18.37% | 11 22.45% 40.82% | 7 14.29% 55.10% | 6 12.24% 67.35% | 2 4.08% 71.43% | 8 16.33% 87.76% | 6 12.24% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 49 +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 147 11.73% 11.73% | 165 13.17% 24.90% | 166 13.25% 38.15% | 141 11.25% 49.40% | 139 11.09% 60.49% | 187 14.92% 75.42% | 164 13.09% 88.51% | 144 11.49% 100.00% +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 1253 +system.ruby.L1Cache_Controller.M_W.Load | 6 12.77% 12.77% | 6 12.77% 25.53% | 4 8.51% 34.04% | 9 19.15% 53.19% | 3 6.38% 59.57% | 4 8.51% 68.09% | 8 17.02% 85.11% | 7 14.89% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 47 +system.ruby.L1Cache_Controller.M_W.Store | 3 11.54% 11.54% | 3 11.54% 23.08% | 3 11.54% 34.62% | 1 3.85% 38.46% | 4 15.38% 53.85% | 4 15.38% 69.23% | 6 23.08% 92.31% | 2 7.69% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 26 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 366785 12.57% 12.57% | 364136 12.48% 25.04% | 364171 12.48% 37.52% | 365652 12.53% 50.05% | 367583 12.59% 62.64% | 363631 12.46% 75.10% | 363794 12.46% 87.57% | 362856 12.43% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2918608 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 64 13.06% 13.06% | 57 11.63% 24.69% | 61 12.45% 37.14% | 57 11.63% 48.78% | 64 13.06% 61.84% | 58 11.84% 73.67% | 63 12.86% 86.53% | 66 13.47% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 490 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 124 15.10% 15.10% | 103 12.55% 27.65% | 88 10.72% 38.37% | 113 13.76% 52.13% | 92 11.21% 63.34% | 100 12.18% 75.52% | 104 12.67% 88.19% | 97 11.81% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 821 +system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 7 14.58% 14.58% | 4 8.33% 22.92% | 4 8.33% 31.25% | 5 10.42% 41.67% | 7 14.58% 56.25% | 10 20.83% 77.08% | 5 10.42% 87.50% | 6 12.50% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 48 +system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 11 15.94% 15.94% | 8 11.59% 27.54% | 7 10.14% 37.68% | 7 10.14% 47.83% | 5 7.25% 55.07% | 8 11.59% 66.67% | 10 14.49% 81.16% | 13 18.84% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 69 +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 444 13.26% 13.26% | 440 13.14% 26.40% | 447 13.35% 39.76% | 403 12.04% 51.79% | 444 13.26% 65.05% | 402 12.01% 77.06% | 363 10.84% 87.90% | 405 12.10% 100.00% +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3348 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 7 14.00% 14.00% | 4 8.00% 22.00% | 4 8.00% 30.00% | 5 10.00% 40.00% | 7 14.00% 54.00% | 12 24.00% 78.00% | 5 10.00% 88.00% | 6 12.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 50 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 11 15.71% 15.71% | 8 11.43% 27.14% | 7 10.00% 37.14% | 7 10.00% 47.14% | 5 7.14% 54.29% | 9 12.86% 67.14% | 10 14.29% 81.43% | 13 18.57% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 70 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50434 12.59% 12.59% | 50157 12.52% 25.11% | 50128 12.51% 37.62% | 50032 12.49% 50.10% | 50253 12.54% 62.65% | 49963 12.47% 75.12% | 49907 12.46% 87.57% | 49791 12.43% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 400665 +system.ruby.L1Cache_Controller.MM_W.Load | 8 24.24% 24.24% | 1 3.03% 27.27% | 1 3.03% 30.30% | 3 9.09% 39.39% | 4 12.12% 51.52% | 3 9.09% 60.61% | 4 12.12% 72.73% | 9 27.27% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 33 +system.ruby.L1Cache_Controller.MM_W.Store | 3 21.43% 21.43% | 1 7.14% 28.57% | 2 14.29% 42.86% | 1 7.14% 50.00% | 2 14.29% 64.29% | 1 7.14% 71.43% | 3 21.43% 92.86% | 1 7.14% 100.00% system.ruby.L1Cache_Controller.MM_W.Store::total 14 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 205695 12.56% 12.56% | 204042 12.46% 25.01% | 205541 12.55% 37.56% | 204063 12.46% 50.01% | 203908 12.45% 62.46% | 207650 12.68% 75.14% | 205078 12.52% 87.66% | 202224 12.34% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1638201 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 28 10.98% 10.98% | 23 9.02% 20.00% | 40 15.69% 35.69% | 41 16.08% 51.76% | 33 12.94% 64.71% | 35 13.73% 78.43% | 23 9.02% 87.45% | 32 12.55% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 255 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 61 13.17% 13.17% | 44 9.50% 22.68% | 64 13.82% 36.50% | 70 15.12% 51.62% | 76 16.41% 68.03% | 48 10.37% 78.40% | 51 11.02% 89.42% | 49 10.58% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 463 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 4 11.76% 11.76% | 5 14.71% 26.47% | 3 8.82% 35.29% | 3 8.82% 44.12% | 3 8.82% 52.94% | 4 11.76% 64.71% | 5 14.71% 79.41% | 7 20.59% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 34 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 1 3.57% 3.57% | 1 3.57% 7.14% | 3 10.71% 17.86% | 1 3.57% 21.43% | 6 21.43% 42.86% | 10 35.71% 78.57% | 2 7.14% 85.71% | 4 14.29% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 28 -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 239 12.35% 12.35% | 242 12.51% 24.86% | 240 12.40% 37.26% | 257 13.28% 50.54% | 244 12.61% 63.15% | 254 13.13% 76.28% | 213 11.01% 87.29% | 246 12.71% 100.00% -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 1935 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 4 11.11% 11.11% | 5 13.89% 25.00% | 3 8.33% 33.33% | 3 8.33% 41.67% | 3 8.33% 50.00% | 4 11.11% 61.11% | 6 16.67% 77.78% | 8 22.22% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 36 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 1 3.23% 3.23% | 1 3.23% 6.45% | 3 9.68% 16.13% | 2 6.45% 22.58% | 7 22.58% 45.16% | 10 32.26% 77.42% | 3 9.68% 87.10% | 4 12.90% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 31 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 28001 12.55% 12.55% | 28054 12.58% 25.13% | 28011 12.56% 37.69% | 27790 12.46% 50.15% | 27658 12.40% 62.55% | 28065 12.58% 75.13% | 27729 12.43% 87.56% | 27742 12.44% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223050 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 295093 12.61% 12.61% | 294925 12.61% 25.22% | 294016 12.57% 37.79% | 291033 12.44% 50.23% | 290166 12.40% 62.64% | 294109 12.57% 75.21% | 290971 12.44% 87.65% | 288911 12.35% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2339224 -system.ruby.L1Cache_Controller.IM.Data_Owner | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 206388 12.57% 12.57% | 205534 12.52% 25.09% | 205266 12.50% 37.60% | 207686 12.65% 50.25% | 201809 12.29% 62.54% | 204178 12.44% 74.98% | 204640 12.47% 87.44% | 206137 12.56% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1641638 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 39 15.06% 15.06% | 31 11.97% 27.03% | 29 11.20% 38.22% | 28 10.81% 49.03% | 36 13.90% 62.93% | 31 11.97% 74.90% | 35 13.51% 88.42% | 30 11.58% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 259 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 58 12.18% 12.18% | 74 15.55% 27.73% | 62 13.03% 40.76% | 36 7.56% 48.32% | 61 12.82% 61.13% | 66 13.87% 75.00% | 64 13.45% 88.45% | 55 11.55% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 476 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 1 5.00% 5.00% | 5 25.00% 30.00% | 2 10.00% 40.00% | 4 20.00% 60.00% | 2 10.00% 70.00% | 1 5.00% 75.00% | 3 15.00% 90.00% | 2 10.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 20 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 6 15.38% 15.38% | 1 2.56% 17.95% | 5 12.82% 30.77% | 5 12.82% 43.59% | 7 17.95% 61.54% | 7 17.95% 79.49% | 3 7.69% 87.18% | 5 12.82% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 39 +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 228 12.34% 12.34% | 250 13.53% 25.87% | 228 12.34% 38.20% | 228 12.34% 50.54% | 244 13.20% 63.74% | 231 12.50% 76.24% | 214 11.58% 87.82% | 225 12.18% 100.00% +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 1848 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 1 4.76% 4.76% | 5 23.81% 28.57% | 2 9.52% 38.10% | 5 23.81% 61.90% | 2 9.52% 71.43% | 1 4.76% 76.19% | 3 14.29% 90.48% | 2 9.52% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 21 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 6 15.00% 15.00% | 1 2.50% 17.50% | 5 12.50% 30.00% | 5 12.50% 42.50% | 7 17.50% 60.00% | 7 17.50% 77.50% | 3 7.50% 85.00% | 6 15.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 40 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 27829 12.42% 12.42% | 28265 12.62% 25.04% | 27908 12.46% 37.50% | 28370 12.66% 50.16% | 27746 12.39% 62.55% | 27913 12.46% 75.01% | 28038 12.52% 87.52% | 27956 12.48% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 224025 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 296218 12.51% 12.51% | 301018 12.71% 25.23% | 295962 12.50% 37.73% | 297411 12.56% 50.29% | 293177 12.38% 62.67% | 292697 12.36% 75.04% | 294725 12.45% 87.49% | 296256 12.51% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2367464 +system.ruby.L1Cache_Controller.IM.Data_Owner | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.IM.Data_Owner::total 3 -system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 28000 12.55% 12.55% | 28057 12.58% 25.13% | 28014 12.56% 37.68% | 27793 12.46% 50.14% | 27665 12.40% 62.54% | 28078 12.59% 75.13% | 27738 12.43% 87.56% | 27748 12.44% 100.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223093 -system.ruby.L1Cache_Controller.IM.Ack | 0 0.00% 0.00% | 1 16.67% 16.67% | 0 0.00% 16.67% | 2 33.33% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 6 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 90 11.97% 11.97% | 100 13.30% 25.27% | 94 12.50% 37.77% | 98 13.03% 50.80% | 73 9.71% 60.51% | 97 12.90% 73.40% | 103 13.70% 87.10% | 97 12.90% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 752 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 161 12.28% 12.28% | 188 14.34% 26.62% | 172 13.12% 39.74% | 163 12.43% 52.17% | 159 12.13% 64.30% | 175 13.35% 77.65% | 133 10.14% 87.80% | 160 12.20% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1311 -system.ruby.L1Cache_Controller.IM.Persistent_GETX | 7 9.86% 9.86% | 13 18.31% 28.17% | 8 11.27% 39.44% | 11 15.49% 54.93% | 11 15.49% 70.42% | 8 11.27% 81.69% | 6 8.45% 90.14% | 7 9.86% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 71 -system.ruby.L1Cache_Controller.IM.Persistent_GETS | 12 10.34% 10.34% | 7 6.03% 16.38% | 16 13.79% 30.17% | 11 9.48% 39.66% | 15 12.93% 52.59% | 20 17.24% 69.83% | 18 15.52% 85.34% | 17 14.66% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 116 -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 1699 12.54% 12.54% | 1672 12.34% 24.89% | 1699 12.54% 37.43% | 1727 12.75% 50.18% | 1702 12.57% 62.75% | 1679 12.40% 75.15% | 1654 12.21% 87.36% | 1712 12.64% 100.00% -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 13544 -system.ruby.L1Cache_Controller.IM.Request_Timeout | 11980 12.55% 12.55% | 12224 12.80% 25.35% | 11886 12.45% 37.80% | 11479 12.02% 49.82% | 11994 12.56% 62.39% | 12457 13.05% 75.43% | 12326 12.91% 88.35% | 11127 11.65% 100.00% -system.ruby.L1Cache_Controller.IM.Request_Timeout::total 95473 -system.ruby.L1Cache_Controller.OM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 40 57.14% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 30 42.86% 100.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement::total 70 -system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 27833 12.42% 12.42% | 28267 12.62% 25.04% | 27913 12.46% 37.50% | 28379 12.67% 50.16% | 27750 12.39% 62.55% | 27915 12.46% 75.01% | 28038 12.51% 87.52% | 27961 12.48% 100.00% +system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 224056 +system.ruby.L1Cache_Controller.IM.Ack | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 4 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 90 12.28% 12.28% | 99 13.51% 25.78% | 102 13.92% 39.70% | 91 12.41% 52.11% | 75 10.23% 62.35% | 113 15.42% 77.76% | 78 10.64% 88.40% | 85 11.60% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 733 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 148 11.45% 11.45% | 145 11.21% 22.66% | 163 12.61% 35.27% | 181 14.00% 49.27% | 167 12.92% 62.18% | 179 13.84% 76.02% | 159 12.30% 88.32% | 151 11.68% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1293 +system.ruby.L1Cache_Controller.IM.Persistent_GETX | 7 13.21% 13.21% | 8 15.09% 28.30% | 4 7.55% 35.85% | 6 11.32% 47.17% | 11 20.75% 67.92% | 4 7.55% 75.47% | 4 7.55% 83.02% | 9 16.98% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 53 +system.ruby.L1Cache_Controller.IM.Persistent_GETS | 13 10.92% 10.92% | 15 12.61% 23.53% | 13 10.92% 34.45% | 13 10.92% 45.38% | 16 13.45% 58.82% | 10 8.40% 67.23% | 20 16.81% 84.03% | 19 15.97% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 119 +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 1529 13.05% 13.05% | 1520 12.97% 26.02% | 1441 12.30% 38.32% | 1393 11.89% 50.20% | 1425 12.16% 62.37% | 1519 12.96% 75.33% | 1459 12.45% 87.78% | 1432 12.22% 100.00% +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 11718 +system.ruby.L1Cache_Controller.IM.Request_Timeout | 11235 12.07% 12.07% | 12352 13.27% 25.33% | 11420 12.27% 37.60% | 11309 12.15% 49.74% | 11543 12.40% 62.14% | 11451 12.30% 74.44% | 11863 12.74% 87.18% | 11935 12.82% 100.00% +system.ruby.L1Cache_Controller.IM.Request_Timeout::total 93108 +system.ruby.L1Cache_Controller.OM.L1_Replacement | 0 0.00% 0.00% | 27 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement::total 27 +system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total 3 -system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock::total 2 -system.ruby.L1Cache_Controller.OM.Request_Timeout | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.OM.Request_Timeout::total 2 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 527596 12.50% 12.50% | 534359 12.66% 25.17% | 527205 12.49% 37.66% | 528297 12.52% 50.18% | 528825 12.53% 62.71% | 521299 12.35% 75.07% | 526429 12.48% 87.54% | 525605 12.46% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4219615 -system.ruby.L1Cache_Controller.IS.Data_Shared | 181 12.75% 12.75% | 177 12.46% 25.21% | 176 12.39% 37.61% | 159 11.20% 48.80% | 181 12.75% 61.55% | 182 12.82% 74.37% | 182 12.82% 87.18% | 182 12.82% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Shared::total 1420 -system.ruby.L1Cache_Controller.IS.Data_Owner | 22 11.52% 11.52% | 27 14.14% 25.65% | 18 9.42% 35.08% | 26 13.61% 48.69% | 24 12.57% 61.26% | 26 13.61% 74.87% | 22 11.52% 86.39% | 26 13.61% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Owner::total 191 -system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 49867 12.44% 12.44% | 50496 12.60% 25.04% | 50150 12.51% 37.55% | 50036 12.48% 50.04% | 50320 12.56% 62.59% | 49785 12.42% 75.02% | 50124 12.51% 87.52% | 50011 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 400789 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 152 11.69% 11.69% | 159 12.23% 23.92% | 175 13.46% 37.38% | 167 12.85% 50.23% | 173 13.31% 63.54% | 154 11.85% 75.38% | 145 11.15% 86.54% | 175 13.46% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1300 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 325 12.87% 12.87% | 314 12.44% 25.31% | 332 13.15% 38.46% | 302 11.96% 50.42% | 305 12.08% 62.50% | 312 12.36% 74.85% | 322 12.75% 87.60% | 313 12.40% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2525 -system.ruby.L1Cache_Controller.IS.Persistent_GETX | 14 12.17% 12.17% | 10 8.70% 20.87% | 18 15.65% 36.52% | 14 12.17% 48.70% | 17 14.78% 63.48% | 12 10.43% 73.91% | 19 16.52% 90.43% | 11 9.57% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 115 -system.ruby.L1Cache_Controller.IS.Persistent_GETS | 28 11.72% 11.72% | 23 9.62% 21.34% | 32 13.39% 34.73% | 25 10.46% 45.19% | 35 14.64% 59.83% | 32 13.39% 73.22% | 39 16.32% 89.54% | 25 10.46% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 239 -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 3103 12.48% 12.48% | 3161 12.72% 25.20% | 3104 12.49% 37.69% | 3090 12.43% 50.12% | 3120 12.55% 62.67% | 3099 12.47% 75.14% | 3066 12.34% 87.48% | 3113 12.52% 100.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 24856 -system.ruby.L1Cache_Controller.IS.Request_Timeout | 21020 12.47% 12.47% | 21488 12.74% 25.21% | 21067 12.49% 37.70% | 21326 12.65% 50.35% | 20944 12.42% 62.77% | 20610 12.22% 74.99% | 20711 12.28% 87.27% | 21463 12.73% 100.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout::total 168629 -system.ruby.L1Cache_Controller.I_L.Load | 18 10.06% 10.06% | 16 8.94% 18.99% | 29 16.20% 35.20% | 27 15.08% 50.28% | 27 15.08% 65.36% | 11 6.15% 71.51% | 26 14.53% 86.03% | 25 13.97% 100.00% -system.ruby.L1Cache_Controller.I_L.Load::total 179 -system.ruby.L1Cache_Controller.I_L.Store | 9 9.68% 9.68% | 18 19.35% 29.03% | 14 15.05% 44.09% | 10 10.75% 54.84% | 10 10.75% 65.59% | 13 13.98% 79.57% | 9 9.68% 89.25% | 10 10.75% 100.00% -system.ruby.L1Cache_Controller.I_L.Store::total 93 -system.ruby.L1Cache_Controller.I_L.L1_Replacement | 125 9.36% 9.36% | 83 6.21% 15.57% | 178 13.32% 28.89% | 173 12.95% 41.84% | 239 17.89% 59.73% | 184 13.77% 73.50% | 192 14.37% 87.87% | 162 12.13% 100.00% -system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1336 -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 27 21.26% 21.26% | 18 14.17% 35.43% | 29 22.83% 58.27% | 16 12.60% 70.87% | 17 13.39% 84.25% | 7 5.51% 89.76% | 7 5.51% 95.28% | 6 4.72% 100.00% -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 127 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 69 11.94% 11.94% | 69 11.94% 23.88% | 63 10.90% 34.78% | 75 12.98% 47.75% | 76 13.15% 60.90% | 71 12.28% 73.18% | 78 13.49% 86.68% | 77 13.32% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 578 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 132 12.88% 12.88% | 128 12.49% 25.37% | 121 11.80% 37.17% | 125 12.20% 49.37% | 127 12.39% 61.76% | 134 13.07% 74.83% | 137 13.37% 88.20% | 121 11.80% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 1025 -system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 13578 12.51% 12.51% | 13598 12.53% 25.04% | 13560 12.49% 37.53% | 13520 12.46% 49.98% | 13540 12.47% 62.46% | 13571 12.50% 74.96% | 13635 12.56% 87.52% | 13544 12.48% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 108546 -system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 24905 12.51% 12.51% | 24862 12.48% 24.99% | 24875 12.49% 37.48% | 24914 12.51% 49.99% | 24915 12.51% 62.50% | 24926 12.52% 75.02% | 24887 12.50% 87.52% | 24855 12.48% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 199139 -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 25 8.53% 8.53% | 34 11.60% 20.14% | 35 11.95% 32.08% | 35 11.95% 44.03% | 46 15.70% 59.73% | 46 15.70% 75.43% | 32 10.92% 86.35% | 40 13.65% 100.00% -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 293 -system.ruby.L1Cache_Controller.S_L.L1_Replacement | 46 14.37% 14.37% | 31 9.69% 24.06% | 38 11.88% 35.94% | 8 2.50% 38.44% | 52 16.25% 54.69% | 22 6.88% 61.56% | 48 15.00% 76.56% | 75 23.44% 100.00% -system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 320 -system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 1 3.23% 3.23% | 3 9.68% 12.90% | 4 12.90% 25.81% | 7 22.58% 48.39% | 3 9.68% 58.06% | 7 22.58% 80.65% | 6 19.35% 100.00% -system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 31 -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 23 12.23% 12.23% | 15 7.98% 20.21% | 27 14.36% 34.57% | 24 12.77% 47.34% | 25 13.30% 60.64% | 26 13.83% 74.47% | 24 12.77% 87.23% | 24 12.77% 100.00% -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 188 -system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 143 9.18% 9.18% | 175 11.23% 20.41% | 168 10.78% 31.19% | 236 15.15% 46.34% | 181 11.62% 57.96% | 285 18.29% 76.25% | 169 10.85% 87.10% | 201 12.90% 100.00% -system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 1558 -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 5 -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX::total 2 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 1 10.00% 10.00% | 1 10.00% 20.00% | 2 20.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 10 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 16.13% 16.13% | 1 3.23% 19.35% | 4 12.90% 32.26% | 2 6.45% 38.71% | 8 25.81% 64.52% | 11 35.48% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 31 -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 28 10.18% 10.18% | 38 13.82% 24.00% | 38 13.82% 37.82% | 31 11.27% 49.09% | 35 12.73% 61.82% | 41 14.91% 76.73% | 31 11.27% 88.00% | 33 12.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 275 -system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 22 5.98% 5.98% | 62 16.85% 22.83% | 33 8.97% 31.79% | 61 16.58% 48.37% | 42 11.41% 59.78% | 13 3.53% 63.32% | 89 24.18% 87.50% | 46 12.50% 100.00% -system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 368 -system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 404 13.20% 13.20% | 259 8.46% 21.67% | 472 15.42% 37.09% | 362 11.83% 48.92% | 384 12.55% 61.47% | 320 10.46% 71.93% | 506 16.54% 88.46% | 353 11.54% 100.00% -system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 3060 -system.ruby.L1Cache_Controller.IS_L.Data_Shared | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 4 -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 0 0.00% 0.00% | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 1 12.50% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 2 25.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 8 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 14.81% 14.81% | 3 11.11% 25.93% | 6 22.22% 48.15% | 2 7.41% 55.56% | 6 22.22% 77.78% | 6 22.22% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 27 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 1 1.89% 1.89% | 2 3.77% 5.66% | 5 9.43% 15.09% | 10 18.87% 33.96% | 8 15.09% 49.06% | 14 26.42% 75.47% | 13 24.53% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 53 -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 59 11.32% 11.32% | 48 9.21% 20.54% | 78 14.97% 35.51% | 62 11.90% 47.41% | 78 14.97% 62.38% | 55 10.56% 72.94% | 83 15.93% 88.87% | 58 11.13% 100.00% -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 521 -system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 186 23.05% 23.05% | 67 8.30% 31.35% | 121 14.99% 46.34% | 77 9.54% 55.89% | 90 11.15% 67.04% | 70 8.67% 75.71% | 143 17.72% 93.43% | 53 6.57% 100.00% -system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 807 -system.ruby.L2Cache_Controller.L1_GETS 402399 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS_Last_Token 20 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 223106 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_INV 683 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 598575 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Shared_Data 975 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 623413 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Owned 430 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETX 15565 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 28553 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token 4 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 43680 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 401075 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 222380 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_INV 492 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 901 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 597337 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Owned 345 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 36371 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETS 61 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETX 35 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_INV 3 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 7485 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 2 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 457 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Owned 8 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Persistent_GETX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Persistent_GETS 15 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 20 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 848 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 6 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 42 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Owned 2 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETS 1 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement | 531190 12.53% 12.53% | 530879 12.52% 25.06% | 530459 12.51% 37.57% | 529762 12.50% 50.07% | 530166 12.51% 62.58% | 531419 12.54% 75.12% | 528660 12.47% 87.59% | 526084 12.41% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4238619 +system.ruby.L1Cache_Controller.IS.Data_Shared | 183 13.01% 13.01% | 167 11.87% 24.88% | 156 11.09% 35.96% | 180 12.79% 48.76% | 187 13.29% 62.05% | 181 12.86% 74.91% | 167 11.87% 86.78% | 186 13.22% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Shared::total 1407 +system.ruby.L1Cache_Controller.IS.Data_Owner | 22 11.17% 11.17% | 19 9.64% 20.81% | 22 11.17% 31.98% | 24 12.18% 44.16% | 28 14.21% 58.38% | 28 14.21% 72.59% | 27 13.71% 86.29% | 27 13.71% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Owner::total 197 +system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50456 12.59% 12.59% | 50172 12.52% 25.11% | 50143 12.51% 37.62% | 50046 12.49% 50.10% | 50272 12.54% 62.64% | 49986 12.47% 75.12% | 49929 12.46% 87.57% | 49812 12.43% 100.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 400816 +system.ruby.L1Cache_Controller.IS.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS.Ack::total 2 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 185 13.17% 13.17% | 180 12.81% 25.98% | 163 11.60% 37.58% | 170 12.10% 49.68% | 176 12.53% 62.21% | 180 12.81% 75.02% | 173 12.31% 87.33% | 178 12.67% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1405 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 290 12.06% 12.06% | 311 12.94% 25.00% | 311 12.94% 37.94% | 331 13.77% 51.71% | 291 12.10% 63.81% | 280 11.65% 75.46% | 262 10.90% 86.36% | 328 13.64% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2404 +system.ruby.L1Cache_Controller.IS.Persistent_GETX | 17 18.48% 18.48% | 10 10.87% 29.35% | 12 13.04% 42.39% | 8 8.70% 51.09% | 10 10.87% 61.96% | 16 17.39% 79.35% | 7 7.61% 86.96% | 12 13.04% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 92 +system.ruby.L1Cache_Controller.IS.Persistent_GETS | 14 8.09% 8.09% | 17 9.83% 17.92% | 21 12.14% 30.06% | 22 12.72% 42.77% | 16 9.25% 52.02% | 32 18.50% 70.52% | 25 14.45% 84.97% | 26 15.03% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 173 +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 2575 12.30% 12.30% | 2712 12.95% 25.25% | 2643 12.62% 37.87% | 2601 12.42% 50.29% | 2597 12.40% 62.69% | 2587 12.35% 75.05% | 2648 12.65% 87.69% | 2577 12.31% 100.00% +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 20940 +system.ruby.L1Cache_Controller.IS.Request_Timeout | 21384 12.87% 12.87% | 21323 12.83% 25.70% | 20616 12.41% 38.11% | 20325 12.23% 50.34% | 20632 12.42% 62.75% | 21552 12.97% 75.72% | 20368 12.26% 87.98% | 19971 12.02% 100.00% +system.ruby.L1Cache_Controller.IS.Request_Timeout::total 166171 +system.ruby.L1Cache_Controller.I_L.Load | 21 14.00% 14.00% | 16 10.67% 24.67% | 15 10.00% 34.67% | 18 12.00% 46.67% | 23 15.33% 62.00% | 19 12.67% 74.67% | 23 15.33% 90.00% | 15 10.00% 100.00% +system.ruby.L1Cache_Controller.I_L.Load::total 150 +system.ruby.L1Cache_Controller.I_L.Store | 8 10.96% 10.96% | 9 12.33% 23.29% | 4 5.48% 28.77% | 11 15.07% 43.84% | 9 12.33% 56.16% | 11 15.07% 71.23% | 8 10.96% 82.19% | 13 17.81% 100.00% +system.ruby.L1Cache_Controller.I_L.Store::total 73 +system.ruby.L1Cache_Controller.I_L.L1_Replacement | 86 6.80% 6.80% | 120 9.49% 16.30% | 129 10.21% 26.50% | 242 19.15% 45.65% | 166 13.13% 58.78% | 201 15.90% 74.68% | 183 14.48% 89.16% | 137 10.84% 100.00% +system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1264 +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 18 20.93% 20.93% | 19 22.09% 43.02% | 12 13.95% 56.98% | 12 13.95% 70.93% | 10 11.63% 82.56% | 5 5.81% 88.37% | 8 9.30% 97.67% | 2 2.33% 100.00% +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 86 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 61 12.90% 12.90% | 57 12.05% 24.95% | 63 13.32% 38.27% | 60 12.68% 50.95% | 58 12.26% 63.21% | 58 12.26% 75.48% | 60 12.68% 88.16% | 56 11.84% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 473 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 105 11.74% 11.74% | 117 13.09% 24.83% | 119 13.31% 38.14% | 115 12.86% 51.01% | 103 11.52% 62.53% | 115 12.86% 75.39% | 108 12.08% 87.47% | 112 12.53% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 894 +system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 11816 12.43% 12.43% | 11806 12.42% 24.85% | 11913 12.53% 37.39% | 11963 12.59% 49.97% | 11904 12.52% 62.50% | 11820 12.44% 74.93% | 11909 12.53% 87.46% | 11915 12.54% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 95046 +system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 21311 12.52% 12.52% | 21181 12.44% 24.97% | 21223 12.47% 37.44% | 21295 12.51% 49.95% | 21275 12.50% 62.45% | 21312 12.52% 74.97% | 21292 12.51% 87.48% | 21308 12.52% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 170197 +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 32 12.03% 12.03% | 28 10.53% 22.56% | 38 14.29% 36.84% | 34 12.78% 49.62% | 33 12.41% 62.03% | 36 13.53% 75.56% | 35 13.16% 88.72% | 30 11.28% 100.00% +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 266 +system.ruby.L1Cache_Controller.S_L.L1_Replacement | 49 12.89% 12.89% | 40 10.53% 23.42% | 38 10.00% 33.42% | 25 6.58% 40.00% | 47 12.37% 52.37% | 7 1.84% 54.21% | 60 15.79% 70.00% | 114 30.00% 100.00% +system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 380 +system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 7.69% 7.69% | 3 23.08% 30.77% | 1 7.69% 38.46% | 2 15.38% 53.85% | 3 23.08% 76.92% | 3 23.08% 100.00% +system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 13 +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 28 14.29% 14.29% | 25 12.76% 27.04% | 25 12.76% 39.80% | 31 15.82% 55.61% | 20 10.20% 65.82% | 18 9.18% 75.00% | 21 10.71% 85.71% | 28 14.29% 100.00% +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 196 +system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 100 8.63% 8.63% | 166 14.32% 22.95% | 84 7.25% 30.20% | 99 8.54% 38.74% | 192 16.57% 55.31% | 157 13.55% 68.85% | 183 15.79% 84.64% | 178 15.36% 100.00% +system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 1159 +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 4 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 42.86% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 3 42.86% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 7 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 1 4.76% 4.76% | 0 0.00% 4.76% | 1 4.76% 9.52% | 6 28.57% 38.10% | 2 9.52% 47.62% | 7 33.33% 80.95% | 4 19.05% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 21 +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 28 11.62% 11.62% | 32 13.28% 24.90% | 21 8.71% 33.61% | 29 12.03% 45.64% | 35 14.52% 60.17% | 24 9.96% 70.12% | 32 13.28% 83.40% | 40 16.60% 100.00% +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 241 +system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 16 3.53% 3.53% | 99 21.85% 25.39% | 40 8.83% 34.22% | 55 12.14% 46.36% | 54 11.92% 58.28% | 15 3.31% 61.59% | 83 18.32% 79.91% | 91 20.09% 100.00% +system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 453 +system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 250 10.84% 10.84% | 201 8.71% 19.55% | 329 14.26% 33.81% | 264 11.44% 45.25% | 307 13.31% 58.56% | 417 18.08% 76.64% | 199 8.63% 85.26% | 340 14.74% 100.00% +system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 2307 +system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 3 +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 3 +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total 2 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 2 10.53% 10.53% | 2 10.53% 21.05% | 2 10.53% 31.58% | 2 10.53% 42.11% | 4 21.05% 63.16% | 2 10.53% 73.68% | 5 26.32% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 19 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 7.14% 7.14% | 7 16.67% 23.81% | 7 16.67% 40.48% | 10 23.81% 64.29% | 5 11.90% 76.19% | 10 23.81% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 42 +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 52 12.71% 12.71% | 42 10.27% 22.98% | 48 11.74% 34.72% | 47 11.49% 46.21% | 49 11.98% 58.19% | 64 15.65% 73.84% | 54 13.20% 87.04% | 53 12.96% 100.00% +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 409 +system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 49 6.98% 6.98% | 87 12.39% 19.37% | 48 6.84% 26.21% | 45 6.41% 32.62% | 38 5.41% 38.03% | 135 19.23% 57.26% | 128 18.23% 75.50% | 172 24.50% 100.00% +system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 702 +system.ruby.L2Cache_Controller.L1_GETS 402424 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS_Last_Token 15 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 224067 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_INV 651 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 603716 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Shared_Data 977 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_All_Tokens 624428 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Owned 419 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETX 13627 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS 24405 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token 2 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 37727 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 401143 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 223340 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_INV 458 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 915 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 602465 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Owned 344 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 32152 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETS 44 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETX 26 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_INV 1 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L2_Replacement 5743 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 453 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_Owned 2 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETX 12 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETS 17 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 15 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 857 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 4 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 57 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Owned 4 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Persistent_GETS 3 0.00% 0.00% system.ruby.L2Cache_Controller.S.Persistent_GETS_Last_Token 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETS 20 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 895 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETS 24 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L2_Replacement 866 0.00% 0.00% system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 3 0.00% 0.00% system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 613 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETS 13 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1170 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 655 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 588544 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETX 2903 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETS 5169 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETS 73 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETX 33 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_INV 188 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L2_Replacement 800 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 62 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 24964 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Owned 75 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 12653 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 23355 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 7296 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.L2_Replacement 3 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Writeback_Shared_Data 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Persistent_GETS_Last_Token 2 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 13 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Persistent_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Persistent_GETS 18 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1151 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 659 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 595469 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETX 2203 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETS 4098 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETS 62 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETX 41 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_INV 191 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L2_Replacement 781 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 55 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 20840 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Owned 69 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETX 11409 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETS 20269 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 5552 0.00% 0.00% +system.ruby.L2Cache_Controller.S_L.L1_INV 1 0.00% 0.00% +system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 23 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index f78dc39b7..299a78275 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.004710 # Number of seconds simulated -sim_ticks 4710288 # Number of ticks simulated -final_tick 4710288 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.004733 # Number of seconds simulated +sim_ticks 4733400 # Number of ticks simulated +final_tick 4733400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 49486 # Simulator tick rate (ticks/s) -host_mem_usage 481348 # Number of bytes of host memory used -host_seconds 95.18 # Real time elapsed on the host +host_tick_rate 45459 # Simulator tick rate (ticks/s) +host_mem_usage 533892 # Number of bytes of host memory used +host_seconds 104.13 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38770176 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 38770176 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14150080 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14150080 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 605784 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 605784 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 221095 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 221095 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 8230956578 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 8230956578 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 3004079581 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 3004079581 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 11235036159 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 11235036159 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 605795 # Number of read requests accepted -system.mem_ctrls.writeReqs 221095 # Number of write requests accepted -system.mem_ctrls.readBursts 605795 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 221095 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 37774848 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 995776 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 13961856 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 38770880 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14150080 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 15559 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 2886 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39017600 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39017600 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14216768 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14216768 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 609650 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 609650 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 222137 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 222137 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 8243038830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 8243038830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 3003500232 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 3003500232 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 11246539063 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 11246539063 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 609676 # Number of read requests accepted +system.mem_ctrls.writeReqs 222137 # Number of write requests accepted +system.mem_ctrls.readBursts 609676 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 222137 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38007168 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 1010496 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14020224 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39019264 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14216768 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 15789 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 3025 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 74027 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 73691 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 74048 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 73659 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 73761 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 73677 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 73634 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 73735 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 74231 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 74363 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 73892 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 74507 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 74187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 73965 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 74227 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 74490 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27260 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27309 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27417 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27165 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27317 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27153 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27104 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27429 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27470 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27400 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27273 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27416 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27333 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27456 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27361 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27357 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,54 +68,54 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 409 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 4710276 # Total gap between requests +system.mem_ctrls.numWrRetry 314 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 4733386 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 605795 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 609676 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 221095 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 191 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 460 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 934 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 1567 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 2278 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 3218 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 4416 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 5814 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 7450 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 9494 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 12542 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 17459 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 24829 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 35282 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 47987 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 59847 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 67739 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 68317 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 61075 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 48105 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 34077 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 22801 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 15601 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 11679 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 9169 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 6988 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 4984 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 3131 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 1722 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 781 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 262 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 37 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 222137 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 153 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 427 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 792 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1352 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 2079 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3064 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 4054 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 5356 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 6864 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 8709 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 11287 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 15494 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 22545 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 32679 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 46246 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 60217 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 70227 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 72202 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 64822 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 51161 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 35852 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 23634 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 16041 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 11999 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 9304 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 7005 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 4851 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 2978 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 1553 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 670 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 234 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 36 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -137,1366 +137,1371 @@ system.mem_ctrls.wrQLenPdf::17 1 # Wh system.mem_ctrls.wrQLenPdf::18 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 11 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 20 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 29 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 68 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 74 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 134 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 217 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 283 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 350 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 534 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 693 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 1556 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 3238 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 5631 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 8129 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 10368 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 12019 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 13539 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 14215 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 14950 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 15548 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 16303 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 16948 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 16348 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 15770 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 15893 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 16867 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 10738 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 3547 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 1132 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 718 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 521 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 376 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 342 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 281 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 722 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 217263 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 238.124375 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 188.064482 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 172.867949 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 37866 17.43% 17.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 92203 42.44% 59.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44887 20.66% 80.53% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 21105 9.71% 90.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10935 5.03% 95.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5805 2.67% 97.95% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2648 1.22% 99.17% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1064 0.49% 99.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 750 0.35% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 217263 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13625 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 43.319780 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 31.150642 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 26.199447 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 1380 10.13% 10.13% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 1829 13.42% 23.55% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 675 4.95% 28.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 992 7.28% 35.79% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 1096 8.04% 43.83% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 1136 8.34% 52.17% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 1294 9.50% 61.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 1412 10.36% 72.03% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 1517 11.13% 83.16% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 1303 9.56% 92.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 700 5.14% 97.86% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 229 1.68% 99.54% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 55 0.40% 99.95% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::104-111 6 0.04% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::248-255 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13625 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13624 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.012405 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.010105 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.322047 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13591 99.76% 99.76% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 6 0.04% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 7 0.05% 99.85% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 0.02% 99.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 1 0.01% 99.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 4 0.03% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 1 0.01% 99.92% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 3 0.02% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 1 0.01% 99.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 3 0.02% 99.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 1 0.01% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 2 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13624 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 73947917 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 85162325 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 2951160 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 125.29 # Average queueing delay per DRAM burst +system.mem_ctrls.wrQLenPdf::21 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 26 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 34 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 78 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 123 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 333 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 413 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 587 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 1402 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 3145 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 5659 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 8204 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 10599 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 12359 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 13826 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 14746 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 15249 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 15665 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 16347 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 17294 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 16657 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 15930 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 15968 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 16886 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 10292 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 3285 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 1017 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 646 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 453 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 337 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 286 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 263 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 592 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 220003 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 236.476194 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 186.977193 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 171.485363 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 38448 17.48% 17.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 94335 42.88% 60.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45147 20.52% 80.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 20844 9.47% 90.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 11176 5.08% 95.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 5677 2.58% 98.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 2632 1.20% 99.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1100 0.50% 99.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 644 0.29% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 220003 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13685 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 43.395031 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 31.687462 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 25.881507 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 1275 9.32% 9.32% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 1849 13.51% 22.83% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 705 5.15% 27.98% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 1036 7.57% 35.55% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 1094 7.99% 43.54% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 1201 8.78% 52.32% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 1379 10.08% 62.40% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 1411 10.31% 72.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 1476 10.79% 83.49% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 1271 9.29% 92.78% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 698 5.10% 97.88% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 219 1.60% 99.48% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-103 51 0.37% 99.85% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::104-111 18 0.13% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::216-223 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 13685 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13685 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.007746 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.006574 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.222457 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13658 99.80% 99.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 7 0.05% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 5 0.04% 99.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 5 0.04% 99.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 0.01% 99.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.01% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 3 0.02% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 1 0.01% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13685 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 74960248 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 86243626 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 2969310 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 126.22 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 144.29 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 8019.65 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 2964.12 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 8231.11 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 3004.08 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 145.22 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 8029.57 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 2961.98 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 8243.39 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 3003.50 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 85.81 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 62.65 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 23.16 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 19.64 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 50.37 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 379240 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 211876 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 64.25 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.10 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 5.70 # Average gap between requests -system.mem_ctrls.pageHitRate 73.12 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1639862280 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 911034600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7354464000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2258160768 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 307170240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 3205313604 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10145400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 15686150892 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 3335.321599 # Core power per rank (mW) +system.mem_ctrls.busUtil 85.87 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 62.73 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 23.14 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 19.75 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 50.40 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 379960 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 212957 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 63.98 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.19 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 5.69 # Average gap between requests +system.mem_ctrls.pageHitRate 72.93 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1660614480 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 922563600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7399816320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2267792640 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 308695920 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3221230284 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10195800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 15790909044 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 3341.005647 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 157040 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 157820 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 4546003 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4568577 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 307170240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 101631456 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 2732643600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3141445296 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.967675 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 4545964 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 157040 # Time in different power states +system.mem_ctrls_1.refreshEnergy 308695920 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 102136248 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2746215600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3157047768 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.967693 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 4568542 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 157820 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 98805 # number of read accesses completed -system.cpu0.num_writes 55123 # number of write accesses completed -system.cpu1.num_reads 98745 # number of read accesses completed -system.cpu1.num_writes 55054 # number of write accesses completed -system.cpu2.num_reads 99065 # number of read accesses completed -system.cpu2.num_writes 56148 # number of write accesses completed -system.cpu3.num_reads 99193 # number of read accesses completed -system.cpu3.num_writes 54886 # number of write accesses completed -system.cpu4.num_reads 98751 # number of read accesses completed -system.cpu4.num_writes 55749 # number of write accesses completed -system.cpu5.num_reads 98704 # number of read accesses completed -system.cpu5.num_writes 55417 # number of write accesses completed -system.cpu6.num_reads 99258 # number of read accesses completed -system.cpu6.num_writes 55160 # number of write accesses completed -system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 55957 # number of write accesses completed +system.cpu0.num_reads 99240 # number of read accesses completed +system.cpu0.num_writes 55703 # number of write accesses completed +system.cpu1.num_reads 99630 # number of read accesses completed +system.cpu1.num_writes 55894 # number of write accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 55558 # number of write accesses completed +system.cpu3.num_reads 99663 # number of read accesses completed +system.cpu3.num_writes 55627 # number of write accesses completed +system.cpu4.num_reads 99301 # number of read accesses completed +system.cpu4.num_writes 55122 # number of write accesses completed +system.cpu5.num_reads 99744 # number of read accesses completed +system.cpu5.num_writes 55403 # number of write accesses completed +system.cpu6.num_reads 99405 # number of read accesses completed +system.cpu6.num_writes 55787 # number of write accesses completed +system.cpu7.num_reads 99787 # number of read accesses completed +system.cpu7.num_writes 56016 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 626839 -system.ruby.outstanding_req_hist::mean 15.998453 -system.ruby.outstanding_req_hist::gmean 15.997188 -system.ruby.outstanding_req_hist::stdev 0.125853 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 26 0.00% 0.02% | 626709 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 626839 +system.ruby.outstanding_req_hist::samples 630953 +system.ruby.outstanding_req_hist::mean 15.998455 +system.ruby.outstanding_req_hist::gmean 15.997199 +system.ruby.outstanding_req_hist::stdev 0.125474 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 630818 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 630953 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 626711 -system.ruby.latency_hist::mean 961.893678 -system.ruby.latency_hist::gmean 687.559253 -system.ruby.latency_hist::stdev 669.975884 -system.ruby.latency_hist | 233282 37.22% 37.22% | 116315 18.56% 55.78% | 118100 18.84% 74.63% | 122318 19.52% 94.14% | 34176 5.45% 99.60% | 2441 0.39% 99.99% | 77 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 626711 +system.ruby.latency_hist::samples 630825 +system.ruby.latency_hist::mean 960.308815 +system.ruby.latency_hist::gmean 687.329820 +system.ruby.latency_hist::stdev 668.477616 +system.ruby.latency_hist | 236510 37.49% 37.49% | 115846 18.36% 55.86% | 117532 18.63% 74.49% | 125080 19.83% 94.32% | 33628 5.33% 99.65% | 2176 0.34% 99.99% | 53 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 630825 system.ruby.hit_latency_hist::bucket_size 256 system.ruby.hit_latency_hist::max_bucket 2559 -system.ruby.hit_latency_hist::samples 687 -system.ruby.hit_latency_hist::mean 97.013100 -system.ruby.hit_latency_hist::gmean 31.183687 -system.ruby.hit_latency_hist::stdev 145.506218 -system.ruby.hit_latency_hist | 624 90.83% 90.83% | 49 7.13% 97.96% | 10 1.46% 99.42% | 1 0.15% 99.56% | 2 0.29% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 687 +system.ruby.hit_latency_hist::samples 703 +system.ruby.hit_latency_hist::mean 107.428165 +system.ruby.hit_latency_hist::gmean 37.578183 +system.ruby.hit_latency_hist::stdev 143.869758 +system.ruby.hit_latency_hist | 636 90.47% 90.47% | 48 6.83% 97.30% | 15 2.13% 99.43% | 2 0.28% 99.72% | 0 0.00% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 703 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 626024 -system.ruby.miss_latency_hist::mean 962.842800 -system.ruby.miss_latency_hist::gmean 689.897168 -system.ruby.miss_latency_hist::stdev 669.712845 -system.ruby.miss_latency_hist | 232609 37.16% 37.16% | 116304 18.58% 55.73% | 118098 18.86% 74.60% | 122317 19.54% 94.14% | 34176 5.46% 99.60% | 2441 0.39% 99.99% | 77 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626024 -system.ruby.L1Cache.incomplete_times 1059 -system.ruby.Directory.incomplete_times 174559 +system.ruby.miss_latency_hist::samples 630122 +system.ruby.miss_latency_hist::mean 961.260337 +system.ruby.miss_latency_hist::gmean 689.562128 +system.ruby.miss_latency_hist::stdev 668.225537 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78671 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 72 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 78269 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 78341 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Dcache.demand_hits 26 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78152 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78178 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 56 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 78599 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 78655 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 28 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78868 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78896 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl1.L2cache.demand_hits 62 # Number of cache demand hits -system.ruby.l1_cntrl1.L2cache.demand_misses 78090 # Number of cache demand misses -system.ruby.l1_cntrl1.L2cache.demand_accesses 78152 # Number of cache demand accesses -system.ruby.l1_cntrl2.L1Dcache.demand_hits 21 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78522 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78543 # Number of cache demand accesses +system.ruby.l1_cntrl1.L2cache.demand_misses 78806 # Number of cache demand misses +system.ruby.l1_cntrl1.L2cache.demand_accesses 78868 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78934 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78953 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L2cache.demand_hits 57 # Number of cache demand hits -system.ruby.l1_cntrl2.L2cache.demand_misses 78465 # Number of cache demand misses -system.ruby.l1_cntrl2.L2cache.demand_accesses 78522 # Number of cache demand accesses -system.ruby.l1_cntrl3.L1Dcache.demand_hits 14 # Number of cache demand hits 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system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.L2cache.demand_hits 61 # Number of cache demand hits -system.ruby.l1_cntrl4.L2cache.demand_misses 78407 # Number of cache demand misses -system.ruby.l1_cntrl4.L2cache.demand_accesses 78468 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Dcache.demand_hits 25 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78409 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78434 # Number of cache demand accesses +system.ruby.l1_cntrl4.L2cache.demand_hits 67 # Number of cache demand hits +system.ruby.l1_cntrl4.L2cache.demand_misses 78938 # Number of cache demand misses +system.ruby.l1_cntrl4.L2cache.demand_accesses 79005 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 20 # Number of cache demand hits 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624664 -system.ruby.network.routers4.percent_links_utilized 15.743220 -system.ruby.network.routers4.msg_count.Request_Control::2 78407 -system.ruby.network.routers4.msg_count.Request_Control::3 142 -system.ruby.network.routers4.msg_count.Response_Data::4 80934 -system.ruby.network.routers4.msg_count.Response_Control::4 1089785 -system.ruby.network.routers4.msg_count.Writeback_Data::5 27788 -system.ruby.network.routers4.msg_count.Writeback_Control::2 74021 -system.ruby.network.routers4.msg_count.Writeback_Control::3 74018 -system.ruby.network.routers4.msg_count.Writeback_Control::5 46049 -system.ruby.network.routers4.msg_count.Broadcast_Control::3 546700 -system.ruby.network.routers4.msg_count.Unblock_Control::5 78584 -system.ruby.network.routers4.msg_bytes.Request_Control::2 627256 -system.ruby.network.routers4.msg_bytes.Request_Control::3 1136 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5827248 -system.ruby.network.routers4.msg_bytes.Response_Control::4 8718280 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-system.ruby.network.routers6.msg_count.Response_Data::4 80574 -system.ruby.network.routers6.msg_count.Response_Control::4 1087587 -system.ruby.network.routers6.msg_count.Writeback_Data::5 27513 -system.ruby.network.routers6.msg_count.Writeback_Control::2 73565 -system.ruby.network.routers6.msg_count.Writeback_Control::3 73562 -system.ruby.network.routers6.msg_count.Writeback_Control::5 45870 -system.ruby.network.routers6.msg_count.Broadcast_Control::3 547058 -system.ruby.network.routers6.msg_count.Unblock_Control::5 78212 -system.ruby.network.routers6.msg_bytes.Request_Control::2 624296 -system.ruby.network.routers6.msg_bytes.Request_Control::3 1048 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5801328 -system.ruby.network.routers6.msg_bytes.Response_Control::4 8700696 -system.ruby.network.routers6.msg_bytes.Writeback_Data::5 1980936 -system.ruby.network.routers6.msg_bytes.Writeback_Control::2 588520 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 588496 -system.ruby.network.routers6.msg_bytes.Writeback_Control::5 366960 -system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4376464 -system.ruby.network.routers6.msg_bytes.Unblock_Control::5 625696 -system.ruby.network.routers7.percent_links_utilized 15.751256 -system.ruby.network.routers7.msg_count.Request_Control::2 78539 -system.ruby.network.routers7.msg_count.Request_Control::3 141 -system.ruby.network.routers7.msg_count.Response_Data::4 81044 -system.ruby.network.routers7.msg_count.Response_Control::4 1090607 -system.ruby.network.routers7.msg_count.Writeback_Data::5 27694 -system.ruby.network.routers7.msg_count.Writeback_Control::2 74130 -system.ruby.network.routers7.msg_count.Writeback_Control::3 74128 -system.ruby.network.routers7.msg_count.Writeback_Control::5 46215 -system.ruby.network.routers7.msg_count.Broadcast_Control::3 546562 -system.ruby.network.routers7.msg_count.Unblock_Control::5 78755 -system.ruby.network.routers7.msg_bytes.Request_Control::2 628312 -system.ruby.network.routers7.msg_bytes.Request_Control::3 1128 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5835168 -system.ruby.network.routers7.msg_bytes.Response_Control::4 8724856 -system.ruby.network.routers7.msg_bytes.Writeback_Data::5 1993968 -system.ruby.network.routers7.msg_bytes.Writeback_Control::2 593040 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 593024 -system.ruby.network.routers7.msg_bytes.Writeback_Control::5 369720 -system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4372496 -system.ruby.network.routers7.msg_bytes.Unblock_Control::5 630040 -system.ruby.network.routers8.percent_links_utilized 57.696143 -system.ruby.network.routers8.msg_count.Request_Control::2 626043 -system.ruby.network.routers8.msg_count.Request_Control::3 1058 -system.ruby.network.routers8.msg_count.Response_Data::4 605779 -system.ruby.network.routers8.msg_count.Writeback_Data::5 221095 -system.ruby.network.routers8.msg_count.Writeback_Control::2 590607 -system.ruby.network.routers8.msg_count.Writeback_Control::3 590583 -system.ruby.network.routers8.msg_count.Writeback_Control::5 367967 -system.ruby.network.routers8.msg_count.Broadcast_Control::3 624964 -system.ruby.network.routers8.msg_count.Unblock_Control::5 627535 -system.ruby.network.routers8.msg_bytes.Request_Control::2 5008344 -system.ruby.network.routers8.msg_bytes.Request_Control::3 8464 -system.ruby.network.routers8.msg_bytes.Response_Data::4 43616088 -system.ruby.network.routers8.msg_bytes.Writeback_Data::5 15918840 -system.ruby.network.routers8.msg_bytes.Writeback_Control::2 4724856 -system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4724664 -system.ruby.network.routers8.msg_bytes.Writeback_Control::5 2943736 -system.ruby.network.routers8.msg_bytes.Broadcast_Control::3 4999712 -system.ruby.network.routers8.msg_bytes.Unblock_Control::5 5020280 -system.ruby.network.routers9.percent_links_utilized 22.596120 -system.ruby.network.routers9.msg_count.Request_Control::2 626043 -system.ruby.network.routers9.msg_count.Request_Control::3 1058 -system.ruby.network.routers9.msg_count.Response_Data::4 626025 -system.ruby.network.routers9.msg_count.Response_Control::4 4355547 -system.ruby.network.routers9.msg_count.Writeback_Data::5 221095 -system.ruby.network.routers9.msg_count.Writeback_Control::2 590607 -system.ruby.network.routers9.msg_count.Writeback_Control::3 590583 -system.ruby.network.routers9.msg_count.Writeback_Control::5 367968 -system.ruby.network.routers9.msg_count.Broadcast_Control::3 4374748 -system.ruby.network.routers9.msg_count.Unblock_Control::5 627535 -system.ruby.network.routers9.msg_bytes.Request_Control::2 5008344 -system.ruby.network.routers9.msg_bytes.Request_Control::3 8464 -system.ruby.network.routers9.msg_bytes.Response_Data::4 45073800 -system.ruby.network.routers9.msg_bytes.Response_Control::4 34844376 -system.ruby.network.routers9.msg_bytes.Writeback_Data::5 15918840 -system.ruby.network.routers9.msg_bytes.Writeback_Control::2 4724856 -system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4724664 -system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2943744 -system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 34997984 -system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5020280 -system.ruby.network.msg_count.Request_Control 1881305 -system.ruby.network.msg_count.Response_Data 1878073 -system.ruby.network.msg_count.Response_Control 13066641 -system.ruby.network.msg_count.Writeback_Data 663285 -system.ruby.network.msg_count.Writeback_Control 4647473 -system.ruby.network.msg_count.Broadcast_Control 9374453 -system.ruby.network.msg_count.Unblock_Control 1882605 -system.ruby.network.msg_byte.Request_Control 15050440 -system.ruby.network.msg_byte.Response_Data 135221256 -system.ruby.network.msg_byte.Response_Control 104533128 -system.ruby.network.msg_byte.Writeback_Data 47756520 -system.ruby.network.msg_byte.Writeback_Control 37179784 -system.ruby.network.msg_byte.Broadcast_Control 74995624 -system.ruby.network.msg_byte.Unblock_Control 15060840 -system.ruby.network.routers0.throttle0.link_utilization 19.845060 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 139 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78266 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 544412 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 73741 -system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3 546833 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3 1112 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5635152 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 4355296 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 589928 -system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3 4374664 -system.ruby.network.routers0.throttle1.link_utilization 11.596637 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 78269 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 2605 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::4 544366 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 27580 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 73745 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 45977 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 78448 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 626152 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 187560 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::4 4354928 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 1985760 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 589960 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 367816 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 627584 -system.ruby.network.routers1.throttle0.link_utilization 19.818746 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::3 131 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78087 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::4 543391 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 73737 -system.ruby.network.routers1.throttle0.msg_count.Broadcast_Control::3 546998 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::3 1048 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5622264 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::4 4347128 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 589896 -system.ruby.network.routers1.throttle0.msg_bytes.Broadcast_Control::3 4375984 -system.ruby.network.routers1.throttle1.link_utilization 11.582614 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 78090 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 2493 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 544635 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::5 27553 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 73740 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::5 45984 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::5 78286 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 624720 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 179496 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 4357080 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::5 1983816 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 589920 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::5 367872 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::5 626288 -system.ruby.network.routers2.throttle0.link_utilization 19.881343 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::3 122 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78462 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::4 546002 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 74045 -system.ruby.network.routers2.throttle0.msg_count.Broadcast_Control::3 546610 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::3 976 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5649264 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::4 4368016 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 592360 -system.ruby.network.routers2.throttle0.msg_bytes.Broadcast_Control::3 4372880 -system.ruby.network.routers2.throttle1.link_utilization 11.627888 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 78465 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 2534 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::4 544197 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 27924 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 74047 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 45930 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 78653 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 627720 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 182448 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4 4353576 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 2010528 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 592376 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 367440 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 629224 -system.ruby.network.routers3.throttle0.link_utilization 19.784459 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::3 152 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 77890 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 541933 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 73508 -system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3 547207 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3 1216 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5608080 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 4335464 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 588064 -system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3 4377656 -system.ruby.network.routers3.throttle1.link_utilization 11.552659 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::2 77893 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 2562 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::4 544796 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5 27209 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2 73510 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5 46106 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5 78083 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2 623144 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 184464 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4 4358368 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5 1959048 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2 588080 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5 368848 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5 624664 -system.ruby.network.routers4.throttle0.link_utilization 19.871067 -system.ruby.network.routers4.throttle0.msg_count.Request_Control::3 142 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78404 -system.ruby.network.routers4.throttle0.msg_count.Response_Control::4 545473 -system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 74018 -system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3 546700 -system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3 1136 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5645088 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4 4363784 -system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 592144 -system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3 4373600 -system.ruby.network.routers4.throttle1.link_utilization 11.615373 -system.ruby.network.routers4.throttle1.msg_count.Request_Control::2 78407 -system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 2530 -system.ruby.network.routers4.throttle1.msg_count.Response_Control::4 544312 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5 27788 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2 74021 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5 46049 -system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5 78584 -system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2 627256 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 182160 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4 4354496 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5 2000736 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2 592168 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5 368392 -system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5 628672 -system.ruby.network.routers5.throttle0.link_utilization 19.858552 -system.ruby.network.routers5.throttle0.msg_count.Request_Control::3 100 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78343 -system.ruby.network.routers5.throttle0.msg_count.Response_Control::4 544986 -system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 73844 -system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3 546773 -system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3 800 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5640696 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4 4359888 -system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 590752 -system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3 4374184 -system.ruby.network.routers5.throttle1.link_utilization 11.609938 -system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 78345 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 2475 -system.ruby.network.routers5.throttle1.msg_count.Response_Control::4 544397 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5 27834 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2 73849 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5 45837 -system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5 78514 -system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 626760 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 178200 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4 4355176 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5 2004048 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 590792 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 366696 -system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 628112 -system.ruby.network.routers6.throttle0.link_utilization 19.807664 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 131 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78034 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 542939 -system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 73562 -system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 547058 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 1048 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5618448 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4343512 -system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 588496 -system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4376464 -system.ruby.network.routers6.throttle1.link_utilization 11.579005 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 78037 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 2540 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::4 544648 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5 27513 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2 73565 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::5 45870 -system.ruby.network.routers6.throttle1.msg_count.Unblock_Control::5 78212 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 624296 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 182880 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::4 4357184 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Data::5 1980936 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::2 588520 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::5 366960 -system.ruby.network.routers6.throttle1.msg_bytes.Unblock_Control::5 625696 -system.ruby.network.routers7.throttle0.link_utilization 19.893508 -system.ruby.network.routers7.throttle0.msg_count.Request_Control::3 141 -system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78538 -system.ruby.network.routers7.throttle0.msg_count.Response_Control::4 546411 -system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 74128 -system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 546562 -system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 1128 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5654736 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4371288 -system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 593024 -system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4372496 -system.ruby.network.routers7.throttle1.link_utilization 11.609004 -system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 78539 -system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 2506 -system.ruby.network.routers7.throttle1.msg_count.Response_Control::4 544196 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5 27694 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2 74130 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::5 46215 -system.ruby.network.routers7.throttle1.msg_count.Unblock_Control::5 78755 -system.ruby.network.routers7.throttle1.msg_bytes.Request_Control::2 628312 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 180432 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Control::4 4353568 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Data::5 1993968 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::2 593040 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::5 369720 -system.ruby.network.routers7.throttle1.msg_bytes.Unblock_Control::5 630040 -system.ruby.network.routers8.throttle0.link_utilization 44.604544 -system.ruby.network.routers8.throttle0.msg_count.Request_Control::2 626043 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Data::5 221095 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2 590607 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5 367967 -system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5 627535 -system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2 5008344 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5 15918840 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2 4724856 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5 2943736 -system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5 5020280 -system.ruby.network.routers8.throttle1.link_utilization 70.787742 -system.ruby.network.routers8.throttle1.msg_count.Request_Control::3 1058 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 605779 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 590583 -system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3 624964 -system.ruby.network.routers8.throttle1.msg_bytes.Request_Control::3 8464 -system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43616088 -system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4724664 -system.ruby.network.routers8.throttle1.msg_bytes.Broadcast_Control::3 4999712 -system.ruby.network.routers9.throttle0.link_utilization 19.845071 -system.ruby.network.routers9.throttle0.msg_count.Request_Control::3 139 -system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78266 -system.ruby.network.routers9.throttle0.msg_count.Response_Control::4 544412 -system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 73741 -system.ruby.network.routers9.throttle0.msg_count.Broadcast_Control::3 546834 -system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3 1112 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5635152 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4 4355296 -system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 589928 -system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4374672 -system.ruby.network.routers9.throttle1.link_utilization 19.818756 -system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 131 -system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78087 -system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 543391 -system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 73737 -system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 546999 -system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 1048 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5622264 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4 4347128 -system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 589896 -system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4375992 -system.ruby.network.routers9.throttle2.link_utilization 19.881353 -system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 122 -system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78462 -system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 546002 -system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 74045 -system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 546611 -system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 976 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5649264 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4368016 -system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 592360 -system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4372888 -system.ruby.network.routers9.throttle3.link_utilization 19.784470 -system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 152 -system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 77890 -system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 541933 -system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 73508 -system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 547208 -system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 1216 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5608080 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4335464 -system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 588064 -system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4377664 -system.ruby.network.routers9.throttle4.link_utilization 19.871078 -system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 142 -system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78404 -system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 545473 -system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 74018 -system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 546701 -system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 1136 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5645088 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4363784 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 592144 -system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4373608 -system.ruby.network.routers9.throttle5.link_utilization 19.858563 -system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 100 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78343 -system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 544986 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 73844 -system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 546774 -system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 800 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5640696 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4359888 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 590752 -system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4374192 -system.ruby.network.routers9.throttle6.link_utilization 19.807685 -system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 131 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78035 -system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 542939 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 73562 -system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 547058 -system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 1048 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5618520 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4343512 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 588496 -system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4376464 -system.ruby.network.routers9.throttle7.link_utilization 19.893529 -system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 141 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78538 -system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 546411 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 74128 -system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 546563 -system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 1128 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5654736 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4371288 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 593024 -system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4372504 -system.ruby.network.routers9.throttle8.link_utilization 44.604576 -system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 626043 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 221095 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 590607 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 367968 -system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 627535 -system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5008344 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15918840 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4724856 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2943744 -system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5020280 +system.ruby.network.routers0.percent_links_utilized 15.737393 +system.ruby.network.routers0.msg_count.Request_Control::2 78599 +system.ruby.network.routers0.msg_count.Request_Control::3 129 +system.ruby.network.routers0.msg_count.Response_Data::4 81242 +system.ruby.network.routers0.msg_count.Response_Control::4 1095039 +system.ruby.network.routers0.msg_count.Writeback_Data::5 27870 +system.ruby.network.routers0.msg_count.Writeback_Control::2 74172 +system.ruby.network.routers0.msg_count.Writeback_Control::3 74170 +system.ruby.network.routers0.msg_count.Writeback_Control::5 46105 +system.ruby.network.routers0.msg_count.Broadcast_Control::3 550644 +system.ruby.network.routers0.msg_count.Unblock_Control::5 78789 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+system.ruby.network.routers1.msg_bytes.Unblock_Control::5 631832 +system.ruby.network.routers2.percent_links_utilized 15.751157 +system.ruby.network.routers2.msg_count.Request_Control::2 78867 +system.ruby.network.routers2.msg_count.Request_Control::3 131 +system.ruby.network.routers2.msg_count.Response_Data::4 81472 +system.ruby.network.routers2.msg_count.Response_Control::4 1096583 +system.ruby.network.routers2.msg_count.Writeback_Data::5 27663 +system.ruby.network.routers2.msg_count.Writeback_Control::2 74294 +system.ruby.network.routers2.msg_count.Writeback_Control::3 74292 +system.ruby.network.routers2.msg_count.Writeback_Control::5 46452 +system.ruby.network.routers2.msg_count.Broadcast_Control::3 550392 +system.ruby.network.routers2.msg_count.Unblock_Control::5 79038 +system.ruby.network.routers2.msg_bytes.Request_Control::2 630936 +system.ruby.network.routers2.msg_bytes.Request_Control::3 1048 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5865984 +system.ruby.network.routers2.msg_bytes.Response_Control::4 8772664 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 1991736 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 594352 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 594336 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 371616 +system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4403136 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 632304 +system.ruby.network.routers3.percent_links_utilized 15.749123 +system.ruby.network.routers3.msg_count.Request_Control::2 78796 +system.ruby.network.routers3.msg_count.Request_Control::3 122 +system.ruby.network.routers3.msg_count.Response_Data::4 81321 +system.ruby.network.routers3.msg_count.Response_Control::4 1096238 +system.ruby.network.routers3.msg_count.Writeback_Data::5 27820 +system.ruby.network.routers3.msg_count.Writeback_Control::2 74344 +system.ruby.network.routers3.msg_count.Writeback_Control::3 74341 +system.ruby.network.routers3.msg_count.Writeback_Control::5 46330 +system.ruby.network.routers3.msg_count.Broadcast_Control::3 550453 +system.ruby.network.routers3.msg_count.Unblock_Control::5 78983 +system.ruby.network.routers3.msg_bytes.Request_Control::2 630368 +system.ruby.network.routers3.msg_bytes.Request_Control::3 976 +system.ruby.network.routers3.msg_bytes.Response_Data::4 5855112 +system.ruby.network.routers3.msg_bytes.Response_Control::4 8769904 +system.ruby.network.routers3.msg_bytes.Writeback_Data::5 2003040 +system.ruby.network.routers3.msg_bytes.Writeback_Control::2 594752 +system.ruby.network.routers3.msg_bytes.Writeback_Control::3 594728 +system.ruby.network.routers3.msg_bytes.Writeback_Control::5 370640 +system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4403624 +system.ruby.network.routers3.msg_bytes.Unblock_Control::5 631864 +system.ruby.network.routers4.percent_links_utilized 15.755366 +system.ruby.network.routers4.msg_count.Request_Control::2 78938 +system.ruby.network.routers4.msg_count.Request_Control::3 132 +system.ruby.network.routers4.msg_count.Response_Data::4 81528 +system.ruby.network.routers4.msg_count.Response_Control::4 1097025 +system.ruby.network.routers4.msg_count.Writeback_Data::5 27614 +system.ruby.network.routers4.msg_count.Writeback_Control::2 74357 +system.ruby.network.routers4.msg_count.Writeback_Control::3 74357 +system.ruby.network.routers4.msg_count.Writeback_Control::5 46551 +system.ruby.network.routers4.msg_count.Broadcast_Control::3 550297 +system.ruby.network.routers4.msg_count.Unblock_Control::5 79123 +system.ruby.network.routers4.msg_bytes.Request_Control::2 631504 +system.ruby.network.routers4.msg_bytes.Request_Control::3 1056 +system.ruby.network.routers4.msg_bytes.Response_Data::4 5870016 +system.ruby.network.routers4.msg_bytes.Response_Control::4 8776200 +system.ruby.network.routers4.msg_bytes.Writeback_Data::5 1988208 +system.ruby.network.routers4.msg_bytes.Writeback_Control::2 594856 +system.ruby.network.routers4.msg_bytes.Writeback_Control::3 594856 +system.ruby.network.routers4.msg_bytes.Writeback_Control::5 372408 +system.ruby.network.routers4.msg_bytes.Broadcast_Control::3 4402376 +system.ruby.network.routers4.msg_bytes.Unblock_Control::5 632984 +system.ruby.network.routers5.percent_links_utilized 15.726787 +system.ruby.network.routers5.msg_count.Request_Control::2 78686 +system.ruby.network.routers5.msg_count.Request_Control::3 133 +system.ruby.network.routers5.msg_count.Response_Data::4 81219 +system.ruby.network.routers5.msg_count.Response_Control::4 1095611 +system.ruby.network.routers5.msg_count.Writeback_Data::5 27527 +system.ruby.network.routers5.msg_count.Writeback_Control::2 74261 +system.ruby.network.routers5.msg_count.Writeback_Control::3 74258 +system.ruby.network.routers5.msg_count.Writeback_Control::5 46553 +system.ruby.network.routers5.msg_count.Broadcast_Control::3 550572 +system.ruby.network.routers5.msg_count.Unblock_Control::5 78859 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+system.ruby.network.routers9.msg_count.Response_Control::4 4384295 +system.ruby.network.routers9.msg_count.Writeback_Data::5 222137 +system.ruby.network.routers9.msg_count.Writeback_Control::2 594489 +system.ruby.network.routers9.msg_count.Writeback_Control::3 594473 +system.ruby.network.routers9.msg_count.Writeback_Control::5 370830 +system.ruby.network.routers9.msg_count.Broadcast_Control::3 4403854 +system.ruby.network.routers9.msg_count.Unblock_Control::5 631614 +system.ruby.network.routers9.msg_bytes.Request_Control::2 5041192 +system.ruby.network.routers9.msg_bytes.Request_Control::3 8080 +system.ruby.network.routers9.msg_bytes.Response_Data::4 45368640 +system.ruby.network.routers9.msg_bytes.Response_Control::4 35074360 +system.ruby.network.routers9.msg_bytes.Writeback_Data::5 15993864 +system.ruby.network.routers9.msg_bytes.Writeback_Control::2 4755912 +system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4755784 +system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2966640 +system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 35230832 +system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5052912 +system.ruby.network.msg_count.Request_Control 1893478 +system.ruby.network.msg_count.Response_Data 1890358 +system.ruby.network.msg_count.Response_Control 13152903 +system.ruby.network.msg_count.Writeback_Data 666411 +system.ruby.network.msg_count.Writeback_Control 4679382 +system.ruby.network.msg_count.Broadcast_Control 9436829 +system.ruby.network.msg_count.Unblock_Control 1894842 +system.ruby.network.msg_byte.Request_Control 15147824 +system.ruby.network.msg_byte.Response_Data 136105776 +system.ruby.network.msg_byte.Response_Control 105223224 +system.ruby.network.msg_byte.Writeback_Data 47981592 +system.ruby.network.msg_byte.Writeback_Control 37435056 +system.ruby.network.msg_byte.Broadcast_Control 75494632 +system.ruby.network.msg_byte.Unblock_Control 15158736 +system.ruby.network.routers0.throttle0.link_utilization 19.850636 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 129 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78595 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 546922 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 74170 +system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3 550644 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3 1032 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5658840 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 4375376 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 593360 +system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3 4405152 +system.ruby.network.routers0.throttle1.link_utilization 11.624150 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 78599 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+system.ruby.network.routers1.throttle0.link_utilization 19.886245 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::3 125 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78801 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::4 548416 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 74404 +system.ruby.network.routers1.throttle0.msg_count.Broadcast_Control::3 550437 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::3 1000 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5673672 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::4 4387328 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 595232 +system.ruby.network.routers1.throttle0.msg_bytes.Broadcast_Control::3 4403496 +system.ruby.network.routers1.throttle1.link_utilization 11.622386 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 78806 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 2503 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 548050 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::5 27909 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 74407 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::5 46318 +system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::5 78979 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 630448 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 180216 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 4384400 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::5 2009448 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 595256 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::5 370544 +system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::5 631832 +system.ruby.network.routers2.throttle0.link_utilization 19.893364 +system.ruby.network.routers2.throttle0.msg_count.Request_Control::3 131 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78864 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::4 548677 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 74292 +system.ruby.network.routers2.throttle0.msg_count.Broadcast_Control::3 550392 +system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::3 1048 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5678208 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::4 4389416 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 594336 +system.ruby.network.routers2.throttle0.msg_bytes.Broadcast_Control::3 4403136 +system.ruby.network.routers2.throttle1.link_utilization 11.608949 +system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 78867 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 2608 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::4 547906 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 27663 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 74294 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 46452 +system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 79038 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 630936 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 187776 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4 4383248 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 1991736 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 594352 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 371616 +system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 632304 +system.ruby.network.routers3.throttle0.link_utilization 19.882769 +system.ruby.network.routers3.throttle0.msg_count.Request_Control::3 122 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78794 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 548200 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 74341 +system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3 550453 +system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3 976 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5673168 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 4385600 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 594728 +system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3 4403624 +system.ruby.network.routers3.throttle1.link_utilization 11.615477 +system.ruby.network.routers3.throttle1.msg_count.Request_Control::2 78796 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 2527 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::4 548038 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5 27820 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2 74344 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5 46330 +system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5 78983 +system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2 630368 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 181944 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4 4384304 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5 2003040 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2 594752 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5 370640 +system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5 631864 +system.ruby.network.routers4.throttle0.link_utilization 19.905153 +system.ruby.network.routers4.throttle0.msg_count.Request_Control::3 132 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78933 +system.ruby.network.routers4.throttle0.msg_count.Response_Control::4 549198 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 74357 +system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3 550297 +system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3 1056 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5683176 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4 4393584 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 594856 +system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3 4402376 +system.ruby.network.routers4.throttle1.link_utilization 11.605579 +system.ruby.network.routers4.throttle1.msg_count.Request_Control::2 78938 +system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 2595 +system.ruby.network.routers4.throttle1.msg_count.Response_Control::4 547827 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5 27614 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2 74357 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5 46551 +system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5 79123 +system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2 631504 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 186840 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4 4382616 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5 1988208 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2 594856 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5 372408 +system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5 632984 +system.ruby.network.routers5.throttle0.link_utilization 19.864801 +system.ruby.network.routers5.throttle0.msg_count.Request_Control::3 133 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78683 +system.ruby.network.routers5.throttle0.msg_count.Response_Control::4 547451 +system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 74258 +system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3 550572 +system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3 1064 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5665176 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4 4379608 +system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 594064 +system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3 4404576 +system.ruby.network.routers5.throttle1.link_utilization 11.588773 +system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 78686 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 2536 +system.ruby.network.routers5.throttle1.msg_count.Response_Control::4 548160 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5 27527 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2 74261 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5 46553 +system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5 78859 +system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 629488 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 182592 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4 4385280 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5 1981944 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 594088 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 372424 +system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 630872 +system.ruby.network.routers6.throttle0.link_utilization 19.847340 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 121 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78581 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 546741 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 74151 +system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 550666 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 968 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5657832 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4373928 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 593208 +system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4405328 +system.ruby.network.routers6.throttle1.link_utilization 11.608178 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 78585 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+system.ruby.network.routers7.throttle0.link_utilization 19.896005 +system.ruby.network.routers7.throttle0.msg_count.Request_Control::3 117 +system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78869 +system.ruby.network.routers7.throttle0.msg_count.Response_Control::4 548686 +system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 74500 +system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 550391 +system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 936 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5678568 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4389488 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 596000 +system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4403128 +system.ruby.network.routers7.throttle1.link_utilization 11.628523 +system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 78873 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+system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3 1032 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5658840 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4 4375376 +system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 593360 +system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4405152 +system.ruby.network.routers9.throttle1.link_utilization 19.886245 +system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 125 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78801 +system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 548416 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 74404 +system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 550437 +system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 1000 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5673672 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+system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4403136 +system.ruby.network.routers9.throttle3.link_utilization 19.882812 +system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 122 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78794 +system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 548204 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 74341 +system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 550453 +system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 976 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5673168 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4385632 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 594728 +system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4403624 +system.ruby.network.routers9.throttle4.link_utilization 19.905153 +system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 132 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78933 +system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 549198 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 74357 +system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 550297 +system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 1056 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5683176 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4393584 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 594856 +system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4402376 +system.ruby.network.routers9.throttle5.link_utilization 19.864822 +system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 133 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78683 +system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 547451 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 74258 +system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 550574 +system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 1064 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5665176 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4379608 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 594064 +system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4404592 +system.ruby.network.routers9.throttle6.link_utilization 19.847340 +system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 121 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78581 +system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 546741 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 74151 +system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 550666 +system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 968 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5657832 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4373928 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 593208 +system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4405328 +system.ruby.network.routers9.throttle7.link_utilization 19.896005 +system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 117 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78869 +system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 548686 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 74500 +system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 550391 +system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 936 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5678568 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4389488 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 596000 +system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4403128 +system.ruby.network.routers9.throttle8.link_utilization 44.643544 +system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 630149 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 222137 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 594489 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 370830 +system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 631614 +system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5041192 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15993864 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4755912 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2966640 +system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5052912 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 402790 -system.ruby.LD.latency_hist::mean 961.759172 -system.ruby.LD.latency_hist::gmean 686.953304 -system.ruby.LD.latency_hist::stdev 670.169680 -system.ruby.LD.latency_hist | 150128 37.27% 37.27% | 74474 18.49% 55.76% | 75905 18.84% 74.61% | 78649 19.53% 94.13% | 22036 5.47% 99.60% | 1551 0.39% 99.99% | 46 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 402790 -system.ruby.LD.hit_latency_hist::bucket_size 128 -system.ruby.LD.hit_latency_hist::max_bucket 1279 -system.ruby.LD.hit_latency_hist::samples 459 -system.ruby.LD.hit_latency_hist::mean 95.638344 -system.ruby.LD.hit_latency_hist::gmean 30.555946 -system.ruby.LD.hit_latency_hist::stdev 138.573266 -system.ruby.LD.hit_latency_hist | 340 74.07% 74.07% | 75 16.34% 90.41% | 27 5.88% 96.30% | 8 1.74% 98.04% | 4 0.87% 98.91% | 2 0.44% 99.35% | 1 0.22% 99.56% | 0 0.00% 99.56% | 1 0.22% 99.78% | 1 0.22% 100.00% -system.ruby.LD.hit_latency_hist::total 459 +system.ruby.LD.latency_hist::samples 405857 +system.ruby.LD.latency_hist::mean 960.278100 +system.ruby.LD.latency_hist::gmean 687.146238 +system.ruby.LD.latency_hist::stdev 668.516283 +system.ruby.LD.latency_hist | 152104 37.48% 37.48% | 74658 18.40% 55.87% | 75456 18.59% 74.46% | 80607 19.86% 94.33% | 21579 5.32% 99.64% | 1421 0.35% 99.99% | 32 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 405857 +system.ruby.LD.hit_latency_hist::bucket_size 256 +system.ruby.LD.hit_latency_hist::max_bucket 2559 +system.ruby.LD.hit_latency_hist::samples 448 +system.ruby.LD.hit_latency_hist::mean 112.939732 +system.ruby.LD.hit_latency_hist::gmean 40.574546 +system.ruby.LD.hit_latency_hist::stdev 146.390268 +system.ruby.LD.hit_latency_hist | 403 89.96% 89.96% | 31 6.92% 96.88% | 11 2.46% 99.33% | 2 0.45% 99.78% | 0 0.00% 99.78% | 1 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 448 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 402331 -system.ruby.LD.miss_latency_hist::mean 962.747288 -system.ruby.LD.miss_latency_hist::gmean 689.397106 -system.ruby.LD.miss_latency_hist::stdev 669.896353 -system.ruby.LD.miss_latency_hist | 149678 37.20% 37.20% | 74467 18.51% 55.71% | 75903 18.87% 74.58% | 78649 19.55% 94.13% | 22036 5.48% 99.60% | 1551 0.39% 99.99% | 46 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 402331 +system.ruby.LD.miss_latency_hist::samples 405409 +system.ruby.LD.miss_latency_hist::mean 961.214457 +system.ruby.LD.miss_latency_hist::gmean 689.298070 +system.ruby.LD.miss_latency_hist::stdev 668.273872 +system.ruby.LD.miss_latency_hist | 151670 37.41% 37.41% | 74645 18.41% 55.82% | 75455 18.61% 74.44% | 80607 19.88% 94.32% | 21579 5.32% 99.64% | 1421 0.35% 99.99% | 32 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 405409 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223921 -system.ruby.ST.latency_hist::mean 962.135628 -system.ruby.ST.latency_hist::gmean 688.650583 -system.ruby.ST.latency_hist::stdev 669.628569 -system.ruby.ST.latency_hist | 83154 37.14% 37.14% | 41841 18.69% 55.82% | 42195 18.84% 74.66% | 43669 19.50% 94.17% | 12140 5.42% 99.59% | 890 0.40% 99.99% | 31 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223921 +system.ruby.ST.latency_hist::samples 224968 +system.ruby.ST.latency_hist::mean 960.364225 +system.ruby.ST.latency_hist::gmean 687.661138 +system.ruby.ST.latency_hist::stdev 668.409336 +system.ruby.ST.latency_hist | 84406 37.52% 37.52% | 41188 18.31% 55.83% | 42076 18.70% 74.53% | 44473 19.77% 94.30% | 12049 5.36% 99.66% | 755 0.34% 99.99% | 21 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 224968 system.ruby.ST.hit_latency_hist::bucket_size 256 system.ruby.ST.hit_latency_hist::max_bucket 2559 -system.ruby.ST.hit_latency_hist::samples 228 -system.ruby.ST.hit_latency_hist::mean 99.780702 -system.ruby.ST.hit_latency_hist::gmean 32.486812 -system.ruby.ST.hit_latency_hist::stdev 158.831790 -system.ruby.ST.hit_latency_hist | 209 91.67% 91.67% | 14 6.14% 97.81% | 4 1.75% 99.56% | 0 0.00% 99.56% | 0 0.00% 99.56% | 0 0.00% 99.56% | 1 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 228 +system.ruby.ST.hit_latency_hist::samples 255 +system.ruby.ST.hit_latency_hist::mean 97.745098 +system.ruby.ST.hit_latency_hist::gmean 32.839822 +system.ruby.ST.hit_latency_hist::stdev 139.085518 +system.ruby.ST.hit_latency_hist | 233 91.37% 91.37% | 17 6.67% 98.04% | 4 1.57% 99.61% | 0 0.00% 99.61% | 0 0.00% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 255 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 223693 -system.ruby.ST.miss_latency_hist::mean 963.014587 -system.ruby.ST.miss_latency_hist::gmean 690.797485 -system.ruby.ST.miss_latency_hist::stdev 669.384126 -system.ruby.ST.miss_latency_hist | 82931 37.07% 37.07% | 41837 18.70% 55.78% | 42195 18.86% 74.64% | 43668 19.52% 94.16% | 12140 5.43% 99.59% | 890 0.40% 99.99% | 31 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223693 +system.ruby.ST.miss_latency_hist::samples 224713 +system.ruby.ST.miss_latency_hist::mean 961.343109 +system.ruby.ST.miss_latency_hist::gmean 690.038778 +system.ruby.ST.miss_latency_hist::stdev 668.139804 +system.ruby.ST.miss_latency_hist | 84156 37.45% 37.45% | 41184 18.33% 55.78% | 42075 18.72% 74.50% | 44473 19.79% 94.29% | 12049 5.36% 99.65% | 755 0.34% 99.99% | 21 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 224713 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 154 +system.ruby.L1Cache.hit_mach_latency_hist::samples 145 system.ruby.L1Cache.hit_mach_latency_hist::mean 2 -system.ruby.L1Cache.hit_mach_latency_hist::gmean 2 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 154 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 154 +system.ruby.L1Cache.hit_mach_latency_hist::gmean 2.000000 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 145 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 145 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 23051 -system.ruby.L1Cache.miss_mach_latency_hist::mean 917.179992 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 631.311998 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 668.277259 -system.ruby.L1Cache.miss_mach_latency_hist | 9264 40.19% 40.19% | 4006 17.38% 57.57% | 4352 18.88% 76.45% | 4291 18.62% 95.06% | 1074 4.66% 99.72% | 61 0.26% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 23051 +system.ruby.L1Cache.miss_mach_latency_hist::samples 23137 +system.ruby.L1Cache.miss_mach_latency_hist::mean 922.547435 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 638.209231 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 666.692084 +system.ruby.L1Cache.miss_mach_latency_hist | 9174 39.65% 39.65% | 4098 17.71% 57.36% | 4329 18.71% 76.07% | 4414 19.08% 95.15% | 1060 4.58% 99.73% | 61 0.26% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 23137 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 21992 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 773.628319 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 22125 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::bucket_size 128 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::max_bucket 1279 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 21992 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 49.064478 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 20.912082 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 75.655363 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 19198 87.30% 87.30% | 2163 9.84% 97.13% | 495 2.25% 99.38% | 92 0.42% 99.80% | 38 0.17% 99.97% | 5 0.02% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 21992 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 22125 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-system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 49.391287 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3796 17.26% 17.26% | 4651 21.15% 38.41% | 5306 24.13% 62.54% | 3457 15.72% 78.26% | 2571 11.69% 89.95% | 1647 7.49% 97.44% | 520 2.36% 99.80% | 43 0.20% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 21992 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples 22125 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean 85.586983 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::gmean 70.964264 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 49.147197 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3841 17.36% 17.36% | 4772 21.57% 38.93% | 5269 23.81% 62.74% | 3490 15.77% 78.52% | 2590 11.71% 90.22% | 1631 7.37% 97.60% | 486 2.20% 99.79% | 45 0.20% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 22125 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::bucket_size 32 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 21992 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 10.106084 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 22.619571 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 19838 90.21% 90.21% | 977 4.44% 94.65% | 719 3.27% 97.92% | 362 1.65% 99.56% | 86 0.39% 99.95% | 9 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 21992 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 22125 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0.00% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 533 +system.ruby.L2Cache.hit_mach_latency_hist::samples 558 +system.ruby.L2Cache.hit_mach_latency_hist::mean 134.824373 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 80.532028 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 149.804509 +system.ruby.L2Cache.hit_mach_latency_hist | 491 87.99% 87.99% | 48 8.60% 96.59% | 15 2.69% 99.28% | 2 0.36% 99.64% | 0 0.00% 99.64% | 2 0.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 558 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 602973 -system.ruby.Directory.miss_mach_latency_hist::mean 964.588439 -system.ruby.Directory.miss_mach_latency_hist::gmean 692.241635 -system.ruby.Directory.miss_mach_latency_hist::stdev 669.706434 -system.ruby.Directory.miss_mach_latency_hist | 223345 37.04% 37.04% | 112298 18.62% 55.66% | 113746 18.86% 74.53% | 118026 19.57% 94.10% | 33102 5.49% 99.59% | 2380 0.39% 99.99% | 74 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 602973 +system.ruby.Directory.miss_mach_latency_hist::samples 606985 +system.ruby.Directory.miss_mach_latency_hist::mean 962.735992 +system.ruby.Directory.miss_mach_latency_hist::gmean 691.599319 +system.ruby.Directory.miss_mach_latency_hist::stdev 668.240095 +system.ruby.Directory.miss_mach_latency_hist | 226652 37.34% 37.34% | 111731 18.41% 55.75% | 113201 18.65% 74.40% | 120666 19.88% 94.28% | 32568 5.37% 99.64% | 2115 0.35% 99.99% | 52 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 606985 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 428414 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 787.219412 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 349.162275 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 658.219998 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 190127 44.38% 44.38% | 73544 17.17% 61.55% | 91535 21.37% 82.91% | 63246 14.76% 97.67% | 9543 2.23% 99.90% | 411 0.10% 100.00% | 8 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 428414 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 435259 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 784.321487 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 346.821847 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 657.460406 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 194525 44.69% 44.69% | 73174 16.81% 61.50% | 93400 21.46% 82.96% | 64531 14.83% 97.79% | 9251 2.13% 99.91% | 371 0.09% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 435259 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 64 system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 639 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 428414 -system.ruby.Directory.miss_latency_hist.initial_to_forward::mean 18.786942 -system.ruby.Directory.miss_latency_hist.initial_to_forward::gmean 12.944841 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev 21.002732 -system.ruby.Directory.miss_latency_hist.initial_to_forward | 397834 92.86% 92.86% | 30211 7.05% 99.91% | 312 0.07% 99.99% | 45 0.01% 100.00% | 9 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 428414 +system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 435259 +system.ruby.Directory.miss_latency_hist.initial_to_forward::mean 18.137679 +system.ruby.Directory.miss_latency_hist.initial_to_forward::gmean 12.662389 +system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev 20.299552 +system.ruby.Directory.miss_latency_hist.initial_to_forward | 407343 93.59% 93.59% | 27542 6.33% 99.91% | 308 0.07% 99.98% | 47 0.01% 100.00% | 11 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.initial_to_forward::total 435259 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 32 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 319 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 428414 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 61.066767 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 52.703942 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 33.547976 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 108299 25.28% 25.28% | 144980 33.84% 59.12% | 106832 24.94% 84.06% | 47268 11.03% 95.09% | 17336 4.05% 99.14% | 3507 0.82% 99.96% | 190 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 428414 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 435259 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-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 123.412429 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 68.596456 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 146.740195 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 235 66.38% 66.38% | 75 21.19% 87.57% | 27 7.63% 95.20% | 8 2.26% 97.46% | 4 1.13% 98.59% | 2 0.56% 99.15% | 1 0.28% 99.44% | 0 0.00% 99.44% | 1 0.28% 99.72% | 1 0.28% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 354 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13134 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 920.965662 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 633.755825 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 666.420559 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 5201 39.60% 39.60% | 2327 17.72% 57.32% | 2488 18.94% 76.26% | 2478 18.87% 95.13% | 599 4.56% 99.69% | 40 0.30% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13134 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 256 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 2559 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 360 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 140.058333 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 84.683196 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 151.422574 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 315 87.50% 87.50% | 31 8.61% 96.11% | 11 3.06% 99.17% | 2 0.56% 99.72% | 0 0.00% 99.72% | 1 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 360 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 389396 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 964.361601 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 691.682512 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 669.836857 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 144453 37.10% 37.10% | 72258 18.56% 55.65% | 73421 18.86% 74.51% | 76277 19.59% 94.10% | 21423 5.50% 99.60% | 1518 0.39% 99.99% | 45 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 389396 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 392275 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 962.562052 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 691.239651 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 668.294745 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 146469 37.34% 37.34% | 72318 18.44% 55.77% | 72967 18.60% 74.37% | 78129 19.92% 94.29% | 20980 5.35% 99.64% | 1381 0.35% 99.99% | 31 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 392275 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 49 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 57 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 49 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 57 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 57 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10116 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 921.054468 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 640.758055 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 666.219932 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 4039 39.93% 39.93% | 1797 17.76% 57.69% | 1870 18.49% 76.18% | 1919 18.97% 95.15% | 461 4.56% 99.70% | 28 0.28% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10116 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10003 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 924.624313 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 644.104136 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 667.076052 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 3973 39.72% 39.72% | 1771 17.70% 57.42% | 1841 18.40% 75.83% | 1936 19.35% 95.18% | 461 4.61% 99.79% | 21 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10003 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 256 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 2559 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 179 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 126.547486 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 69.682143 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 169.763754 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 160 89.39% 89.39% | 14 7.82% 97.21% | 4 2.23% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 179 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 198 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 125.308081 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 73.498803 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 146.717454 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 176 88.89% 88.89% | 17 8.59% 97.47% | 4 2.02% 99.49% | 0 0.00% 99.49% | 0 0.00% 99.49% | 1 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 198 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213577 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 965.002013 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 693.262198 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 669.469949 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 78892 36.94% 36.94% | 40040 18.75% 55.69% | 40325 18.88% 74.57% | 41749 19.55% 94.11% | 11679 5.47% 99.58% | 862 0.40% 99.99% | 29 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213577 -system.ruby.Directory_Controller.GETX 227677 0.00% 0.00% -system.ruby.Directory_Controller.GETS 408275 0.00% 0.00% -system.ruby.Directory_Controller.PUT 604225 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 1518 0.00% 0.00% -system.ruby.Directory_Controller.UnblockS 26146 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 599871 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Clean 7905 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Dirty 1418 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 360062 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 219677 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 605779 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 221094 0.00% 0.00% -system.ruby.Directory_Controller.All_Unblocks 1058 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETX 87 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETS 94 0.00% 0.00% -system.ruby.Directory_Controller.NX.PUT 10803 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 7224 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 11783 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 579803 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 9234 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 16635 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 207154 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 372772 0.00% 0.00% -system.ruby.Directory_Controller.E.PUT 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETX 582 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETS 1058 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 13362 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockS 8383 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 598303 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.PUT 16 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockS 26 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockM 556 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.PUT 37 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockS 46 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockM 1012 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETX 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETS 1 0.00% 0.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 214710 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 963.053780 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 692.256914 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 668.141678 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 80183 37.34% 37.34% | 39413 18.36% 55.70% | 40234 18.74% 74.44% | 42537 19.81% 94.25% | 11588 5.40% 99.65% | 734 0.34% 99.99% | 21 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 214710 +system.ruby.Directory_Controller.GETX 228707 0.00% 0.00% +system.ruby.Directory_Controller.GETS 411589 0.00% 0.00% +system.ruby.Directory_Controller.PUT 607987 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 1497 0.00% 0.00% +system.ruby.Directory_Controller.UnblockS 26223 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 603892 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Clean 8046 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Dirty 1391 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 362783 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220746 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 609650 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 222137 0.00% 0.00% +system.ruby.Directory_Controller.All_Unblocks 1010 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETX 72 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETS 95 0.00% 0.00% +system.ruby.Directory_Controller.NX.PUT 10905 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 7267 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 12027 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 583582 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 9352 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 16609 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 208035 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 375680 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETX 593 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETS 1010 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 13238 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockS 8544 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 602348 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.PUT 14 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockS 21 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockM 572 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.PUT 41 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockS 38 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockM 972 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.GETX 1 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.GETS 3 0.00% 0.00% system.ruby.Directory_Controller.NO_B_S_W.PUT 138 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.UnblockS 1059 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 1058 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.UnblockS 1012 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 1010 0.00% 0.00% system.ruby.Directory_Controller.O_B.GETX 9 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETS 25 0.00% 0.00% -system.ruby.Directory_Controller.O_B.UnblockS 16632 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETX 1927 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETS 3352 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 589145 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETX 51 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETS 103 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.Memory_Data 16634 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 1371 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 2380 0.00% 0.00% -system.ruby.Directory_Controller.WB.PUT 65 0.00% 0.00% -system.ruby.Directory_Controller.WB.Unblock 1518 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Clean 7905 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Dirty 1418 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 360062 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 219677 0.00% 0.00% -system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1418 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETX 34 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 71 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 219676 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50441 12.51% 12.51% | 50284 12.47% 24.99% | 50341 12.49% 37.48% | 50472 12.52% 50.00% | 50384 12.50% 62.50% | 50303 12.48% 74.98% | 50287 12.48% 87.45% | 50586 12.55% 100.00% -system.ruby.L1Cache_Controller.Load::total 403098 -system.ruby.L1Cache_Controller.Store | 27978 12.49% 12.49% | 27946 12.47% 24.96% | 28262 12.61% 37.57% | 27557 12.30% 49.87% | 28153 12.56% 62.43% | 28184 12.58% 75.01% | 27910 12.46% 87.47% | 28086 12.53% 100.00% -system.ruby.L1Cache_Controller.Store::total 224076 -system.ruby.L1Cache_Controller.L2_Replacement | 78258 12.50% 12.50% | 78079 12.47% 24.98% | 78452 12.53% 37.51% | 77881 12.44% 49.95% | 78395 12.52% 62.48% | 78336 12.51% 74.99% | 78026 12.47% 87.45% | 78526 12.55% 100.00% -system.ruby.L1Cache_Controller.L2_Replacement::total 625953 -system.ruby.L1Cache_Controller.L1_to_L2 | 976938 12.50% 12.50% | 978501 12.52% 25.01% | 977534 12.50% 37.52% | 974694 12.47% 49.98% | 977852 12.51% 62.49% | 976494 12.49% 74.98% | 976920 12.50% 87.48% | 978975 12.52% 100.00% -system.ruby.L1Cache_Controller.L1_to_L2::total 7817908 -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 73 13.37% 13.37% | 64 11.72% 25.09% | 59 10.81% 35.90% | 74 13.55% 49.45% | 63 11.54% 60.99% | 64 11.72% 72.71% | 79 14.47% 87.18% | 70 12.82% 100.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 546 -system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 73 13.37% 13.37% | 64 11.72% 25.09% | 59 10.81% 35.90% | 74 13.55% 49.45% | 63 11.54% 60.99% | 64 11.72% 72.71% | 79 14.47% 87.18% | 70 12.82% 100.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 546 -system.ruby.L1Cache_Controller.Other_GETX | 195769 12.50% 12.50% | 195808 12.50% 25.01% | 195461 12.48% 37.49% | 196183 12.53% 50.02% | 195586 12.49% 62.51% | 195564 12.49% 75.00% | 195830 12.51% 87.50% | 195657 12.50% 100.00% -system.ruby.L1Cache_Controller.Other_GETX::total 1565858 -system.ruby.L1Cache_Controller.Other_GETS | 351064 12.50% 12.50% | 351190 12.50% 25.00% | 351149 12.50% 37.50% | 351024 12.50% 50.00% | 351114 12.50% 62.50% | 351209 12.50% 75.00% | 351228 12.50% 87.51% | 350905 12.49% 100.00% -system.ruby.L1Cache_Controller.Other_GETS::total 2808883 -system.ruby.L1Cache_Controller.Merged_GETS | 139 13.14% 13.14% | 131 12.38% 25.52% | 122 11.53% 37.05% | 152 14.37% 51.42% | 142 13.42% 64.84% | 100 9.45% 74.29% | 131 12.38% 86.67% | 141 13.33% 100.00% -system.ruby.L1Cache_Controller.Merged_GETS::total 1058 -system.ruby.L1Cache_Controller.Ack | 544353 12.50% 12.50% | 543353 12.48% 24.98% | 545955 12.54% 37.51% | 541876 12.44% 49.95% | 545429 12.52% 62.48% | 544934 12.51% 74.99% | 542876 12.47% 87.46% | 546350 12.54% 100.00% -system.ruby.L1Cache_Controller.Ack::total 4355126 -system.ruby.L1Cache_Controller.Shared_Ack | 59 14.01% 14.01% | 38 9.03% 23.04% | 47 11.16% 34.20% | 57 13.54% 47.74% | 44 10.45% 58.19% | 52 12.35% 70.55% | 63 14.96% 85.51% | 61 14.49% 100.00% -system.ruby.L1Cache_Controller.Shared_Ack::total 421 -system.ruby.L1Cache_Controller.Data | 3443 12.55% 12.55% | 3428 12.50% 25.05% | 3401 12.40% 37.44% | 3393 12.37% 49.81% | 3427 12.49% 62.30% | 3495 12.74% 75.04% | 3416 12.45% 87.49% | 3431 12.51% 100.00% -system.ruby.L1Cache_Controller.Data::total 27434 -system.ruby.L1Cache_Controller.Shared_Data | 1248 13.12% 13.12% | 1157 12.16% 25.28% | 1179 12.39% 37.67% | 1166 12.26% 49.93% | 1183 12.43% 62.36% | 1208 12.70% 75.06% | 1185 12.46% 87.51% | 1188 12.49% 100.00% -system.ruby.L1Cache_Controller.Shared_Data::total 9514 -system.ruby.L1Cache_Controller.Exclusive_Data | 73575 12.49% 12.49% | 73502 12.48% 24.97% | 73882 12.54% 37.51% | 73331 12.45% 49.96% | 73794 12.53% 62.48% | 73640 12.50% 74.99% | 73433 12.47% 87.45% | 73919 12.55% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 589076 -system.ruby.L1Cache_Controller.Writeback_Ack | 73741 12.49% 12.49% | 73736 12.49% 24.97% | 74045 12.54% 37.51% | 73508 12.45% 49.96% | 74018 12.53% 62.49% | 73844 12.50% 74.99% | 73562 12.46% 87.45% | 74128 12.55% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 590582 -system.ruby.L1Cache_Controller.Writeback_Nack | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 1 -system.ruby.L1Cache_Controller.All_acks | 1299 13.13% 13.13% | 1192 12.05% 25.18% | 1222 12.35% 37.54% | 1212 12.25% 49.79% | 1221 12.34% 62.14% | 1259 12.73% 74.87% | 1245 12.59% 87.45% | 1241 12.55% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 9891 -system.ruby.L1Cache_Controller.All_acks_no_sharers | 76966 12.49% 12.49% | 76895 12.48% 24.97% | 77240 12.54% 37.51% | 76678 12.45% 49.95% | 77182 12.53% 62.48% | 77082 12.51% 74.99% | 76789 12.46% 87.45% | 77296 12.55% 100.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers::total 616128 -system.ruby.L1Cache_Controller.I.Load | 50343 12.51% 12.51% | 50202 12.48% 24.99% | 50229 12.48% 37.47% | 50381 12.52% 50.00% | 50297 12.50% 62.50% | 50214 12.48% 74.98% | 50172 12.47% 87.45% | 50503 12.55% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 402341 -system.ruby.L1Cache_Controller.I.Store | 27925 12.48% 12.48% | 27886 12.47% 24.95% | 28233 12.62% 37.57% | 27511 12.30% 49.87% | 28108 12.57% 62.44% | 28131 12.58% 75.01% | 27864 12.46% 87.47% | 28034 12.53% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 223692 -system.ruby.L1Cache_Controller.I.L2_Replacement | 1231 13.06% 13.06% | 1181 12.53% 25.59% | 1181 12.53% 38.11% | 1159 12.29% 50.41% | 1164 12.35% 62.76% | 1144 12.14% 74.89% | 1231 13.06% 87.95% | 1136 12.05% 100.00% -system.ruby.L1Cache_Controller.I.L2_Replacement::total 9427 -system.ruby.L1Cache_Controller.I.L1_to_L2 | 85 12.25% 12.25% | 91 13.11% 25.36% | 73 10.52% 35.88% | 83 11.96% 47.84% | 90 12.97% 60.81% | 97 13.98% 74.78% | 89 12.82% 87.61% | 86 12.39% 100.00% -system.ruby.L1Cache_Controller.I.L1_to_L2::total 694 -system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 0 0.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total 8 -system.ruby.L1Cache_Controller.I.Other_GETX | 194598 12.50% 12.50% | 194683 12.50% 25.00% | 194349 12.48% 37.49% | 195081 12.53% 50.02% | 194486 12.49% 62.51% | 194479 12.49% 75.00% | 194715 12.51% 87.51% | 194530 12.49% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETX::total 1556921 -system.ruby.L1Cache_Controller.I.Other_GETS | 349168 12.50% 12.50% | 349401 12.51% 25.00% | 349271 12.50% 37.50% | 349157 12.50% 50.00% | 349254 12.50% 62.50% | 349362 12.50% 75.00% | 349363 12.50% 87.51% | 349100 12.49% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETS::total 2794076 -system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 2 -system.ruby.L1Cache_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory_Controller.O_B.GETS 27 0.00% 0.00% +system.ruby.Directory_Controller.O_B.UnblockS 16608 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETX 1928 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETS 3580 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 593042 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETX 49 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETS 101 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.Memory_Data 16608 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 1361 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 2377 0.00% 0.00% +system.ruby.Directory_Controller.WB.PUT 69 0.00% 0.00% +system.ruby.Directory_Controller.WB.Unblock 1497 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Clean 8046 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Dirty 1391 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 362783 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220746 0.00% 0.00% +system.ruby.Directory_Controller.WB_O_W.GETX 1 0.00% 0.00% +system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1391 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETX 39 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 78 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220746 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50425 12.41% 12.41% | 50709 12.48% 24.90% | 50956 12.55% 37.45% | 50792 12.51% 49.95% | 51090 12.58% 62.53% | 50892 12.53% 75.06% | 50587 12.45% 87.51% | 50715 12.49% 100.00% +system.ruby.L1Cache_Controller.Load::total 406166 +system.ruby.L1Cache_Controller.Store | 28286 12.56% 12.56% | 28252 12.55% 25.11% | 28051 12.46% 37.57% | 28152 12.50% 50.08% | 27992 12.43% 62.51% | 27935 12.41% 74.92% | 28146 12.50% 87.42% | 28326 12.58% 100.00% +system.ruby.L1Cache_Controller.Store::total 225140 +system.ruby.L1Cache_Controller.L2_Replacement | 78587 12.47% 12.47% | 78793 12.51% 24.98% | 78855 12.52% 37.49% | 78785 12.50% 50.00% | 78925 12.53% 62.53% | 78672 12.49% 75.01% | 78574 12.47% 87.48% | 78861 12.52% 100.00% +system.ruby.L1Cache_Controller.L2_Replacement::total 630052 +system.ruby.L1Cache_Controller.L1_to_L2 | 979843 12.49% 12.49% | 985286 12.56% 25.04% | 982191 12.52% 37.56% | 981607 12.51% 50.06% | 980625 12.50% 62.56% | 979114 12.48% 75.04% | 981906 12.51% 87.55% | 977135 12.45% 100.00% +system.ruby.L1Cache_Controller.L1_to_L2::total 7847707 +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 58 10.07% 10.07% | 65 11.28% 21.35% | 70 12.15% 33.51% | 75 13.02% 46.53% | 70 12.15% 58.68% | 68 11.81% 70.49% | 84 14.58% 85.07% | 86 14.93% 100.00% +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 576 +system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 58 10.07% 10.07% | 65 11.28% 21.35% | 70 12.15% 33.51% | 75 13.02% 46.53% | 70 12.15% 58.68% | 68 11.81% 70.49% | 84 14.58% 85.07% | 86 14.93% 100.00% +system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 576 +system.ruby.L1Cache_Controller.Other_GETX | 196471 12.49% 12.49% | 196526 12.49% 24.98% | 196715 12.51% 37.49% | 196608 12.50% 49.99% | 196780 12.51% 62.50% | 196834 12.51% 75.01% | 196619 12.50% 87.51% | 196466 12.49% 100.00% +system.ruby.L1Cache_Controller.Other_GETX::total 1573019 +system.ruby.L1Cache_Controller.Other_GETS | 354173 12.51% 12.51% | 353911 12.50% 25.01% | 353677 12.49% 37.51% | 353845 12.50% 50.01% | 353517 12.49% 62.49% | 353736 12.50% 74.99% | 354047 12.51% 87.50% | 353925 12.50% 100.00% +system.ruby.L1Cache_Controller.Other_GETS::total 2830831 +system.ruby.L1Cache_Controller.Merged_GETS | 129 12.77% 12.77% | 125 12.38% 25.15% | 131 12.97% 38.12% | 122 12.08% 50.20% | 132 13.07% 63.27% | 133 13.17% 76.44% | 121 11.98% 88.42% | 117 11.58% 100.00% +system.ruby.L1Cache_Controller.Merged_GETS::total 1010 +system.ruby.L1Cache_Controller.Ack | 546875 12.47% 12.47% | 548356 12.51% 24.98% | 548622 12.51% 37.50% | 548157 12.50% 50.00% | 549146 12.53% 62.53% | 547407 12.49% 75.01% | 546694 12.47% 87.49% | 548631 12.51% 100.00% +system.ruby.L1Cache_Controller.Ack::total 4383888 +system.ruby.L1Cache_Controller.Shared_Ack | 47 11.66% 11.66% | 60 14.89% 26.55% | 55 13.65% 40.20% | 43 10.67% 50.87% | 52 12.90% 63.77% | 44 10.92% 74.69% | 47 11.66% 86.35% | 55 13.65% 100.00% +system.ruby.L1Cache_Controller.Shared_Ack::total 403 +system.ruby.L1Cache_Controller.Data | 3359 12.22% 12.22% | 3473 12.63% 24.85% | 3497 12.72% 37.57% | 3463 12.60% 50.16% | 3413 12.41% 62.58% | 3427 12.46% 75.04% | 3416 12.42% 87.47% | 3446 12.53% 100.00% +system.ruby.L1Cache_Controller.Data::total 27494 +system.ruby.L1Cache_Controller.Shared_Data | 1154 12.00% 12.00% | 1176 12.23% 24.23% | 1180 12.27% 36.51% | 1237 12.87% 49.37% | 1274 13.25% 62.62% | 1156 12.02% 74.64% | 1231 12.80% 87.45% | 1207 12.55% 100.00% +system.ruby.L1Cache_Controller.Shared_Data::total 9615 +system.ruby.L1Cache_Controller.Exclusive_Data | 74082 12.49% 12.49% | 74152 12.50% 25.00% | 74187 12.51% 37.51% | 74094 12.49% 50.00% | 74246 12.52% 62.52% | 74100 12.50% 75.02% | 73934 12.47% 87.48% | 74216 12.52% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 593011 +system.ruby.L1Cache_Controller.Writeback_Ack | 74170 12.48% 12.48% | 74404 12.52% 24.99% | 74292 12.50% 37.49% | 74341 12.51% 50.00% | 74357 12.51% 62.50% | 74258 12.49% 74.99% | 74151 12.47% 87.47% | 74500 12.53% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 594473 +system.ruby.L1Cache_Controller.All_acks | 1194 11.98% 11.98% | 1225 12.29% 24.27% | 1234 12.38% 36.65% | 1275 12.79% 49.44% | 1320 13.24% 62.68% | 1193 11.97% 74.65% | 1269 12.73% 87.38% | 1258 12.62% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 9968 +system.ruby.L1Cache_Controller.All_acks_no_sharers | 77401 12.48% 12.48% | 77577 12.51% 24.99% | 77629 12.52% 37.51% | 77517 12.50% 50.01% | 77614 12.52% 62.52% | 77490 12.50% 75.02% | 77312 12.47% 87.49% | 77611 12.51% 100.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers::total 620151 +system.ruby.L1Cache_Controller.I.Load | 50351 12.42% 12.42% | 50613 12.48% 24.90% | 50864 12.55% 37.45% | 50687 12.50% 49.95% | 51000 12.58% 62.53% | 50800 12.53% 75.06% | 50486 12.45% 87.51% | 50617 12.49% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 405418 +system.ruby.L1Cache_Controller.I.Store | 28246 12.57% 12.57% | 28190 12.54% 25.11% | 28000 12.46% 37.58% | 28107 12.51% 50.08% | 27935 12.43% 62.51% | 27882 12.41% 74.92% | 28099 12.50% 87.43% | 28254 12.57% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 224713 +system.ruby.L1Cache_Controller.I.L2_Replacement | 1236 12.89% 12.89% | 1152 12.01% 24.90% | 1250 13.03% 37.93% | 1180 12.30% 50.23% | 1243 12.96% 63.19% | 1211 12.63% 75.81% | 1148 11.97% 87.78% | 1172 12.22% 100.00% +system.ruby.L1Cache_Controller.I.L2_Replacement::total 9592 +system.ruby.L1Cache_Controller.I.L1_to_L2 | 99 12.47% 12.47% | 92 11.59% 24.06% | 95 11.96% 36.02% | 85 10.71% 46.73% | 93 11.71% 58.44% | 121 15.24% 73.68% | 87 10.96% 84.63% | 122 15.37% 100.00% +system.ruby.L1Cache_Controller.I.L1_to_L2::total 794 +system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 1 11.11% 11.11% | 1 11.11% 22.22% | 1 11.11% 33.33% | 0 0.00% 33.33% | 2 22.22% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total 9 +system.ruby.L1Cache_Controller.I.Other_GETX | 195341 12.49% 12.49% | 195451 12.50% 24.99% | 195544 12.50% 37.49% | 195508 12.50% 49.99% | 195605 12.51% 62.49% | 195730 12.51% 75.01% | 195526 12.50% 87.51% | 195339 12.49% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETX::total 1564044 +system.ruby.L1Cache_Controller.I.Other_GETS | 352206 12.51% 12.51% | 352024 12.50% 25.01% | 351754 12.49% 37.50% | 351944 12.50% 50.00% | 351596 12.49% 62.49% | 351866 12.50% 74.99% | 352184 12.51% 87.50% | 352077 12.50% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETS::total 2815651 +system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 3 +system.ruby.L1Cache_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Store::total 1 -system.ruby.L1Cache_Controller.S.L2_Replacement | 3281 12.66% 12.66% | 3158 12.19% 24.84% | 3224 12.44% 37.28% | 3212 12.39% 49.68% | 3210 12.39% 62.06% | 3343 12.90% 74.96% | 3230 12.46% 87.43% | 3259 12.57% 100.00% -system.ruby.L1Cache_Controller.S.L2_Replacement::total 25917 -system.ruby.L1Cache_Controller.S.L1_to_L2 | 3309 12.66% 12.66% | 3182 12.17% 24.83% | 3249 12.43% 37.26% | 3236 12.38% 49.64% | 3243 12.41% 62.05% | 3372 12.90% 74.95% | 3258 12.46% 87.41% | 3290 12.59% 100.00% -system.ruby.L1Cache_Controller.S.L1_to_L2::total 26139 -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 1 5.56% 5.56% | 2 11.11% 16.67% | 1 5.56% 22.22% | 5 27.78% 50.00% | 0 0.00% 50.00% | 1 5.56% 55.56% | 3 16.67% 72.22% | 5 27.78% 100.00% -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 18 -system.ruby.L1Cache_Controller.S.Other_GETX | 27 12.16% 12.16% | 23 10.36% 22.52% | 25 11.26% 33.78% | 23 10.36% 44.14% | 37 16.67% 60.81% | 31 13.96% 74.77% | 28 12.61% 87.39% | 28 12.61% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETX::total 222 -system.ruby.L1Cache_Controller.S.Other_GETS | 50 11.88% 11.88% | 58 13.78% 25.65% | 48 11.40% 37.05% | 57 13.54% 50.59% | 53 12.59% 63.18% | 48 11.40% 74.58% | 56 13.30% 87.89% | 51 12.11% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETS::total 421 -system.ruby.L1Cache_Controller.O.L2_Replacement | 853 12.74% 12.74% | 805 12.02% 24.76% | 861 12.86% 37.62% | 860 12.84% 50.46% | 837 12.50% 62.96% | 826 12.34% 75.30% | 802 11.98% 87.28% | 852 12.72% 100.00% -system.ruby.L1Cache_Controller.O.L2_Replacement::total 6696 -system.ruby.L1Cache_Controller.O.L1_to_L2 | 72 12.50% 12.50% | 69 11.98% 24.48% | 72 12.50% 36.98% | 78 13.54% 50.52% | 78 13.54% 64.06% | 62 10.76% 74.83% | 75 13.02% 87.85% | 70 12.15% 100.00% -system.ruby.L1Cache_Controller.O.L1_to_L2::total 576 -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 5 -system.ruby.L1Cache_Controller.O.Other_GETX | 6 12.77% 12.77% | 5 10.64% 23.40% | 9 19.15% 42.55% | 8 17.02% 59.57% | 7 14.89% 74.47% | 3 6.38% 80.85% | 7 14.89% 95.74% | 2 4.26% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETX::total 47 -system.ruby.L1Cache_Controller.O.Other_GETS | 8 16.33% 16.33% | 5 10.20% 26.53% | 4 8.16% 34.69% | 7 14.29% 48.98% | 4 8.16% 57.14% | 9 18.37% 75.51% | 5 10.20% 85.71% | 7 14.29% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETS::total 49 -system.ruby.L1Cache_Controller.O.Merged_GETS | 3 13.04% 13.04% | 4 17.39% 30.43% | 4 17.39% 47.83% | 3 13.04% 60.87% | 4 17.39% 78.26% | 2 8.70% 86.96% | 1 4.35% 91.30% | 2 8.70% 100.00% -system.ruby.L1Cache_Controller.O.Merged_GETS::total 23 -system.ruby.L1Cache_Controller.M.Load | 3 8.33% 8.33% | 5 13.89% 22.22% | 7 19.44% 41.67% | 3 8.33% 50.00% | 6 16.67% 66.67% | 6 16.67% 83.33% | 1 2.78% 86.11% | 5 13.89% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 36 -system.ruby.L1Cache_Controller.M.Store | 2 11.76% 11.76% | 4 23.53% 35.29% | 3 17.65% 52.94% | 0 0.00% 52.94% | 0 0.00% 52.94% | 5 29.41% 82.35% | 3 17.65% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 17 -system.ruby.L1Cache_Controller.M.L2_Replacement | 45717 12.49% 12.49% | 45764 12.50% 25.00% | 45686 12.48% 37.48% | 45851 12.53% 50.01% | 45789 12.51% 62.52% | 45558 12.45% 74.97% | 45647 12.47% 87.44% | 45961 12.56% 100.00% -system.ruby.L1Cache_Controller.M.L2_Replacement::total 365973 -system.ruby.L1Cache_Controller.M.L1_to_L2 | 46965 12.51% 12.51% | 46934 12.50% 25.00% | 46906 12.49% 37.49% | 47064 12.53% 50.02% | 46964 12.50% 62.53% | 46761 12.45% 74.98% | 46832 12.47% 87.45% | 47142 12.55% 100.00% -system.ruby.L1Cache_Controller.M.L1_to_L2::total 375568 -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 43 13.87% 13.87% | 35 11.29% 25.16% | 31 10.00% 35.16% | 44 14.19% 49.35% | 35 11.29% 60.65% | 43 13.87% 74.52% | 42 13.55% 88.06% | 37 11.94% 100.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 310 -system.ruby.L1Cache_Controller.M.Other_GETX | 481 13.18% 13.18% | 466 12.77% 25.95% | 455 12.47% 38.42% | 444 12.17% 50.59% | 438 12.00% 62.59% | 461 12.63% 75.23% | 479 13.13% 88.35% | 425 11.65% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETX::total 3649 -system.ruby.L1Cache_Controller.M.Other_GETS | 748 12.76% 12.76% | 702 11.97% 24.73% | 764 13.03% 37.76% | 746 12.72% 50.48% | 725 12.36% 62.84% | 741 12.64% 75.48% | 698 11.90% 87.38% | 740 12.62% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETS::total 5864 -system.ruby.L1Cache_Controller.M.Merged_GETS | 64 12.14% 12.14% | 63 11.95% 24.10% | 62 11.76% 35.86% | 79 14.99% 50.85% | 78 14.80% 65.65% | 50 9.49% 75.14% | 63 11.95% 87.10% | 68 12.90% 100.00% -system.ruby.L1Cache_Controller.M.Merged_GETS::total 527 -system.ruby.L1Cache_Controller.MM.Load | 3 12.00% 12.00% | 1 4.00% 16.00% | 2 8.00% 24.00% | 5 20.00% 44.00% | 4 16.00% 60.00% | 3 12.00% 72.00% | 4 16.00% 88.00% | 3 12.00% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 25 -system.ruby.L1Cache_Controller.MM.Store | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 1 9.09% 54.55% | 0 0.00% 54.55% | 1 9.09% 63.64% | 4 36.36% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 11 -system.ruby.L1Cache_Controller.MM.L2_Replacement | 27176 12.47% 12.47% | 27171 12.47% 24.94% | 27500 12.62% 37.55% | 26799 12.30% 49.85% | 27395 12.57% 62.42% | 27465 12.60% 75.02% | 27116 12.44% 87.47% | 27318 12.53% 100.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement::total 217940 -system.ruby.L1Cache_Controller.MM.L1_to_L2 | 27906 12.48% 12.48% | 27872 12.47% 24.95% | 28217 12.62% 37.57% | 27501 12.30% 49.87% | 28089 12.56% 62.43% | 28113 12.57% 75.01% | 27857 12.46% 87.47% | 28015 12.53% 100.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2::total 223570 -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 27 13.17% 13.17% | 25 12.20% 25.37% | 24 11.71% 37.07% | 25 12.20% 49.27% | 26 12.68% 61.95% | 19 9.27% 71.22% | 33 16.10% 87.32% | 26 12.68% 100.00% +system.ruby.L1Cache_Controller.S.L2_Replacement | 3179 12.24% 12.24% | 3234 12.45% 24.69% | 3311 12.75% 37.44% | 3261 12.56% 50.00% | 3325 12.80% 62.80% | 3200 12.32% 75.13% | 3275 12.61% 87.74% | 3185 12.26% 100.00% +system.ruby.L1Cache_Controller.S.L2_Replacement::total 25970 +system.ruby.L1Cache_Controller.S.L1_to_L2 | 3204 12.23% 12.23% | 3269 12.47% 24.70% | 3343 12.76% 37.46% | 3292 12.56% 50.02% | 3354 12.80% 62.82% | 3229 12.32% 75.14% | 3299 12.59% 87.72% | 3217 12.28% 100.00% +system.ruby.L1Cache_Controller.S.L1_to_L2::total 26207 +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 4 20.00% 20.00% | 1 5.00% 25.00% | 2 10.00% 35.00% | 3 15.00% 50.00% | 2 10.00% 60.00% | 2 10.00% 70.00% | 3 15.00% 85.00% | 3 15.00% 100.00% +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 20 +system.ruby.L1Cache_Controller.S.Other_GETX | 25 10.29% 10.29% | 35 14.40% 24.69% | 33 13.58% 38.27% | 30 12.35% 50.62% | 29 11.93% 62.55% | 33 13.58% 76.13% | 24 9.88% 86.01% | 34 13.99% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETX::total 243 +system.ruby.L1Cache_Controller.S.Other_GETS | 44 10.92% 10.92% | 50 12.41% 23.33% | 48 11.91% 35.24% | 49 12.16% 47.39% | 52 12.90% 60.30% | 52 12.90% 73.20% | 61 15.14% 88.34% | 47 11.66% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETS::total 403 +system.ruby.L1Cache_Controller.O.L2_Replacement | 898 13.24% 13.24% | 855 12.61% 25.84% | 861 12.69% 38.54% | 871 12.84% 51.38% | 823 12.13% 63.51% | 817 12.04% 75.56% | 846 12.47% 88.03% | 812 11.97% 100.00% +system.ruby.L1Cache_Controller.O.L2_Replacement::total 6783 +system.ruby.L1Cache_Controller.O.L1_to_L2 | 75 13.16% 13.16% | 74 12.98% 26.14% | 66 11.58% 37.72% | 72 12.63% 50.35% | 66 11.58% 61.93% | 73 12.81% 74.74% | 82 14.39% 89.12% | 62 10.88% 100.00% +system.ruby.L1Cache_Controller.O.L1_to_L2::total 570 +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 3 +system.ruby.L1Cache_Controller.O.Other_GETX | 5 13.16% 13.16% | 3 7.89% 21.05% | 7 18.42% 39.47% | 5 13.16% 52.63% | 2 5.26% 57.89% | 4 10.53% 68.42% | 5 13.16% 81.58% | 7 18.42% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETX::total 38 +system.ruby.L1Cache_Controller.O.Other_GETS | 2 3.64% 3.64% | 5 9.09% 12.73% | 9 16.36% 29.09% | 5 9.09% 38.18% | 10 18.18% 56.36% | 6 10.91% 67.27% | 10 18.18% 85.45% | 8 14.55% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETS::total 55 +system.ruby.L1Cache_Controller.O.Merged_GETS | 0 0.00% 0.00% | 2 14.29% 14.29% | 1 7.14% 21.43% | 1 7.14% 28.57% | 2 14.29% 42.86% | 3 21.43% 64.29% | 2 14.29% 78.57% | 3 21.43% 100.00% +system.ruby.L1Cache_Controller.O.Merged_GETS::total 14 +system.ruby.L1Cache_Controller.M.Load | 5 13.51% 13.51% | 9 24.32% 37.84% | 7 18.92% 56.76% | 5 13.51% 70.27% | 2 5.41% 75.68% | 1 2.70% 78.38% | 4 10.81% 89.19% | 4 10.81% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 37 +system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 7 35.00% 35.00% | 0 0.00% 35.00% | 3 15.00% 50.00% | 2 10.00% 60.00% | 2 10.00% 70.00% | 2 10.00% 80.00% | 4 20.00% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 20 +system.ruby.L1Cache_Controller.M.L2_Replacement | 45800 12.42% 12.42% | 46049 12.49% 24.90% | 46199 12.53% 37.43% | 46062 12.49% 49.92% | 46337 12.56% 62.48% | 46329 12.56% 75.05% | 45903 12.45% 87.49% | 46127 12.51% 100.00% +system.ruby.L1Cache_Controller.M.L2_Replacement::total 368806 +system.ruby.L1Cache_Controller.M.L1_to_L2 | 47052 12.43% 12.43% | 47253 12.48% 24.91% | 47440 12.53% 37.45% | 47312 12.50% 49.95% | 47567 12.57% 62.51% | 47475 12.54% 75.06% | 47100 12.44% 87.50% | 47318 12.50% 100.00% +system.ruby.L1Cache_Controller.M.L1_to_L2::total 378517 +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 32 9.44% 9.44% | 37 10.91% 20.35% | 37 10.91% 31.27% | 48 14.16% 45.43% | 43 12.68% 58.11% | 39 11.50% 69.62% | 53 15.63% 85.25% | 50 14.75% 100.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 339 +system.ruby.L1Cache_Controller.M.Other_GETX | 465 12.67% 12.67% | 445 12.13% 24.80% | 472 12.86% 37.67% | 457 12.46% 50.12% | 497 13.55% 63.67% | 429 11.69% 75.36% | 449 12.24% 87.60% | 455 12.40% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETX::total 3669 +system.ruby.L1Cache_Controller.M.Other_GETS | 787 13.14% 13.14% | 748 12.49% 25.62% | 758 12.65% 38.27% | 778 12.99% 51.26% | 725 12.10% 63.36% | 725 12.10% 75.46% | 745 12.44% 87.90% | 725 12.10% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETS::total 5991 +system.ruby.L1Cache_Controller.M.Merged_GETS | 74 13.91% 13.91% | 72 13.53% 27.44% | 69 12.97% 40.41% | 68 12.78% 53.20% | 61 11.47% 64.66% | 61 11.47% 76.13% | 66 12.41% 88.53% | 61 11.47% 100.00% +system.ruby.L1Cache_Controller.M.Merged_GETS::total 532 +system.ruby.L1Cache_Controller.MM.Load | 0 0.00% 0.00% | 1 7.69% 7.69% | 2 15.38% 23.08% | 3 23.08% 46.15% | 1 7.69% 53.85% | 1 7.69% 61.54% | 2 15.38% 76.92% | 3 23.08% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 13 +system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 3 25.00% 25.00% | 1 8.33% 33.33% | 1 8.33% 41.67% | 2 16.67% 58.33% | 3 25.00% 83.33% | 1 8.33% 91.67% | 1 8.33% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 12 +system.ruby.L1Cache_Controller.MM.L2_Replacement | 27474 12.55% 12.55% | 27503 12.56% 25.12% | 27234 12.44% 37.56% | 27411 12.52% 50.08% | 27197 12.42% 62.50% | 27115 12.39% 74.89% | 27402 12.52% 87.41% | 27565 12.59% 100.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement::total 218901 +system.ruby.L1Cache_Controller.MM.L1_to_L2 | 28221 12.57% 12.57% | 28176 12.55% 25.11% | 27986 12.46% 37.57% | 28104 12.51% 50.09% | 27921 12.43% 62.52% | 27848 12.40% 74.92% | 28097 12.51% 87.43% | 28234 12.57% 100.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2::total 224587 +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 21 10.24% 10.24% | 25 12.20% 22.44% | 30 14.63% 37.07% | 24 11.71% 48.78% | 22 10.73% 59.51% | 25 12.20% 71.71% | 28 13.66% 85.37% | 30 14.63% 100.00% system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 205 -system.ruby.L1Cache_Controller.MM.Other_GETX | 267 12.74% 12.74% | 270 12.88% 25.62% | 259 12.36% 37.98% | 265 12.64% 50.62% | 246 11.74% 62.36% | 255 12.17% 74.52% | 260 12.40% 86.93% | 274 13.07% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETX::total 2096 -system.ruby.L1Cache_Controller.MM.Other_GETS | 451 13.18% 13.18% | 418 12.22% 25.40% | 435 12.72% 38.12% | 419 12.25% 50.37% | 438 12.80% 63.17% | 394 11.52% 74.69% | 458 13.39% 88.07% | 408 11.93% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETS::total 3421 -system.ruby.L1Cache_Controller.MM.Merged_GETS | 47 13.31% 13.31% | 45 12.75% 26.06% | 44 12.46% 38.53% | 43 12.18% 50.71% | 42 11.90% 62.61% | 38 10.76% 73.37% | 48 13.60% 86.97% | 46 13.03% 100.00% -system.ruby.L1Cache_Controller.MM.Merged_GETS::total 353 -system.ruby.L1Cache_Controller.IR.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 2 33.33% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETX | 277 12.99% 12.99% | 248 11.63% 24.62% | 289 13.56% 38.18% | 251 11.77% 49.95% | 272 12.76% 62.71% | 302 14.17% 76.88% | 242 11.35% 88.23% | 251 11.77% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETX::total 2132 +system.ruby.L1Cache_Controller.MM.Other_GETS | 465 13.21% 13.21% | 422 11.99% 25.21% | 450 12.79% 37.99% | 437 12.42% 50.41% | 445 12.65% 63.06% | 445 12.65% 75.70% | 428 12.16% 87.87% | 427 12.13% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETS::total 3519 +system.ruby.L1Cache_Controller.MM.Merged_GETS | 42 14.00% 14.00% | 39 13.00% 27.00% | 41 13.67% 40.67% | 30 10.00% 50.67% | 40 13.33% 64.00% | 35 11.67% 75.67% | 40 13.33% 89.00% | 33 11.00% 100.00% +system.ruby.L1Cache_Controller.MM.Merged_GETS::total 300 +system.ruby.L1Cache_Controller.IR.Load | 1 16.67% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00% system.ruby.L1Cache_Controller.IR.Load::total 6 -system.ruby.L1Cache_Controller.IR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.IR.Store::total 2 -system.ruby.L1Cache_Controller.IR.L1_to_L2 | 7 35.00% 35.00% | 0 0.00% 35.00% | 1 5.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 12 60.00% 100.00% -system.ruby.L1Cache_Controller.IR.L1_to_L2::total 20 -system.ruby.L1Cache_Controller.SR.Load | 1 7.69% 7.69% | 1 7.69% 15.38% | 1 7.69% 23.08% | 4 30.77% 53.85% | 0 0.00% 53.85% | 1 7.69% 61.54% | 3 23.08% 84.62% | 2 15.38% 100.00% +system.ruby.L1Cache_Controller.IR.Store | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.IR.Store::total 3 +system.ruby.L1Cache_Controller.IR.L1_to_L2 | 1 8.33% 8.33% | 10 83.33% 91.67% | 0 0.00% 91.67% | 0 0.00% 91.67% | 0 0.00% 91.67% | 0 0.00% 91.67% | 0 0.00% 91.67% | 1 8.33% 100.00% +system.ruby.L1Cache_Controller.IR.L1_to_L2::total 12 +system.ruby.L1Cache_Controller.SR.Load | 3 23.08% 23.08% | 0 0.00% 23.08% | 0 0.00% 23.08% | 2 15.38% 38.46% | 2 15.38% 53.85% | 0 0.00% 53.85% | 3 23.08% 76.92% | 3 23.08% 100.00% system.ruby.L1Cache_Controller.SR.Load::total 13 -system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00% -system.ruby.L1Cache_Controller.SR.Store::total 5 -system.ruby.L1Cache_Controller.SR.L1_to_L2 | 11 21.57% 21.57% | 14 27.45% 49.02% | 0 0.00% 49.02% | 12 23.53% 72.55% | 0 0.00% 72.55% | 0 0.00% 72.55% | 9 17.65% 90.20% | 5 9.80% 100.00% -system.ruby.L1Cache_Controller.SR.L1_to_L2::total 51 -system.ruby.L1Cache_Controller.OR.Load | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.OR.Load::total 5 -system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 6 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OR.L1_to_L2::total 12 -system.ruby.L1Cache_Controller.MR.Load | 27 13.64% 13.64% | 21 10.61% 24.24% | 27 13.64% 37.88% | 27 13.64% 51.52% | 20 10.10% 61.62% | 23 11.62% 73.23% | 28 14.14% 87.37% | 25 12.63% 100.00% -system.ruby.L1Cache_Controller.MR.Load::total 198 -system.ruby.L1Cache_Controller.MR.Store | 16 14.29% 14.29% | 14 12.50% 26.79% | 4 3.57% 30.36% | 17 15.18% 45.54% | 15 13.39% 58.93% | 20 17.86% 76.79% | 14 12.50% 89.29% | 12 10.71% 100.00% -system.ruby.L1Cache_Controller.MR.Store::total 112 -system.ruby.L1Cache_Controller.MR.L1_to_L2 | 88 17.78% 17.78% | 39 7.88% 25.66% | 51 10.30% 35.96% | 88 17.78% 53.74% | 74 14.95% 68.69% | 39 7.88% 76.57% | 69 13.94% 90.51% | 47 9.49% 100.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2::total 495 -system.ruby.L1Cache_Controller.MMR.Load | 19 13.77% 13.77% | 13 9.42% 23.19% | 18 13.04% 36.23% | 20 14.49% 50.72% | 17 12.32% 63.04% | 13 9.42% 72.46% | 23 16.67% 89.13% | 15 10.87% 100.00% -system.ruby.L1Cache_Controller.MMR.Load::total 138 -system.ruby.L1Cache_Controller.MMR.Store | 8 11.94% 11.94% | 12 17.91% 29.85% | 6 8.96% 38.81% | 5 7.46% 46.27% | 9 13.43% 59.70% | 6 8.96% 68.66% | 10 14.93% 83.58% | 11 16.42% 100.00% -system.ruby.L1Cache_Controller.MMR.Store::total 67 -system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 77 18.55% 18.55% | 56 13.49% 32.05% | 70 16.87% 48.92% | 35 8.43% 57.35% | 58 13.98% 71.33% | 20 4.82% 76.14% | 76 18.31% 94.46% | 23 5.54% 100.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 415 -system.ruby.L1Cache_Controller.IM.L1_to_L2 | 278544 12.60% 12.60% | 277743 12.56% 25.16% | 280869 12.70% 37.86% | 272194 12.31% 50.17% | 276047 12.48% 62.65% | 276727 12.51% 75.16% | 274477 12.41% 87.57% | 274776 12.43% 100.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2211377 -system.ruby.L1Cache_Controller.IM.Other_GETX | 85 16.16% 16.16% | 58 11.03% 27.19% | 69 13.12% 40.30% | 47 8.94% 49.24% | 75 14.26% 63.50% | 70 13.31% 76.81% | 62 11.79% 88.59% | 60 11.41% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETX::total 526 -system.ruby.L1Cache_Controller.IM.Other_GETS | 106 11.79% 11.79% | 118 13.13% 24.92% | 113 12.57% 37.49% | 111 12.35% 49.83% | 103 11.46% 61.29% | 111 12.35% 73.64% | 119 13.24% 86.87% | 118 13.13% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETS::total 899 -system.ruby.L1Cache_Controller.IM.Ack | 136713 12.57% 12.57% | 135265 12.43% 25.00% | 137767 12.66% 37.67% | 133467 12.27% 49.94% | 136048 12.51% 62.44% | 136618 12.56% 75.00% | 135810 12.49% 87.49% | 136093 12.51% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1087781 -system.ruby.L1Cache_Controller.IM.Data | 1382 12.80% 12.80% | 1402 12.99% 25.79% | 1328 12.30% 38.10% | 1322 12.25% 50.34% | 1363 12.63% 62.97% | 1329 12.31% 75.28% | 1343 12.44% 87.72% | 1325 12.28% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 10794 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26543 12.47% 12.47% | 26483 12.44% 24.91% | 26903 12.64% 37.54% | 26188 12.30% 49.85% | 26745 12.56% 62.41% | 26801 12.59% 75.00% | 26521 12.46% 87.45% | 26709 12.55% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 212893 -system.ruby.L1Cache_Controller.SM.L1_to_L2 | 0 0.00% 0.00% | 6 18.18% 18.18% | 4 12.12% 30.30% | 7 21.21% 51.52% | 0 0.00% 51.52% | 0 0.00% 51.52% | 0 0.00% 51.52% | 16 48.48% 100.00% -system.ruby.L1Cache_Controller.SM.L1_to_L2::total 33 -system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 14 66.67% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 21 -system.ruby.L1Cache_Controller.SM.Data | 0 0.00% 0.00% | 1 16.67% 16.67% | 1 16.67% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 3 50.00% 100.00% -system.ruby.L1Cache_Controller.SM.Data::total 6 -system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1378 12.28% 12.28% | 1476 13.15% 25.43% | 1358 12.10% 37.52% | 1291 11.50% 49.02% | 1461 13.02% 62.04% | 1735 15.46% 77.50% | 1152 10.26% 87.76% | 1374 12.24% 100.00% -system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 11225 -system.ruby.L1Cache_Controller.ISM.Ack | 2968 12.36% 12.36% | 3074 12.80% 25.15% | 2971 12.37% 37.52% | 3107 12.93% 50.46% | 3108 12.94% 63.39% | 3097 12.89% 76.29% | 2854 11.88% 88.17% | 2842 11.83% 100.00% -system.ruby.L1Cache_Controller.ISM.Ack::total 24021 -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1382 12.80% 12.80% | 1403 12.99% 25.79% | 1329 12.31% 38.09% | 1323 12.25% 50.34% | 1363 12.62% 62.96% | 1329 12.31% 75.27% | 1343 12.44% 87.70% | 1328 12.30% 100.00% -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10800 -system.ruby.L1Cache_Controller.M_W.Load | 2 9.52% 9.52% | 6 28.57% 38.10% | 4 19.05% 57.14% | 1 4.76% 61.90% | 2 9.52% 71.43% | 3 14.29% 85.71% | 3 14.29% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 21 -system.ruby.L1Cache_Controller.M_W.Store | 2 14.29% 14.29% | 4 28.57% 42.86% | 1 7.14% 50.00% | 2 14.29% 64.29% | 1 7.14% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 14 -system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 74738 12.51% 12.51% | 76785 12.85% 25.37% | 73525 12.31% 37.68% | 73939 12.38% 50.05% | 74584 12.49% 62.54% | 74401 12.46% 75.00% | 74616 12.49% 87.49% | 74732 12.51% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 597320 -system.ruby.L1Cache_Controller.M_W.Ack | 98263 12.50% 12.50% | 98562 12.53% 25.03% | 97942 12.46% 37.49% | 98017 12.46% 49.95% | 97892 12.45% 62.40% | 97827 12.44% 74.84% | 98974 12.59% 87.43% | 98873 12.57% 100.00% -system.ruby.L1Cache_Controller.M_W.Ack::total 786350 -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47030 12.50% 12.50% | 47015 12.50% 25.00% | 46978 12.49% 37.49% | 47141 12.53% 50.02% | 47047 12.51% 62.53% | 46836 12.45% 74.98% | 46909 12.47% 87.45% | 47210 12.55% 100.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 376166 -system.ruby.L1Cache_Controller.MM_W.Load | 2 11.11% 11.11% | 4 22.22% 33.33% | 2 11.11% 44.44% | 1 5.56% 50.00% | 3 16.67% 66.67% | 4 22.22% 88.89% | 2 11.11% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 18 -system.ruby.L1Cache_Controller.MM_W.Store | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 1 14.29% 28.57% | 0 0.00% 28.57% | 2 28.57% 57.14% | 2 28.57% 85.71% | 1 14.29% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 7 -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 41839 12.37% 12.37% | 42308 12.51% 24.87% | 42669 12.61% 37.49% | 42131 12.45% 49.94% | 42574 12.59% 62.53% | 41857 12.37% 74.90% | 42636 12.60% 87.50% | 42269 12.50% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 338283 -system.ruby.L1Cache_Controller.MM_W.Ack | 54858 12.28% 12.28% | 55978 12.53% 24.81% | 55938 12.52% 37.33% | 55130 12.34% 49.66% | 56721 12.69% 62.36% | 56318 12.60% 74.96% | 55482 12.42% 87.38% | 56384 12.62% 100.00% -system.ruby.L1Cache_Controller.MM_W.Ack::total 446809 -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26545 12.47% 12.47% | 26487 12.44% 24.91% | 26904 12.64% 37.55% | 26190 12.30% 49.85% | 26746 12.56% 62.41% | 26802 12.59% 75.00% | 26524 12.46% 87.46% | 26709 12.54% 100.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 212907 -system.ruby.L1Cache_Controller.IS.L1_to_L2 | 496961 12.46% 12.46% | 496660 12.45% 24.91% | 494888 12.41% 37.32% | 501380 12.57% 49.89% | 498894 12.51% 62.39% | 497896 12.48% 74.88% | 500417 12.55% 87.42% | 501712 12.58% 100.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2::total 3988808 -system.ruby.L1Cache_Controller.IS.Other_GETX | 120 13.70% 13.70% | 102 11.64% 25.34% | 104 11.87% 37.21% | 122 13.93% 51.14% | 116 13.24% 64.38% | 92 10.50% 74.89% | 101 11.53% 86.42% | 119 13.58% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETX::total 876 -system.ruby.L1Cache_Controller.IS.Other_GETS | 212 13.16% 13.16% | 192 11.92% 25.08% | 219 13.59% 38.67% | 199 12.35% 51.02% | 188 11.67% 62.69% | 205 12.73% 75.42% | 205 12.73% 88.14% | 191 11.86% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETS::total 1611 -system.ruby.L1Cache_Controller.IS.Ack | 244322 12.52% 12.52% | 243435 12.47% 24.99% | 243945 12.50% 37.48% | 245096 12.56% 50.04% | 244536 12.53% 62.56% | 243639 12.48% 75.04% | 242664 12.43% 87.48% | 244497 12.52% 100.00% -system.ruby.L1Cache_Controller.IS.Ack::total 1952134 -system.ruby.L1Cache_Controller.IS.Shared_Ack | 37 12.63% 12.63% | 28 9.56% 22.18% | 26 8.87% 31.06% | 37 12.63% 43.69% | 35 11.95% 55.63% | 36 12.29% 67.92% | 48 16.38% 84.30% | 46 15.70% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Ack::total 293 -system.ruby.L1Cache_Controller.IS.Data | 2061 12.39% 12.39% | 2025 12.17% 24.56% | 2072 12.46% 37.02% | 2070 12.44% 49.46% | 2064 12.41% 61.87% | 2166 13.02% 74.89% | 2073 12.46% 87.36% | 2103 12.64% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 16634 -system.ruby.L1Cache_Controller.IS.Shared_Data | 1248 13.12% 13.12% | 1157 12.16% 25.28% | 1179 12.39% 37.67% | 1166 12.26% 49.93% | 1183 12.43% 62.36% | 1208 12.70% 75.06% | 1185 12.46% 87.51% | 1188 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Data::total 9514 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47032 12.50% 12.50% | 47019 12.50% 25.00% | 46979 12.49% 37.49% | 47143 12.53% 50.02% | 47049 12.51% 62.53% | 46839 12.45% 74.98% | 46912 12.47% 87.45% | 47210 12.55% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 376183 -system.ruby.L1Cache_Controller.SS.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.SS.Load::total 3 -system.ruby.L1Cache_Controller.SS.L1_to_L2 | 4693 11.36% 11.36% | 5086 12.31% 23.68% | 5364 12.99% 36.66% | 5399 13.07% 49.74% | 5426 13.14% 62.87% | 5212 12.62% 75.49% | 4958 12.00% 87.50% | 5163 12.50% 100.00% -system.ruby.L1Cache_Controller.SS.L1_to_L2::total 41301 -system.ruby.L1Cache_Controller.SS.Ack | 7229 12.46% 12.46% | 7039 12.13% 24.60% | 7385 12.73% 37.33% | 7059 12.17% 49.49% | 7124 12.28% 61.78% | 7435 12.82% 74.59% | 7092 12.23% 86.82% | 7647 13.18% 100.00% -system.ruby.L1Cache_Controller.SS.Ack::total 58010 -system.ruby.L1Cache_Controller.SS.Shared_Ack | 22 17.19% 17.19% | 10 7.81% 25.00% | 21 16.41% 41.41% | 20 15.62% 57.03% | 9 7.03% 64.06% | 16 12.50% 76.56% | 15 11.72% 88.28% | 15 11.72% 100.00% -system.ruby.L1Cache_Controller.SS.Shared_Ack::total 128 -system.ruby.L1Cache_Controller.SS.All_acks | 1299 13.13% 13.13% | 1192 12.05% 25.18% | 1222 12.35% 37.54% | 1212 12.25% 49.79% | 1221 12.34% 62.14% | 1259 12.73% 74.87% | 1245 12.59% 87.45% | 1241 12.55% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks::total 9891 -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2009 12.36% 12.36% | 1990 12.24% 24.60% | 2029 12.48% 37.08% | 2024 12.45% 49.54% | 2026 12.46% 62.00% | 2115 13.01% 75.01% | 2013 12.38% 87.39% | 2049 12.61% 100.00% +system.ruby.L1Cache_Controller.SR.Store | 1 14.29% 14.29% | 1 14.29% 28.57% | 2 28.57% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SR.Store::total 7 +system.ruby.L1Cache_Controller.SR.L1_to_L2 | 6 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 9 30.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 5 16.67% 66.67% | 10 33.33% 100.00% +system.ruby.L1Cache_Controller.SR.L1_to_L2::total 30 +system.ruby.L1Cache_Controller.OR.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.OR.Load::total 1 +system.ruby.L1Cache_Controller.OR.Store | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OR.Store::total 2 +system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% +system.ruby.L1Cache_Controller.OR.L1_to_L2::total 5 +system.ruby.L1Cache_Controller.MR.Load | 20 9.26% 9.26% | 23 10.65% 19.91% | 23 10.65% 30.56% | 33 15.28% 45.83% | 28 12.96% 58.80% | 26 12.04% 70.83% | 36 16.67% 87.50% | 27 12.50% 100.00% +system.ruby.L1Cache_Controller.MR.Load::total 216 +system.ruby.L1Cache_Controller.MR.Store | 12 9.76% 9.76% | 14 11.38% 21.14% | 14 11.38% 32.52% | 15 12.20% 44.72% | 15 12.20% 56.91% | 13 10.57% 67.48% | 17 13.82% 81.30% | 23 18.70% 100.00% +system.ruby.L1Cache_Controller.MR.Store::total 123 +system.ruby.L1Cache_Controller.MR.L1_to_L2 | 61 10.65% 10.65% | 80 13.96% 24.61% | 51 8.90% 33.51% | 40 6.98% 40.49% | 77 13.44% 53.93% | 68 11.87% 65.79% | 53 9.25% 75.04% | 143 24.96% 100.00% +system.ruby.L1Cache_Controller.MR.L1_to_L2::total 573 +system.ruby.L1Cache_Controller.MMR.Load | 14 10.77% 10.77% | 14 10.77% 21.54% | 19 14.62% 36.15% | 17 13.08% 49.23% | 10 7.69% 56.92% | 17 13.08% 70.00% | 21 16.15% 86.15% | 18 13.85% 100.00% +system.ruby.L1Cache_Controller.MMR.Load::total 130 +system.ruby.L1Cache_Controller.MMR.Store | 7 9.33% 9.33% | 11 14.67% 24.00% | 11 14.67% 38.67% | 7 9.33% 48.00% | 12 16.00% 64.00% | 8 10.67% 74.67% | 7 9.33% 84.00% | 12 16.00% 100.00% +system.ruby.L1Cache_Controller.MMR.Store::total 75 +system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 50 11.39% 11.39% | 56 12.76% 24.15% | 72 16.40% 40.55% | 41 9.34% 49.89% | 73 16.63% 66.51% | 45 10.25% 76.77% | 49 11.16% 87.93% | 53 12.07% 100.00% +system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 439 +system.ruby.L1Cache_Controller.IM.L1_to_L2 | 283520 12.65% 12.65% | 280559 12.52% 25.18% | 278577 12.43% 37.61% | 282969 12.63% 50.24% | 277805 12.40% 62.64% | 276768 12.35% 74.99% | 280123 12.50% 87.49% | 280175 12.51% 100.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2240496 +system.ruby.L1Cache_Controller.IM.Other_GETX | 69 13.75% 13.75% | 47 9.36% 23.11% | 73 14.54% 37.65% | 58 11.55% 49.20% | 71 14.14% 63.35% | 55 10.96% 74.30% | 74 14.74% 89.04% | 55 10.96% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETX::total 502 +system.ruby.L1Cache_Controller.IM.Other_GETS | 129 13.59% 13.59% | 118 12.43% 26.03% | 120 12.64% 38.67% | 118 12.43% 51.11% | 128 13.49% 64.59% | 136 14.33% 78.93% | 87 9.17% 88.09% | 113 11.91% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETS::total 949 +system.ruby.L1Cache_Controller.IM.Ack | 138770 12.59% 12.59% | 138200 12.54% 25.12% | 136999 12.43% 37.55% | 138460 12.56% 50.11% | 136866 12.42% 62.53% | 136573 12.39% 74.92% | 137631 12.48% 87.40% | 138894 12.60% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1102393 +system.ruby.L1Cache_Controller.IM.Data | 1307 12.02% 12.02% | 1378 12.67% 24.68% | 1329 12.22% 36.90% | 1405 12.92% 49.82% | 1332 12.24% 62.06% | 1346 12.37% 74.43% | 1347 12.38% 86.82% | 1434 13.18% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 10878 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26937 12.60% 12.60% | 26811 12.54% 25.14% | 26670 12.47% 37.61% | 26702 12.49% 50.10% | 26603 12.44% 62.54% | 26535 12.41% 74.95% | 26750 12.51% 87.46% | 26817 12.54% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 213825 +system.ruby.L1Cache_Controller.SM.L1_to_L2 | 6 9.38% 9.38% | 25 39.06% 48.44% | 5 7.81% 56.25% | 2 3.12% 59.38% | 0 0.00% 59.38% | 26 40.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.L1_to_L2::total 64 +system.ruby.L1Cache_Controller.SM.Ack | 1 2.33% 2.33% | 7 16.28% 18.60% | 14 32.56% 51.16% | 7 16.28% 67.44% | 0 0.00% 67.44% | 14 32.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 43 +system.ruby.L1Cache_Controller.SM.Data | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Data::total 8 +system.ruby.L1Cache_Controller.OM.Ack | 0 0.00% 0.00% | 7 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.Ack::total 14 +system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 2 +system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1168 10.71% 10.71% | 1389 12.74% 23.46% | 1158 10.62% 34.08% | 1445 13.26% 47.34% | 1501 13.77% 61.10% | 1257 11.53% 72.64% | 1603 14.71% 87.34% | 1380 12.66% 100.00% +system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 10901 +system.ruby.L1Cache_Controller.ISM.Ack | 2566 11.15% 11.15% | 3004 13.06% 24.21% | 2589 11.25% 35.46% | 2967 12.89% 48.35% | 2929 12.73% 61.08% | 2855 12.41% 73.49% | 3081 13.39% 86.88% | 3019 13.12% 100.00% +system.ruby.L1Cache_Controller.ISM.Ack::total 23010 +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1308 12.02% 12.02% | 1379 12.67% 24.68% | 1331 12.23% 36.91% | 1407 12.92% 49.83% | 1332 12.24% 62.07% | 1348 12.38% 74.45% | 1347 12.37% 86.83% | 1434 13.17% 100.00% +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10886 +system.ruby.L1Cache_Controller.M_W.Load | 6 21.43% 21.43% | 3 10.71% 32.14% | 4 14.29% 46.43% | 2 7.14% 53.57% | 3 10.71% 64.29% | 7 25.00% 89.29% | 1 3.57% 92.86% | 2 7.14% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 28 +system.ruby.L1Cache_Controller.M_W.Store | 2 11.76% 11.76% | 2 11.76% 23.53% | 3 17.65% 41.18% | 3 17.65% 58.82% | 3 17.65% 76.47% | 1 5.88% 82.35% | 1 5.88% 88.24% | 2 11.76% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 17 +system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 70208 12.27% 12.27% | 71483 12.50% 24.77% | 72279 12.64% 37.41% | 71279 12.46% 49.87% | 72276 12.64% 62.50% | 71468 12.49% 75.00% | 71747 12.54% 87.54% | 71273 12.46% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 572013 +system.ruby.L1Cache_Controller.M_W.Ack | 95563 12.35% 12.35% | 97187 12.56% 24.92% | 96343 12.45% 37.37% | 97412 12.59% 49.96% | 97834 12.65% 62.61% | 96623 12.49% 75.10% | 96494 12.47% 87.57% | 96142 12.43% 100.00% +system.ruby.L1Cache_Controller.M_W.Ack::total 773598 +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47143 12.43% 12.43% | 47339 12.49% 24.92% | 47513 12.53% 37.45% | 47388 12.50% 49.95% | 47640 12.56% 62.51% | 47564 12.54% 75.06% | 47183 12.44% 87.50% | 47397 12.50% 100.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 379167 +system.ruby.L1Cache_Controller.MM_W.Load | 1 14.29% 14.29% | 2 28.57% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 2 28.57% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 7 +system.ruby.L1Cache_Controller.MM_W.Store | 2 25.00% 25.00% | 0 0.00% 25.00% | 2 25.00% 50.00% | 0 0.00% 50.00% | 1 12.50% 62.50% | 2 25.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 8 +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 41379 12.65% 12.65% | 41221 12.60% 25.25% | 41051 12.55% 37.80% | 40535 12.39% 50.19% | 40742 12.46% 62.65% | 40472 12.37% 75.02% | 41502 12.69% 87.71% | 40195 12.29% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 327097 +system.ruby.L1Cache_Controller.MM_W.Ack | 55447 12.59% 12.59% | 55256 12.55% 25.14% | 55503 12.61% 37.75% | 54454 12.37% 50.12% | 54820 12.45% 62.57% | 54819 12.45% 75.02% | 55083 12.51% 87.53% | 54923 12.47% 100.00% +system.ruby.L1Cache_Controller.MM_W.Ack::total 440305 +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26939 12.60% 12.60% | 26813 12.54% 25.14% | 26673 12.47% 37.61% | 26704 12.49% 50.10% | 26606 12.44% 62.54% | 26536 12.41% 74.95% | 26751 12.51% 87.46% | 26819 12.54% 100.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 213841 +system.ruby.L1Cache_Controller.IS.L1_to_L2 | 499192 12.41% 12.41% | 505934 12.58% 24.99% | 504666 12.55% 37.54% | 500825 12.45% 49.99% | 503592 12.52% 62.51% | 505147 12.56% 75.07% | 502816 12.50% 87.58% | 499646 12.42% 100.00% +system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4021818 +system.ruby.L1Cache_Controller.IS.Other_GETX | 95 10.66% 10.66% | 120 13.47% 24.13% | 122 13.69% 37.82% | 108 12.12% 49.94% | 113 12.68% 62.63% | 103 11.56% 74.19% | 115 12.91% 87.09% | 115 12.91% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETX::total 891 +system.ruby.L1Cache_Controller.IS.Other_GETS | 217 12.73% 12.73% | 214 12.55% 25.28% | 221 12.96% 38.24% | 233 13.67% 51.91% | 238 13.96% 65.87% | 192 11.26% 77.13% | 183 10.73% 87.86% | 207 12.14% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETS::total 1705 +system.ruby.L1Cache_Controller.IS.Ack | 247332 12.45% 12.45% | 247416 12.45% 24.90% | 250036 12.58% 37.48% | 247568 12.46% 49.94% | 249322 12.55% 62.49% | 249531 12.56% 75.05% | 247241 12.44% 87.50% | 248455 12.50% 100.00% +system.ruby.L1Cache_Controller.IS.Ack::total 1986901 +system.ruby.L1Cache_Controller.IS.Shared_Ack | 33 11.07% 11.07% | 39 13.09% 24.16% | 44 14.77% 38.93% | 33 11.07% 50.00% | 37 12.42% 62.42% | 37 12.42% 74.83% | 31 10.40% 85.23% | 44 14.77% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Ack::total 298 +system.ruby.L1Cache_Controller.IS.Data | 2051 12.35% 12.35% | 2094 12.61% 24.96% | 2166 13.04% 38.00% | 2056 12.38% 50.38% | 2081 12.53% 62.91% | 2079 12.52% 75.43% | 2069 12.46% 87.89% | 2012 12.11% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 16608 +system.ruby.L1Cache_Controller.IS.Shared_Data | 1154 12.00% 12.00% | 1176 12.23% 24.23% | 1180 12.27% 36.51% | 1237 12.87% 49.37% | 1274 13.25% 62.62% | 1156 12.02% 74.64% | 1231 12.80% 87.45% | 1207 12.55% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Data::total 9615 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47145 12.43% 12.43% | 47341 12.48% 24.92% | 47517 12.53% 37.45% | 47392 12.50% 49.95% | 47643 12.56% 62.51% | 47565 12.54% 75.06% | 47184 12.44% 87.50% | 47399 12.50% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 379186 +system.ruby.L1Cache_Controller.SS.L1_to_L2 | 5412 13.03% 13.03% | 5439 13.09% 26.12% | 5189 12.49% 38.62% | 5322 12.81% 51.43% | 5271 12.69% 64.12% | 4898 11.79% 75.91% | 5046 12.15% 88.06% | 4958 11.94% 100.00% +system.ruby.L1Cache_Controller.SS.L1_to_L2::total 41535 +system.ruby.L1Cache_Controller.SS.Ack | 7196 12.49% 12.49% | 7279 12.63% 25.12% | 7138 12.39% 37.51% | 7289 12.65% 50.16% | 7368 12.79% 62.94% | 6992 12.13% 75.08% | 7164 12.43% 87.51% | 7198 12.49% 100.00% +system.ruby.L1Cache_Controller.SS.Ack::total 57624 +system.ruby.L1Cache_Controller.SS.Shared_Ack | 14 13.33% 13.33% | 21 20.00% 33.33% | 11 10.48% 43.81% | 10 9.52% 53.33% | 15 14.29% 67.62% | 7 6.67% 74.29% | 16 15.24% 89.52% | 11 10.48% 100.00% +system.ruby.L1Cache_Controller.SS.Shared_Ack::total 105 +system.ruby.L1Cache_Controller.SS.All_acks | 1194 11.98% 11.98% | 1225 12.29% 24.27% | 1234 12.38% 36.65% | 1275 12.79% 49.44% | 1320 13.24% 62.68% | 1193 11.97% 74.65% | 1269 12.73% 87.38% | 1258 12.62% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks::total 9968 +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2011 12.37% 12.37% | 2045 12.58% 24.95% | 2112 12.99% 37.95% | 2018 12.41% 50.36% | 2035 12.52% 62.88% | 2042 12.56% 75.44% | 2031 12.49% 87.94% | 1961 12.06% 100.00% system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16255 -system.ruby.L1Cache_Controller.OI.Other_GETX | 8 33.33% 33.33% | 5 20.83% 54.17% | 2 8.33% 62.50% | 2 8.33% 70.83% | 0 0.00% 70.83% | 2 8.33% 79.17% | 2 8.33% 87.50% | 3 12.50% 100.00% +system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Load::total 1 +system.ruby.L1Cache_Controller.OI.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Store::total 1 +system.ruby.L1Cache_Controller.OI.Other_GETX | 4 16.67% 16.67% | 1 4.17% 20.83% | 3 12.50% 33.33% | 2 8.33% 41.67% | 3 12.50% 54.17% | 1 4.17% 58.33% | 2 8.33% 66.67% | 8 33.33% 100.00% system.ruby.L1Cache_Controller.OI.Other_GETX::total 24 -system.ruby.L1Cache_Controller.OI.Other_GETS | 2 9.52% 9.52% | 4 19.05% 28.57% | 2 9.52% 38.10% | 3 14.29% 52.38% | 2 9.52% 61.90% | 2 9.52% 71.43% | 1 4.76% 76.19% | 5 23.81% 100.00% -system.ruby.L1Cache_Controller.OI.Other_GETS::total 21 -system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 17.39% 17.39% | 1 4.35% 21.74% | 2 8.70% 30.43% | 4 17.39% 47.83% | 8 34.78% 82.61% | 2 8.70% 91.30% | 0 0.00% 91.30% | 2 8.70% 100.00% -system.ruby.L1Cache_Controller.OI.Merged_GETS::total 23 -system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1185 12.71% 12.71% | 1110 11.90% 24.61% | 1162 12.46% 37.08% | 1206 12.93% 50.01% | 1193 12.79% 62.81% | 1169 12.54% 75.34% | 1142 12.25% 87.59% | 1157 12.41% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9324 -system.ruby.L1Cache_Controller.MI.Load | 12 10.34% 10.34% | 9 7.76% 18.10% | 21 18.10% 36.21% | 10 8.62% 44.83% | 14 12.07% 56.90% | 18 15.52% 72.41% | 19 16.38% 88.79% | 13 11.21% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 116 -system.ruby.L1Cache_Controller.MI.Store | 11 17.19% 17.19% | 11 17.19% 34.38% | 8 12.50% 46.88% | 8 12.50% 59.38% | 5 7.81% 67.19% | 9 14.06% 81.25% | 5 7.81% 89.06% | 7 10.94% 100.00% -system.ruby.L1Cache_Controller.MI.Store::total 64 -system.ruby.L1Cache_Controller.MI.Other_GETX | 176 11.77% 11.77% | 195 13.04% 24.82% | 189 12.64% 37.46% | 191 12.78% 50.23% | 181 12.11% 62.34% | 171 11.44% 73.78% | 176 11.77% 85.55% | 216 14.45% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETX::total 1495 -system.ruby.L1Cache_Controller.MI.Other_GETS | 319 12.65% 12.65% | 292 11.58% 24.24% | 293 11.62% 35.86% | 325 12.89% 48.75% | 347 13.76% 62.51% | 337 13.37% 75.88% | 323 12.81% 88.69% | 285 11.31% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETS::total 2521 -system.ruby.L1Cache_Controller.MI.Merged_GETS | 21 15.91% 15.91% | 18 13.64% 29.55% | 10 7.58% 37.12% | 23 17.42% 54.55% | 10 7.58% 62.12% | 8 6.06% 68.18% | 19 14.39% 82.58% | 23 17.42% 100.00% -system.ruby.L1Cache_Controller.MI.Merged_GETS::total 132 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72372 12.48% 12.48% | 72427 12.49% 24.98% | 72692 12.54% 37.52% | 72109 12.44% 49.95% | 72644 12.53% 62.48% | 72502 12.51% 74.99% | 72242 12.46% 87.45% | 72752 12.55% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 579740 -system.ruby.L1Cache_Controller.II.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Load::total 2 -system.ruby.L1Cache_Controller.II.Other_GETX | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETS | 5 26.32% 26.32% | 2 10.53% 36.84% | 2 10.53% 47.37% | 5 26.32% 73.68% | 1 5.26% 78.95% | 0 0.00% 78.95% | 1 5.26% 84.21% | 3 15.79% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETS::total 19 +system.ruby.L1Cache_Controller.OI.Merged_GETS | 2 8.33% 8.33% | 1 4.17% 12.50% | 2 8.33% 20.83% | 4 16.67% 37.50% | 5 20.83% 58.33% | 2 8.33% 66.67% | 5 20.83% 87.50% | 3 12.50% 100.00% +system.ruby.L1Cache_Controller.OI.Merged_GETS::total 24 +system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1223 12.96% 12.96% | 1193 12.64% 25.60% | 1191 12.62% 38.22% | 1164 12.33% 50.56% | 1166 12.36% 62.91% | 1162 12.31% 75.23% | 1200 12.72% 87.94% | 1138 12.06% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9437 +system.ruby.L1Cache_Controller.MI.Load | 5 4.63% 4.63% | 17 15.74% 20.37% | 12 11.11% 31.48% | 18 16.67% 48.15% | 16 14.81% 62.96% | 15 13.89% 76.85% | 8 7.41% 84.26% | 17 15.74% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 108 +system.ruby.L1Cache_Controller.MI.Store | 6 10.17% 10.17% | 8 13.56% 23.73% | 5 8.47% 32.20% | 4 6.78% 38.98% | 6 10.17% 49.15% | 10 16.95% 66.10% | 10 16.95% 83.05% | 10 16.95% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 59 +system.ruby.L1Cache_Controller.MI.Other_GETX | 190 12.89% 12.89% | 176 11.94% 24.83% | 172 11.67% 36.50% | 189 12.82% 49.32% | 186 12.62% 61.94% | 177 12.01% 73.95% | 182 12.35% 86.30% | 202 13.70% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETX::total 1474 +system.ruby.L1Cache_Controller.MI.Other_GETS | 318 12.53% 12.53% | 328 12.92% 25.45% | 315 12.41% 37.86% | 276 10.87% 48.74% | 322 12.69% 61.43% | 314 12.37% 73.80% | 348 13.71% 87.51% | 317 12.49% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETS::total 2538 +system.ruby.L1Cache_Controller.MI.Merged_GETS | 11 7.86% 7.86% | 11 7.86% 15.71% | 18 12.86% 28.57% | 19 13.57% 42.14% | 24 17.14% 59.29% | 32 22.86% 82.14% | 8 5.71% 87.86% | 17 12.14% 100.00% +system.ruby.L1Cache_Controller.MI.Merged_GETS::total 140 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72753 12.47% 12.47% | 73034 12.52% 24.98% | 72926 12.50% 37.48% | 72986 12.51% 49.99% | 73002 12.51% 62.50% | 72918 12.50% 74.99% | 72767 12.47% 87.46% | 73153 12.54% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 583539 +system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.II.Other_GETX::total 2 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 184 12.12% 12.12% | 199 13.11% 25.23% | 191 12.58% 37.81% | 193 12.71% 50.53% | 181 11.92% 62.45% | 173 11.40% 73.85% | 178 11.73% 85.57% | 219 14.43% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1518 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1 -system.ruby.L1Cache_Controller.IT.Load | 1 25.00% 25.00% | 0 0.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IT.Load::total 4 -system.ruby.L1Cache_Controller.IT.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.L1Cache_Controller.IT.Store::total 2 -system.ruby.L1Cache_Controller.IT.L1_to_L2 | 7 35.00% 35.00% | 0 0.00% 35.00% | 1 5.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 12 60.00% 100.00% -system.ruby.L1Cache_Controller.IT.L1_to_L2::total 20 -system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 0 0.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% -system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total 8 -system.ruby.L1Cache_Controller.ST.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 3 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.II.Other_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.II.Other_GETS::total 1 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 194 12.96% 12.96% | 177 11.82% 24.78% | 175 11.69% 36.47% | 191 12.76% 49.23% | 189 12.63% 61.86% | 178 11.89% 73.75% | 184 12.29% 86.04% | 209 13.96% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1497 +system.ruby.L1Cache_Controller.IT.Load | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IT.Load::total 3 +system.ruby.L1Cache_Controller.IT.Store | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IT.Store::total 1 +system.ruby.L1Cache_Controller.IT.L1_to_L2 | 1 3.57% 3.57% | 10 35.71% 39.29% | 0 0.00% 39.29% | 0 0.00% 39.29% | 6 21.43% 60.71% | 3 10.71% 71.43% | 0 0.00% 71.43% | 8 28.57% 100.00% +system.ruby.L1Cache_Controller.IT.L1_to_L2::total 28 +system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 1 11.11% 11.11% | 1 11.11% 22.22% | 1 11.11% 33.33% | 0 0.00% 33.33% | 2 22.22% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total 9 +system.ruby.L1Cache_Controller.ST.Load | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 33.33% 66.67% | 2 33.33% 100.00% system.ruby.L1Cache_Controller.ST.Load::total 6 -system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 3 75.00% 100.00% -system.ruby.L1Cache_Controller.ST.Store::total 4 -system.ruby.L1Cache_Controller.ST.L1_to_L2 | 11 10.89% 10.89% | 14 13.86% 24.75% | 8 7.92% 32.67% | 12 11.88% 44.55% | 0 0.00% 44.55% | 0 0.00% 44.55% | 9 8.91% 53.47% | 47 46.53% 100.00% -system.ruby.L1Cache_Controller.ST.L1_to_L2::total 101 -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 1 5.56% 5.56% | 2 11.11% 16.67% | 1 5.56% 22.22% | 5 27.78% 50.00% | 0 0.00% 50.00% | 1 5.56% 55.56% | 3 16.67% 72.22% | 5 27.78% 100.00% -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 18 -system.ruby.L1Cache_Controller.OT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.OT.Load::total 3 -system.ruby.L1Cache_Controller.OT.L1_to_L2 | 3 20.00% 20.00% | 0 0.00% 20.00% | 6 40.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 6 40.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OT.L1_to_L2::total 15 -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 5 -system.ruby.L1Cache_Controller.MT.Load | 15 16.85% 16.85% | 10 11.24% 28.09% | 12 13.48% 41.57% | 11 12.36% 53.93% | 11 12.36% 66.29% | 9 10.11% 76.40% | 13 14.61% 91.01% | 8 8.99% 100.00% -system.ruby.L1Cache_Controller.MT.Load::total 89 -system.ruby.L1Cache_Controller.MT.Store | 7 15.91% 15.91% | 5 11.36% 27.27% | 1 2.27% 29.55% | 8 18.18% 47.73% | 9 20.45% 68.18% | 4 9.09% 77.27% | 5 11.36% 88.64% | 5 11.36% 100.00% -system.ruby.L1Cache_Controller.MT.Store::total 44 -system.ruby.L1Cache_Controller.MT.L1_to_L2 | 153 13.17% 13.17% | 95 8.18% 21.34% | 101 8.69% 30.03% | 171 14.72% 44.75% | 156 13.43% 58.18% | 158 13.60% 71.77% | 214 18.42% 90.19% | 114 9.81% 100.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1162 -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 43 13.87% 13.87% | 35 11.29% 25.16% | 31 10.00% 35.16% | 44 14.19% 49.35% | 35 11.29% 60.65% | 43 13.87% 74.52% | 42 13.55% 88.06% | 37 11.94% 100.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 310 -system.ruby.L1Cache_Controller.MMT.Load | 10 13.89% 13.89% | 8 11.11% 25.00% | 10 13.89% 38.89% | 8 11.11% 50.00% | 9 12.50% 62.50% | 6 8.33% 70.83% | 13 18.06% 88.89% | 8 11.11% 100.00% -system.ruby.L1Cache_Controller.MMT.Load::total 72 -system.ruby.L1Cache_Controller.MMT.Store | 5 14.71% 14.71% | 6 17.65% 32.35% | 4 11.76% 44.12% | 3 8.82% 52.94% | 3 8.82% 61.76% | 6 17.65% 79.41% | 3 8.82% 88.24% | 4 11.76% 100.00% -system.ruby.L1Cache_Controller.MMT.Store::total 34 -system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 91 12.59% 12.59% | 71 9.82% 22.41% | 96 13.28% 35.68% | 73 10.10% 45.78% | 114 15.77% 61.55% | 32 4.43% 65.98% | 176 24.34% 90.32% | 70 9.68% 100.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 723 -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 27 13.17% 13.17% | 25 12.20% 25.37% | 24 11.71% 37.07% | 25 12.20% 49.27% | 26 12.68% 61.95% | 19 9.27% 71.22% | 33 16.10% 87.32% | 26 12.68% 100.00% +system.ruby.L1Cache_Controller.ST.Store | 1 16.67% 16.67% | 0 0.00% 16.67% | 3 50.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.Store::total 6 +system.ruby.L1Cache_Controller.ST.L1_to_L2 | 10 14.29% 14.29% | 7 10.00% 24.29% | 0 0.00% 24.29% | 9 12.86% 37.14% | 1 1.43% 38.57% | 9 12.86% 51.43% | 3 4.29% 55.71% | 31 44.29% 100.00% +system.ruby.L1Cache_Controller.ST.L1_to_L2::total 70 +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 4 20.00% 20.00% | 1 5.00% 25.00% | 2 10.00% 35.00% | 3 15.00% 50.00% | 2 10.00% 60.00% | 2 10.00% 70.00% | 3 15.00% 85.00% | 3 15.00% 100.00% +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 20 +system.ruby.L1Cache_Controller.OT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.OT.Load::total 1 +system.ruby.L1Cache_Controller.OT.Store | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OT.Store::total 1 +system.ruby.L1Cache_Controller.OT.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% +system.ruby.L1Cache_Controller.OT.L1_to_L2::total 5 +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 3 +system.ruby.L1Cache_Controller.MT.Load | 9 7.89% 7.89% | 19 16.67% 24.56% | 15 13.16% 37.72% | 15 13.16% 50.88% | 17 14.91% 65.79% | 12 10.53% 76.32% | 13 11.40% 87.72% | 14 12.28% 100.00% +system.ruby.L1Cache_Controller.MT.Load::total 114 +system.ruby.L1Cache_Controller.MT.Store | 6 12.00% 12.00% | 6 12.00% 24.00% | 4 8.00% 32.00% | 4 8.00% 40.00% | 6 12.00% 52.00% | 5 10.00% 62.00% | 5 10.00% 72.00% | 14 28.00% 100.00% +system.ruby.L1Cache_Controller.MT.Store::total 50 +system.ruby.L1Cache_Controller.MT.L1_to_L2 | 121 10.82% 10.82% | 141 12.61% 23.43% | 82 7.33% 30.77% | 189 16.91% 47.67% | 135 12.08% 59.75% | 120 10.73% 70.48% | 127 11.36% 81.84% | 203 18.16% 100.00% +system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1118 +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 32 9.44% 9.44% | 37 10.91% 20.35% | 37 10.91% 31.27% | 48 14.16% 45.43% | 43 12.68% 58.11% | 39 11.50% 69.62% | 53 15.63% 85.25% | 50 14.75% 100.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 339 +system.ruby.L1Cache_Controller.MMT.Load | 8 13.11% 13.11% | 6 9.84% 22.95% | 9 14.75% 37.70% | 8 13.11% 50.82% | 8 13.11% 63.93% | 7 11.48% 75.41% | 10 16.39% 91.80% | 5 8.20% 100.00% +system.ruby.L1Cache_Controller.MMT.Load::total 61 +system.ruby.L1Cache_Controller.MMT.Store | 3 7.32% 7.32% | 6 14.63% 21.95% | 5 12.20% 34.15% | 6 14.63% 48.78% | 8 19.51% 68.29% | 5 12.20% 80.49% | 4 9.76% 90.24% | 4 9.76% 100.00% +system.ruby.L1Cache_Controller.MMT.Store::total 41 +system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 57 6.88% 6.88% | 68 8.21% 15.10% | 131 15.82% 30.92% | 77 9.30% 40.22% | 145 17.51% 57.73% | 87 10.51% 68.24% | 167 20.17% 88.41% | 96 11.59% 100.00% +system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 828 +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 21 10.24% 10.24% | 25 12.20% 22.44% | 30 14.63% 37.07% | 24 11.71% 48.78% | 22 10.73% 59.51% | 25 12.20% 71.71% | 28 13.66% 85.37% | 30 14.63% 100.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 205 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index a573d3fa4..118b5390e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007555 # Number of seconds simulated -sim_ticks 7555268 # Number of ticks simulated -final_tick 7555268 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007664 # Number of seconds simulated +sim_ticks 7663697 # Number of ticks simulated +final_tick 7663697 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 300368 # Simulator tick rate (ticks/s) -host_mem_usage 516584 # Number of bytes of host memory used -host_seconds 25.15 # Real time elapsed on the host +host_tick_rate 221013 # Simulator tick rate (ticks/s) +host_mem_usage 570240 # Number of bytes of host memory used +host_seconds 34.68 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39518912 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39518912 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39517888 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 39517888 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 617483 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 617483 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 617467 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 617467 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 5230643307 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 5230643307 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 5230507773 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 5230507773 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 10461151080 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 10461151080 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 617498 # Number of read requests accepted -system.mem_ctrls.writeReqs 617467 # Number of write requests accepted -system.mem_ctrls.readBursts 617498 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 617467 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 38662976 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 856576 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 39021568 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39519872 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 39517888 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 13384 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 7703 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39606720 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39606720 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39605504 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 39605504 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 618855 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 618855 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 618836 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 618836 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 5168095764 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 5168095764 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 5167937094 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 5167937094 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 10336032857 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 10336032857 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 618867 # Number of read requests accepted +system.mem_ctrls.writeReqs 618836 # Number of write requests accepted +system.mem_ctrls.readBursts 618867 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 618836 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38729152 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 877568 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 39100032 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39607488 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 39605504 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 13712 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 7842 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 75345 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 75630 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 75779 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 75335 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 74961 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 75413 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76010 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 75636 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76101 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 75669 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 75586 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 75582 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 75688 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 75150 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 75932 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 75435 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 76025 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 76356 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 76461 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 76035 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 75665 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 76133 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 76696 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 76341 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 76815 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 76432 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 76283 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 76308 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 76418 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 75865 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 76657 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 76160 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,53 +68,53 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 1313 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 7555254 # Total gap between requests +system.mem_ctrls.numWrRetry 1565 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 7663682 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 617498 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 618867 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 617467 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 27 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 395 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 1547 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 4803 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 10732 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 19329 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 29926 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 39736 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 47332 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 51238 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 49822 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 45328 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 39038 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 34104 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 29932 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 27412 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 25532 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 24223 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 23465 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 22388 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 20868 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 18295 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 14861 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 10803 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 6963 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 3724 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 1587 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 536 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 146 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 19 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 3 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 618836 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 17 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 261 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1039 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 3286 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7979 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 15656 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 25778 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 37228 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 46409 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 53585 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 54448 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 51035 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 44560 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 37792 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 31846 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 28053 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 25672 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 23930 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 22890 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 21644 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 19735 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 17142 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 13645 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 9856 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 6202 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 3287 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 1464 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 529 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 152 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 30 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 5 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see @@ -147,511 +147,511 @@ system.mem_ctrls.wrQLenPdf::27 1 # Wh system.mem_ctrls.wrQLenPdf::28 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 72 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 237 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 615 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 1345 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 2774 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 4991 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 7821 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 10763 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 14754 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 18194 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 20672 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 23139 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 24969 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 25977 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 27541 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 28269 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 29583 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 30968 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 32545 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 33941 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 33783 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 34127 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 36711 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 56250 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 47740 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 20435 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 15303 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 10488 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 7108 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 4178 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 1989 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 2445 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 244165 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 318.158098 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 243.329803 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 225.133894 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 33053 13.54% 13.54% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 74498 30.51% 44.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 47835 19.59% 63.64% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 35613 14.59% 78.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 24095 9.87% 88.09% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 14293 5.85% 93.95% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7627 3.12% 97.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3851 1.58% 98.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 3300 1.35% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 244165 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 38107 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.852311 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 8.829731 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 11.389209 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-3 12433 32.63% 32.63% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::4-7 1821 4.78% 37.41% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-11 458 1.20% 38.61% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-15 176 0.46% 39.07% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-19 3225 8.46% 47.53% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-23 7120 18.68% 66.22% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-27 6436 16.89% 83.11% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::28-31 5233 13.73% 96.84% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-35 1168 3.07% 99.90% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-39 36 0.09% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.wrQLenPdf::31 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 123 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 305 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 824 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 1781 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 3229 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 4948 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 8209 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 11908 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 15017 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 18231 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 20205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 21771 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 23468 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 24901 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 25709 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 26816 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 28040 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 29869 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 32691 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 34751 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 37242 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 41772 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 66357 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 58736 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 24195 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 18322 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 13247 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 8126 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 4786 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 2460 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 2871 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 245598 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 316.887532 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 240.845849 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 227.054939 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 34539 14.06% 14.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 75522 30.75% 44.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 47012 19.14% 63.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 34656 14.11% 78.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 24109 9.82% 87.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14722 5.99% 93.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7733 3.15% 97.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3901 1.59% 98.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 3404 1.39% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 245598 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 38184 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.848078 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 8.302353 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 11.863449 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-3 13558 35.51% 35.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::4-7 1227 3.21% 38.72% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-11 321 0.84% 39.56% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-15 186 0.49% 40.05% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-19 3091 8.10% 48.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-23 6038 15.81% 63.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-27 5831 15.27% 79.23% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::28-31 6271 16.42% 95.65% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-35 1620 4.24% 99.89% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-39 40 0.10% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::80-83 1 0.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 38107 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 38107 # Writes before turning the bus around for reads +system.mem_ctrls.rdPerTurnAround::total 38184 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 38183 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 38107 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 38107 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 111252820 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 122730891 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3020545 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 184.16 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::16 38183 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 38183 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 114251031 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 125748748 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3025715 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 188.80 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 203.16 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 5117.35 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 5164.82 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 5230.77 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 5230.51 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 207.80 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 5053.59 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 5101.98 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 5168.20 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 5167.94 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 80.33 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 39.98 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 40.35 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 18.19 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 53.14 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 369680 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 599969 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 61.19 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 98.39 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 6.12 # Average gap between requests -system.mem_ctrls.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1845214560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 1025119200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7536484800 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 6319337472 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 493303200 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 5147480988 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 16294800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 22383235020 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 2963.601171 # Core power per rank (mW) +system.mem_ctrls.busUtil 79.34 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 39.48 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 39.86 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 18.24 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 53.79 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 369216 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 601261 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 61.01 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 98.41 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 6.19 # Average gap between requests +system.mem_ctrls.pageHitRate 79.80 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1856244600 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1031247000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7550137920 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6332442624 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 500423040 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5221769544 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 16530000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 22508794728 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2937.826817 # Core power per rank (mW) system.mem_ctrls_0.memoryStateTime::IDLE 12 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 252200 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 255840 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 7300517 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7405878 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 493303200 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 163216080 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 4388427600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 5044946880 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.969017 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 7300480 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 252200 # Time in different power states +system.mem_ctrls_1.refreshEnergy 500423040 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 165571776 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4451763600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 5117758416 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.969048 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7405844 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 255840 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 1 # Clock period in ticks -system.cpu0.num_reads 98710 # number of read accesses completed -system.cpu0.num_writes 55193 # number of write accesses completed -system.cpu1.num_reads 99197 # number of read accesses completed -system.cpu1.num_writes 54876 # number of write accesses completed -system.cpu2.num_reads 99807 # number of read accesses completed -system.cpu2.num_writes 55097 # number of write accesses completed -system.cpu3.num_reads 99629 # number of read accesses completed -system.cpu3.num_writes 55678 # number of write accesses completed -system.cpu4.num_reads 99475 # number of read accesses completed -system.cpu4.num_writes 55578 # number of write accesses completed -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 55526 # number of write accesses completed -system.cpu6.num_reads 99558 # number of read accesses completed -system.cpu6.num_writes 55241 # number of write accesses completed -system.cpu7.num_reads 99313 # number of read accesses completed -system.cpu7.num_writes 55346 # number of write accesses completed +system.cpu0.num_reads 99096 # number of read accesses completed +system.cpu0.num_writes 55531 # number of write accesses completed +system.cpu1.num_reads 99775 # number of read accesses completed +system.cpu1.num_writes 55445 # number of write accesses completed +system.cpu2.num_reads 99195 # number of read accesses completed +system.cpu2.num_writes 55707 # number of write accesses completed +system.cpu3.num_reads 99465 # number of read accesses completed +system.cpu3.num_writes 55386 # number of write accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 55371 # number of write accesses completed +system.cpu5.num_reads 99596 # number of read accesses completed +system.cpu5.num_writes 55348 # number of write accesses completed +system.cpu6.num_reads 99601 # number of read accesses completed +system.cpu6.num_writes 55337 # number of write accesses completed +system.cpu7.num_reads 99679 # number of read accesses completed +system.cpu7.num_writes 55088 # number of write accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 32 # delay histogram for all message system.ruby.delayHist::max_bucket 319 # delay histogram for all message -system.ruby.delayHist::samples 1255488 # delay histogram for all message -system.ruby.delayHist::mean 2.169527 # delay histogram for all message -system.ruby.delayHist::stdev 7.600459 # delay histogram for all message -system.ruby.delayHist | 1238674 98.66% 98.66% | 10648 0.85% 99.51% | 5547 0.44% 99.95% | 516 0.04% 99.99% | 82 0.01% 100.00% | 21 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1255488 # delay histogram for all message +system.ruby.delayHist::samples 1258206 # delay histogram for all message +system.ruby.delayHist::mean 2.294932 # delay histogram for all message +system.ruby.delayHist::stdev 7.756260 # delay histogram for all message +system.ruby.delayHist | 1240255 98.57% 98.57% | 11748 0.93% 99.51% | 5468 0.43% 99.94% | 595 0.05% 99.99% | 125 0.01% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1258206 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 625936 +system.ruby.outstanding_req_hist::samples 627344 system.ruby.outstanding_req_hist::mean 15.998449 -system.ruby.outstanding_req_hist::gmean 15.997183 -system.ruby.outstanding_req_hist::stdev 0.125950 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 27 0.00% 0.02% | 625805 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 625936 +system.ruby.outstanding_req_hist::gmean 15.997186 +system.ruby.outstanding_req_hist::stdev 0.125821 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 29 0.00% 0.02% | 627211 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 627344 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 625808 -system.ruby.latency_hist::mean 1545.142387 -system.ruby.latency_hist::gmean 1522.552701 -system.ruby.latency_hist::stdev 264.347793 -system.ruby.latency_hist | 80 0.01% 0.01% | 8131 1.30% 1.31% | 315699 50.45% 51.76% | 277984 44.42% 96.18% | 23716 3.79% 99.97% | 198 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 625808 +system.ruby.latency_hist::samples 627216 +system.ruby.latency_hist::mean 1563.828817 +system.ruby.latency_hist::gmean 1541.754061 +system.ruby.latency_hist::stdev 262.502843 +system.ruby.latency_hist | 74 0.01% 0.01% | 6345 1.01% 1.02% | 297362 47.41% 48.43% | 296923 47.34% 95.77% | 26326 4.20% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 627216 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 625808 -system.ruby.miss_latency_hist::mean 1545.142387 -system.ruby.miss_latency_hist::gmean 1522.552701 -system.ruby.miss_latency_hist::stdev 264.347793 -system.ruby.miss_latency_hist | 80 0.01% 0.01% | 8131 1.30% 1.31% | 315699 50.45% 51.76% | 277984 44.42% 96.18% | 23716 3.79% 99.97% | 198 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 625808 -system.ruby.L1Cache.incomplete_times 8330 -system.ruby.Directory.incomplete_times 617475 +system.ruby.miss_latency_hist::samples 627216 +system.ruby.miss_latency_hist::mean 1563.828817 +system.ruby.miss_latency_hist::gmean 1541.754061 +system.ruby.miss_latency_hist::stdev 262.502843 +system.ruby.miss_latency_hist | 74 0.01% 0.01% | 6345 1.01% 1.02% | 297362 47.41% 48.43% | 296923 47.34% 95.77% | 26326 4.20% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 627216 +system.ruby.L1Cache.incomplete_times 8365 +system.ruby.Directory.incomplete_times 618848 system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 78125 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78125 # Number of cache demand accesses +system.ruby.l1_cntrl0.cacheMemory.demand_misses 78375 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78375 # Number of cache demand accesses system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.cacheMemory.demand_misses 78092 # Number of cache demand misses -system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78092 # Number of cache demand accesses +system.ruby.l1_cntrl1.cacheMemory.demand_misses 78728 # Number of cache demand misses +system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78728 # Number of cache demand accesses system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.cacheMemory.demand_misses 78168 # Number of cache demand misses -system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78168 # Number of cache demand accesses +system.ruby.l1_cntrl2.cacheMemory.demand_misses 78427 # Number of cache demand misses +system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78427 # Number of cache demand accesses system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.cacheMemory.demand_misses 78501 # Number of cache demand misses -system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78501 # Number of cache demand accesses +system.ruby.l1_cntrl3.cacheMemory.demand_misses 78400 # Number of cache demand misses +system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78400 # Number of cache demand accesses system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.cacheMemory.demand_misses 78224 # Number of cache demand misses -system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78224 # Number of cache demand accesses +system.ruby.l1_cntrl4.cacheMemory.demand_misses 78248 # Number of cache demand misses +system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78248 # Number of cache demand accesses system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.cacheMemory.demand_misses 78367 # Number of cache demand misses -system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78367 # Number of cache demand accesses +system.ruby.l1_cntrl5.cacheMemory.demand_misses 78372 # Number of cache demand misses +system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78372 # Number of cache demand accesses system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.cacheMemory.demand_misses 78095 # Number of cache demand misses -system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78095 # Number of cache demand accesses +system.ruby.l1_cntrl6.cacheMemory.demand_misses 78413 # Number of cache demand misses +system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78413 # Number of cache demand accesses system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.cacheMemory.demand_misses 78258 # Number of cache demand misses -system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78258 # Number of cache demand accesses +system.ruby.l1_cntrl7.cacheMemory.demand_misses 78273 # Number of cache demand misses +system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78273 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 5.185365 -system.ruby.network.routers0.msg_count.Control::2 78125 -system.ruby.network.routers0.msg_count.Data::2 77570 -system.ruby.network.routers0.msg_count.Response_Data::4 79137 -system.ruby.network.routers0.msg_count.Writeback_Control::3 78585 -system.ruby.network.routers0.msg_bytes.Control::2 625000 -system.ruby.network.routers0.msg_bytes.Data::2 5585040 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5697864 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 628680 -system.ruby.network.routers1.percent_links_utilized 5.183506 -system.ruby.network.routers1.msg_count.Control::2 78092 -system.ruby.network.routers1.msg_count.Data::2 77517 -system.ruby.network.routers1.msg_count.Response_Data::4 79134 -system.ruby.network.routers1.msg_count.Writeback_Control::3 78560 -system.ruby.network.routers1.msg_bytes.Control::2 624736 -system.ruby.network.routers1.msg_bytes.Data::2 5581224 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5697648 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 628480 -system.ruby.network.routers2.percent_links_utilized 5.188578 -system.ruby.network.routers2.msg_count.Control::2 78168 -system.ruby.network.routers2.msg_count.Data::2 77620 -system.ruby.network.routers2.msg_count.Response_Data::4 79184 -system.ruby.network.routers2.msg_count.Writeback_Control::3 78640 -system.ruby.network.routers2.msg_bytes.Control::2 625344 -system.ruby.network.routers2.msg_bytes.Data::2 5588640 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5701248 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 629120 -system.ruby.network.routers3.percent_links_utilized 5.211370 -system.ruby.network.routers3.msg_count.Control::2 78501 -system.ruby.network.routers3.msg_count.Data::2 77919 -system.ruby.network.routers3.msg_count.Response_Data::4 79574 -system.ruby.network.routers3.msg_count.Writeback_Control::3 78994 -system.ruby.network.routers3.msg_bytes.Control::2 628008 -system.ruby.network.routers3.msg_bytes.Data::2 5610168 -system.ruby.network.routers3.msg_bytes.Response_Data::4 5729328 -system.ruby.network.routers3.msg_bytes.Writeback_Control::3 631952 -system.ruby.network.routers4.percent_links_utilized 5.192410 -system.ruby.network.routers4.msg_count.Control::2 78224 -system.ruby.network.routers4.msg_count.Data::2 77649 -system.ruby.network.routers4.msg_count.Response_Data::4 79271 -system.ruby.network.routers4.msg_count.Writeback_Control::3 78698 -system.ruby.network.routers4.msg_bytes.Control::2 625792 -system.ruby.network.routers4.msg_bytes.Data::2 5590728 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers4.msg_bytes.Writeback_Control::3 629584 -system.ruby.network.routers5.percent_links_utilized 5.202986 -system.ruby.network.routers5.msg_count.Control::2 78366 -system.ruby.network.routers5.msg_count.Data::2 77813 -system.ruby.network.routers5.msg_count.Response_Data::4 79427 -system.ruby.network.routers5.msg_count.Writeback_Control::3 78875 -system.ruby.network.routers5.msg_bytes.Control::2 626928 -system.ruby.network.routers5.msg_bytes.Data::2 5602536 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5718744 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 631000 -system.ruby.network.routers6.percent_links_utilized 5.183810 -system.ruby.network.routers6.msg_count.Control::2 78095 -system.ruby.network.routers6.msg_count.Data::2 77543 -system.ruby.network.routers6.msg_count.Response_Data::4 79117 -system.ruby.network.routers6.msg_count.Writeback_Control::3 78568 -system.ruby.network.routers6.msg_bytes.Control::2 624760 -system.ruby.network.routers6.msg_bytes.Data::2 5583096 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5696424 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 628544 -system.ruby.network.routers7.percent_links_utilized 5.195587 -system.ruby.network.routers7.msg_count.Control::2 78258 -system.ruby.network.routers7.msg_count.Data::2 77722 -system.ruby.network.routers7.msg_count.Response_Data::4 79294 -system.ruby.network.routers7.msg_count.Writeback_Control::3 78760 -system.ruby.network.routers7.msg_bytes.Control::2 626064 -system.ruby.network.routers7.msg_bytes.Data::2 5595984 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5709168 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 630080 -system.ruby.network.routers8.percent_links_utilized 41.047495 -system.ruby.network.routers8.msg_count.Control::2 625829 -system.ruby.network.routers8.msg_count.Data::2 621353 -system.ruby.network.routers8.msg_count.Response_Data::4 617479 -system.ruby.network.routers8.msg_count.Writeback_Control::3 629681 -system.ruby.network.routers8.msg_bytes.Control::2 5006632 -system.ruby.network.routers8.msg_bytes.Data::2 44737416 -system.ruby.network.routers8.msg_bytes.Response_Data::4 44458488 -system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5037448 -system.ruby.network.routers9.percent_links_utilized 9.176790 -system.ruby.network.routers9.msg_count.Control::2 625829 -system.ruby.network.routers9.msg_count.Data::2 621353 -system.ruby.network.routers9.msg_count.Response_Data::4 625808 -system.ruby.network.routers9.msg_count.Writeback_Control::3 629681 -system.ruby.network.routers9.msg_bytes.Control::2 5006632 -system.ruby.network.routers9.msg_bytes.Data::2 44737416 -system.ruby.network.routers9.msg_bytes.Response_Data::4 45058176 -system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5037448 -system.ruby.network.msg_count.Control 1877487 -system.ruby.network.msg_count.Data 1864059 -system.ruby.network.msg_count.Response_Data 1877425 -system.ruby.network.msg_count.Writeback_Control 1889042 -system.ruby.network.msg_byte.Control 15019896 -system.ruby.network.msg_byte.Data 134212248 -system.ruby.network.msg_byte.Response_Data 135174600 -system.ruby.network.msg_byte.Writeback_Control 15112336 -system.ruby.network.routers0.throttle0.link_utilization 5.173099 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78122 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78585 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5624784 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 628680 -system.ruby.network.routers0.throttle1.link_utilization 5.197632 -system.ruby.network.routers0.throttle1.msg_count.Control::2 78125 -system.ruby.network.routers0.throttle1.msg_count.Data::2 77570 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1015 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 625000 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5585040 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 73080 -system.ruby.network.routers1.throttle0.link_utilization 5.171087 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78091 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 78560 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5622552 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 628480 -system.ruby.network.routers1.throttle1.link_utilization 5.195924 -system.ruby.network.routers1.throttle1.msg_count.Control::2 78092 -system.ruby.network.routers1.throttle1.msg_count.Data::2 77517 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1043 -system.ruby.network.routers1.throttle1.msg_bytes.Control::2 624736 -system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5581224 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 75096 -system.ruby.network.routers2.throttle0.link_utilization 5.175965 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78164 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 78640 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5627808 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 629120 -system.ruby.network.routers2.throttle1.link_utilization 5.201192 -system.ruby.network.routers2.throttle1.msg_count.Control::2 78168 -system.ruby.network.routers2.throttle1.msg_count.Data::2 77620 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1020 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 625344 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5588640 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 73440 -system.ruby.network.routers3.throttle0.link_utilization 5.198141 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78497 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 78994 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5651784 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 631952 -system.ruby.network.routers3.throttle1.link_utilization 5.224600 -system.ruby.network.routers3.throttle1.msg_count.Control::2 78501 -system.ruby.network.routers3.throttle1.msg_count.Data::2 77919 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1077 -system.ruby.network.routers3.throttle1.msg_bytes.Control::2 628008 -system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5610168 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 77544 -system.ruby.network.routers4.throttle0.link_utilization 5.179743 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78221 -system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 78698 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5631912 -system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 629584 -system.ruby.network.routers4.throttle1.link_utilization 5.205077 -system.ruby.network.routers4.throttle1.msg_count.Control::2 78224 -system.ruby.network.routers4.throttle1.msg_count.Data::2 77649 -system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1050 -system.ruby.network.routers4.throttle1.msg_bytes.Control::2 625792 -system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5590728 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 75600 -system.ruby.network.routers5.throttle0.link_utilization 5.189472 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78365 -system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 78875 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5642280 -system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 631000 -system.ruby.network.routers5.throttle1.link_utilization 5.216499 -system.ruby.network.routers5.throttle1.msg_count.Control::2 78366 -system.ruby.network.routers5.throttle1.msg_count.Data::2 77813 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1062 -system.ruby.network.routers5.throttle1.msg_bytes.Control::2 626928 -system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5602536 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 76464 -system.ruby.network.routers6.throttle0.link_utilization 5.171200 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78092 -system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78568 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5622624 -system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 628544 -system.ruby.network.routers6.throttle1.link_utilization 5.196421 -system.ruby.network.routers6.throttle1.msg_count.Control::2 78095 -system.ruby.network.routers6.throttle1.msg_count.Data::2 77543 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1025 -system.ruby.network.routers6.throttle1.msg_bytes.Control::2 624760 -system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5583096 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 73800 -system.ruby.network.routers7.throttle0.link_utilization 5.182238 -system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78256 -system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 78760 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5634432 -system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 630080 -system.ruby.network.routers7.throttle1.link_utilization 5.208935 -system.ruby.network.routers7.throttle1.msg_count.Control::2 78258 -system.ruby.network.routers7.throttle1.msg_count.Data::2 77722 -system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1038 -system.ruby.network.routers7.throttle1.msg_bytes.Control::2 626064 -system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5595984 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 74736 -system.ruby.network.routers8.throttle0.link_utilization 41.150135 -system.ruby.network.routers8.throttle0.msg_count.Control::2 625829 -system.ruby.network.routers8.throttle0.msg_count.Data::2 621353 -system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5006632 -system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44737416 -system.ruby.network.routers8.throttle1.link_utilization 40.944855 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 617479 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 629681 -system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44458488 -system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5037448 -system.ruby.network.routers9.throttle0.link_utilization 5.173099 -system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78122 -system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 78585 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5624784 -system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 628680 -system.ruby.network.routers9.throttle1.link_utilization 5.171087 -system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78091 -system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 78560 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5622552 -system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 628480 -system.ruby.network.routers9.throttle2.link_utilization 5.175965 -system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78164 -system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 78640 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5627808 -system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 629120 -system.ruby.network.routers9.throttle3.link_utilization 5.198148 -system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78497 -system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 78995 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5651784 -system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 631960 -system.ruby.network.routers9.throttle4.link_utilization 5.179743 -system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78221 -system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 78698 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5631912 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 629584 -system.ruby.network.routers9.throttle5.link_utilization 5.189492 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78365 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 78875 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5642280 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 631000 -system.ruby.network.routers9.throttle6.link_utilization 5.171200 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78092 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78568 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5622624 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 628544 -system.ruby.network.routers9.throttle7.link_utilization 5.182238 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78256 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 78760 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5634432 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 630080 -system.ruby.network.routers9.throttle8.link_utilization 41.150135 -system.ruby.network.routers9.throttle8.msg_count.Control::2 625829 -system.ruby.network.routers9.throttle8.msg_count.Data::2 621353 -system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5006632 -system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44737416 +system.ruby.network.routers0.percent_links_utilized 5.129319 +system.ruby.network.routers0.msg_count.Control::2 78375 +system.ruby.network.routers0.msg_count.Data::2 77802 +system.ruby.network.routers0.msg_count.Response_Data::4 79436 +system.ruby.network.routers0.msg_count.Writeback_Control::3 78865 +system.ruby.network.routers0.msg_bytes.Control::2 627000 +system.ruby.network.routers0.msg_bytes.Data::2 5601744 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5719392 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 630920 +system.ruby.network.routers1.percent_links_utilized 5.151332 +system.ruby.network.routers1.msg_count.Control::2 78726 +system.ruby.network.routers1.msg_count.Data::2 78144 +system.ruby.network.routers1.msg_count.Response_Data::4 79769 +system.ruby.network.routers1.msg_count.Writeback_Control::3 79187 +system.ruby.network.routers1.msg_bytes.Control::2 629808 +system.ruby.network.routers1.msg_bytes.Data::2 5626368 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5743368 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 633496 +system.ruby.network.routers2.percent_links_utilized 5.131632 +system.ruby.network.routers2.msg_count.Control::2 78427 +system.ruby.network.routers2.msg_count.Data::2 77847 +system.ruby.network.routers2.msg_count.Response_Data::4 79462 +system.ruby.network.routers2.msg_count.Writeback_Control::3 78883 +system.ruby.network.routers2.msg_bytes.Control::2 627416 +system.ruby.network.routers2.msg_bytes.Data::2 5604984 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5721264 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 631064 +system.ruby.network.routers3.percent_links_utilized 5.129381 +system.ruby.network.routers3.msg_count.Control::2 78400 +system.ruby.network.routers3.msg_count.Data::2 77822 +system.ruby.network.routers3.msg_count.Response_Data::4 79418 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+system.ruby.network.msg_byte.Response_Data 135478728 +system.ruby.network.msg_byte.Writeback_Control 15143776 +system.ruby.network.routers0.throttle0.link_utilization 5.116473 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78373 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78865 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5642856 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 630920 +system.ruby.network.routers0.throttle1.link_utilization 5.142166 +system.ruby.network.routers0.throttle1.msg_count.Control::2 78375 +system.ruby.network.routers0.throttle1.msg_count.Data::2 77802 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1063 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 627000 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5601744 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 76536 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+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 78883 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5646456 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 631064 +system.ruby.network.routers2.throttle1.link_utilization 5.143738 +system.ruby.network.routers2.throttle1.msg_count.Control::2 78427 +system.ruby.network.routers2.throttle1.msg_count.Data::2 77847 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1039 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 627416 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5604984 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 74808 +system.ruby.network.routers3.throttle0.link_utilization 5.117843 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78399 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 78841 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5644728 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 630728 +system.ruby.network.routers3.throttle1.link_utilization 5.140920 +system.ruby.network.routers3.throttle1.msg_count.Control::2 78400 +system.ruby.network.routers3.throttle1.msg_count.Data::2 77822 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1019 +system.ruby.network.routers3.throttle1.msg_bytes.Control::2 627200 +system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5603184 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 73368 +system.ruby.network.routers4.throttle0.link_utilization 5.108253 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78246 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 78751 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5633712 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 630008 +system.ruby.network.routers4.throttle1.link_utilization 5.134643 +system.ruby.network.routers4.throttle1.msg_count.Control::2 78248 +system.ruby.network.routers4.throttle1.msg_count.Data::2 77658 +system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1093 +system.ruby.network.routers4.throttle1.msg_bytes.Control::2 625984 +system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5591376 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 78696 +system.ruby.network.routers5.throttle0.link_utilization 5.116121 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78370 +system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 78838 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5642640 +system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 630704 +system.ruby.network.routers5.throttle1.link_utilization 5.140561 +system.ruby.network.routers5.throttle1.msg_count.Control::2 78372 +system.ruby.network.routers5.throttle1.msg_count.Data::2 77763 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1075 +system.ruby.network.routers5.throttle1.msg_bytes.Control::2 626976 +system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5598936 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 77400 +system.ruby.network.routers6.throttle0.link_utilization 5.118600 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78409 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78867 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5645448 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 630936 +system.ruby.network.routers6.throttle1.link_utilization 5.142531 +system.ruby.network.routers6.throttle1.msg_count.Control::2 78413 +system.ruby.network.routers6.throttle1.msg_count.Data::2 77861 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1006 +system.ruby.network.routers6.throttle1.msg_bytes.Control::2 627304 +system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5605992 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 72432 +system.ruby.network.routers7.throttle0.link_utilization 5.109845 +system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78272 +system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 78758 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5635584 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 630064 +system.ruby.network.routers7.throttle1.link_utilization 5.135217 +system.ruby.network.routers7.throttle1.msg_count.Control::2 78273 +system.ruby.network.routers7.throttle1.msg_count.Data::2 77733 +system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1025 +system.ruby.network.routers7.throttle1.msg_bytes.Control::2 626184 +system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5596776 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 73800 +system.ruby.network.routers8.throttle0.link_utilization 40.652025 +system.ruby.network.routers8.throttle0.msg_count.Control::2 627233 +system.ruby.network.routers8.throttle0.msg_count.Data::2 622630 +system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5017864 +system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44829360 +system.ruby.network.routers8.throttle1.link_utilization 40.454718 +system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 618852 +system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 630991 +system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44557344 +system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5047928 +system.ruby.network.routers9.throttle0.link_utilization 5.116473 +system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78373 +system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 78865 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5642856 +system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 630920 +system.ruby.network.routers9.throttle1.link_utilization 5.139184 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78724 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 79187 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5668128 +system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 633496 +system.ruby.network.routers9.throttle2.link_utilization 5.119533 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78423 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 78884 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5646456 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 631072 +system.ruby.network.routers9.throttle3.link_utilization 5.117843 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78399 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 78841 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5644728 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 630728 +system.ruby.network.routers9.throttle4.link_utilization 5.108272 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78246 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 78751 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5633712 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 630008 +system.ruby.network.routers9.throttle5.link_utilization 5.116121 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78370 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 78838 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5642640 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 630704 +system.ruby.network.routers9.throttle6.link_utilization 5.118600 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78409 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78867 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5645448 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 630936 +system.ruby.network.routers9.throttle7.link_utilization 5.109845 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78272 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 78758 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5635584 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 630064 +system.ruby.network.routers9.throttle8.link_utilization 40.652051 +system.ruby.network.routers9.throttle8.msg_count.Control::2 627233 +system.ruby.network.routers9.throttle8.msg_count.Data::2 622630 +system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5017864 +system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44829360 system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 625808 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.264720 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 1.304410 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 600768 96.00% 96.00% | 18387 2.94% 98.94% | 5734 0.92% 99.85% | 745 0.12% 99.97% | 149 0.02% 100.00% | 19 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 625808 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 627216 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.278025 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 1.343597 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 601064 95.83% 95.83% | 19006 3.03% 98.86% | 6107 0.97% 99.83% | 844 0.13% 99.97% | 158 0.03% 99.99% | 32 0.01% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 627216 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 32 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 319 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 629680 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 4.062621 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 10.310093 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 612866 97.33% 97.33% | 10648 1.69% 99.02% | 5547 0.88% 99.90% | 516 0.08% 99.98% | 82 0.01% 100.00% | 21 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 629680 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 630990 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 4.299775 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 10.492949 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 613039 97.16% 97.16% | 11748 1.86% 99.02% | 5468 0.87% 99.88% | 595 0.09% 99.98% | 125 0.02% 100.00% | 15 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 630990 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 403166 -system.ruby.LD.latency_hist::mean 1544.913271 -system.ruby.LD.latency_hist::gmean 1522.275613 -system.ruby.LD.latency_hist::stdev 264.561950 -system.ruby.LD.latency_hist | 54 0.01% 0.01% | 5301 1.31% 1.33% | 203466 50.47% 51.80% | 178892 44.37% 96.17% | 15319 3.80% 99.97% | 134 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 403166 +system.ruby.LD.latency_hist::samples 403846 +system.ruby.LD.latency_hist::mean 1564.356052 +system.ruby.LD.latency_hist::gmean 1542.244005 +system.ruby.LD.latency_hist::stdev 262.678202 +system.ruby.LD.latency_hist | 49 0.01% 0.01% | 4121 1.02% 1.03% | 191073 47.31% 48.35% | 191459 47.41% 95.75% | 17013 4.21% 99.97% | 131 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 403846 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 403166 -system.ruby.LD.miss_latency_hist::mean 1544.913271 -system.ruby.LD.miss_latency_hist::gmean 1522.275613 -system.ruby.LD.miss_latency_hist::stdev 264.561950 -system.ruby.LD.miss_latency_hist | 54 0.01% 0.01% | 5301 1.31% 1.33% | 203466 50.47% 51.80% | 178892 44.37% 96.17% | 15319 3.80% 99.97% | 134 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 403166 +system.ruby.LD.miss_latency_hist::samples 403846 +system.ruby.LD.miss_latency_hist::mean 1564.356052 +system.ruby.LD.miss_latency_hist::gmean 1542.244005 +system.ruby.LD.miss_latency_hist::stdev 262.678202 +system.ruby.LD.miss_latency_hist | 49 0.01% 0.01% | 4121 1.02% 1.03% | 191073 47.31% 48.35% | 191459 47.41% 95.75% | 17013 4.21% 99.97% | 131 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 403846 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 222642 -system.ruby.ST.latency_hist::mean 1545.557276 -system.ruby.ST.latency_hist::gmean 1523.054587 -system.ruby.ST.latency_hist::stdev 263.959637 -system.ruby.ST.latency_hist | 26 0.01% 0.01% | 2830 1.27% 1.28% | 112233 50.41% 51.69% | 99092 44.51% 96.20% | 8397 3.77% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 222642 +system.ruby.ST.latency_hist::samples 223370 +system.ruby.ST.latency_hist::mean 1562.875592 +system.ruby.ST.latency_hist::gmean 1540.868654 +system.ruby.ST.latency_hist::stdev 262.183398 +system.ruby.ST.latency_hist | 25 0.01% 0.01% | 2224 1.00% 1.01% | 106289 47.58% 48.59% | 105464 47.21% 95.81% | 9313 4.17% 99.98% | 55 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 223370 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 222642 -system.ruby.ST.miss_latency_hist::mean 1545.557276 -system.ruby.ST.miss_latency_hist::gmean 1523.054587 -system.ruby.ST.miss_latency_hist::stdev 263.959637 -system.ruby.ST.miss_latency_hist | 26 0.01% 0.01% | 2830 1.27% 1.28% | 112233 50.41% 51.69% | 99092 44.51% 96.20% | 8397 3.77% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 222642 +system.ruby.ST.miss_latency_hist::samples 223370 +system.ruby.ST.miss_latency_hist::mean 1562.875592 +system.ruby.ST.miss_latency_hist::gmean 1540.868654 +system.ruby.ST.miss_latency_hist::stdev 262.183398 +system.ruby.ST.miss_latency_hist | 25 0.01% 0.01% | 2224 1.00% 1.01% | 106289 47.58% 48.59% | 105464 47.21% 95.81% | 9313 4.17% 99.98% | 55 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 223370 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 256 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 2559 -system.ruby.L1Cache.miss_mach_latency_hist::samples 8330 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1434.603121 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 1410.421846 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 264.603090 -system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 1 0.01% 0.01% | 5 0.06% 0.07% | 356 4.27% 4.35% | 2133 25.61% 29.95% | 3056 36.69% 66.64% | 1973 23.69% 90.32% | 656 7.88% 98.20% | 135 1.62% 99.82% | 15 0.18% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 8330 +system.ruby.L1Cache.miss_mach_latency_hist::samples 8365 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1451.964973 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 1428.123132 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 264.328285 +system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 0.08% 0.08% | 311 3.72% 3.80% | 1935 23.13% 26.93% | 3130 37.42% 64.35% | 2091 25.00% 89.35% | 726 8.68% 98.03% | 146 1.75% 99.77% | 19 0.23% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 8365 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 617478 -system.ruby.Directory.miss_mach_latency_hist::mean 1546.633602 -system.ruby.Directory.miss_mach_latency_hist::gmean 1524.124795 -system.ruby.Directory.miss_mach_latency_hist::stdev 264.028380 -system.ruby.Directory.miss_mach_latency_hist | 79 0.01% 0.01% | 7770 1.26% 1.27% | 310510 50.29% 51.56% | 275355 44.59% 96.15% | 23566 3.82% 99.97% | 198 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 617478 +system.ruby.Directory.miss_mach_latency_hist::samples 618851 +system.ruby.Directory.miss_mach_latency_hist::mean 1565.340878 +system.ruby.Directory.miss_mach_latency_hist::gmean 1543.350381 +system.ruby.Directory.miss_mach_latency_hist::stdev 262.151529 +system.ruby.Directory.miss_mach_latency_hist | 74 0.01% 0.01% | 6027 0.97% 0.99% | 292297 47.23% 48.22% | 294106 47.52% 95.74% | 26161 4.23% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 618851 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 3 @@ -677,82 +677,82 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion | system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 3 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 256 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5325 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1437.811643 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1413.385470 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 266.536201 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 1 0.02% 0.02% | 2 0.04% 0.06% | 221 4.15% 4.21% | 1362 25.58% 29.78% | 1962 36.85% 66.63% | 1238 23.25% 89.88% | 433 8.13% 98.01% | 97 1.82% 99.83% | 9 0.17% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5325 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5351 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1448.396001 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1424.162973 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 266.250656 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 0.07% 0.07% | 221 4.13% 4.20% | 1256 23.47% 27.68% | 2002 37.41% 65.09% | 1297 24.24% 89.33% | 460 8.60% 97.93% | 99 1.85% 99.78% | 12 0.22% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5351 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 397841 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1546.346799 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1523.788586 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 264.241520 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 53 0.01% 0.01% | 5078 1.28% 1.29% | 200142 50.31% 51.60% | 177221 44.55% 96.14% | 15213 3.82% 99.97% | 134 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 397841 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 398495 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1565.913166 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1543.894470 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 262.281631 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 49 0.01% 0.01% | 3896 0.98% 0.99% | 187815 47.13% 48.12% | 189702 47.60% 95.73% | 16902 4.24% 99.97% | 131 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 398495 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 256 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 3005 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1428.917471 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1405.185421 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 261.089644 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 0.10% 0.10% | 135 4.49% 4.59% | 771 25.66% 30.25% | 1094 36.41% 66.66% | 735 24.46% 91.11% | 223 7.42% 98.54% | 38 1.26% 99.80% | 6 0.20% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 3005 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 3014 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1458.301261 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1435.181075 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 260.804046 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 0.10% 0.10% | 90 2.99% 3.09% | 679 22.53% 25.61% | 1128 37.43% 63.04% | 794 26.34% 89.38% | 266 8.83% 98.21% | 47 1.56% 99.77% | 7 0.23% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 3014 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 219637 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1547.153103 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1524.733978 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 263.641675 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 26 0.01% 0.01% | 2692 1.23% 1.24% | 110368 50.25% 51.49% | 98134 44.68% 96.17% | 8353 3.80% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 219637 -system.ruby.Directory_Controller.GETX 689360 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 617467 0.00% 0.00% -system.ruby.Directory_Controller.PUTX_NotOwner 3886 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 617479 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 617466 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 617498 0.00% 0.00% -system.ruby.Directory_Controller.M.GETX 8330 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 617467 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX_NotOwner 3886 0.00% 0.00% -system.ruby.Directory_Controller.IM.GETX 63241 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 617479 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 291 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 617466 0.00% 0.00% -system.ruby.L1Cache_Controller.Load | 50298 12.48% 12.48% | 50313 12.48% 24.95% | 50604 12.55% 37.51% | 50559 12.54% 50.05% | 50335 12.48% 62.53% | 50365 12.49% 75.02% | 50340 12.49% 87.51% | 50369 12.49% 100.00% -system.ruby.L1Cache_Controller.Load::total 403183 -system.ruby.L1Cache_Controller.Store | 27827 12.50% 12.50% | 27779 12.48% 24.97% | 27564 12.38% 37.36% | 27942 12.55% 49.91% | 27889 12.53% 62.43% | 28002 12.58% 75.01% | 27755 12.47% 87.47% | 27889 12.53% 100.00% -system.ruby.L1Cache_Controller.Store::total 222647 -system.ruby.L1Cache_Controller.Data | 78122 12.48% 12.48% | 78091 12.48% 24.96% | 78164 12.49% 37.45% | 78497 12.54% 50.00% | 78221 12.50% 62.49% | 78365 12.52% 75.02% | 78092 12.48% 87.50% | 78256 12.50% 100.00% -system.ruby.L1Cache_Controller.Data::total 625808 -system.ruby.L1Cache_Controller.Fwd_GETX | 1015 12.18% 12.18% | 1043 12.52% 24.71% | 1020 12.24% 36.95% | 1077 12.93% 49.88% | 1050 12.61% 62.48% | 1062 12.75% 75.23% | 1025 12.30% 87.54% | 1038 12.46% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 8330 -system.ruby.L1Cache_Controller.Replacement | 78121 12.48% 12.48% | 78088 12.48% 24.96% | 78164 12.49% 37.45% | 78497 12.54% 50.00% | 78220 12.50% 62.49% | 78363 12.52% 75.02% | 78091 12.48% 87.50% | 78254 12.50% 100.00% -system.ruby.L1Cache_Controller.Replacement::total 625798 -system.ruby.L1Cache_Controller.Writeback_Ack | 77106 12.49% 12.49% | 77045 12.48% 24.97% | 77144 12.49% 37.46% | 77418 12.54% 50.00% | 77169 12.50% 62.49% | 77300 12.52% 75.01% | 77066 12.48% 87.49% | 77216 12.51% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 617464 -system.ruby.L1Cache_Controller.Writeback_Nack | 464 11.94% 11.94% | 472 12.15% 24.09% | 476 12.25% 36.34% | 499 12.84% 49.18% | 479 12.33% 61.50% | 513 13.20% 74.70% | 477 12.27% 86.98% | 506 13.02% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 3886 -system.ruby.L1Cache_Controller.I.Load | 50298 12.48% 12.48% | 50313 12.48% 24.95% | 50604 12.55% 37.51% | 50559 12.54% 50.05% | 50335 12.48% 62.53% | 50365 12.49% 75.02% | 50340 12.49% 87.51% | 50369 12.49% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 403183 -system.ruby.L1Cache_Controller.I.Store | 27827 12.50% 12.50% | 27779 12.48% 24.97% | 27564 12.38% 37.36% | 27942 12.55% 49.91% | 27889 12.53% 62.43% | 28002 12.58% 75.01% | 27755 12.47% 87.47% | 27889 12.53% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 222647 -system.ruby.L1Cache_Controller.I.Replacement | 551 12.40% 12.40% | 571 12.85% 25.25% | 544 12.24% 37.49% | 578 13.01% 50.50% | 571 12.85% 63.34% | 549 12.35% 75.70% | 548 12.33% 88.03% | 532 11.97% 100.00% -system.ruby.L1Cache_Controller.I.Replacement::total 4444 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 464 11.94% 11.94% | 472 12.15% 24.09% | 476 12.25% 36.34% | 499 12.84% 49.18% | 479 12.33% 61.50% | 513 13.20% 74.70% | 477 12.27% 86.98% | 506 13.02% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3886 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 551 12.40% 12.40% | 571 12.85% 25.25% | 544 12.24% 37.49% | 578 13.01% 50.50% | 571 12.85% 63.34% | 549 12.35% 75.70% | 548 12.33% 88.03% | 532 11.97% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4444 -system.ruby.L1Cache_Controller.M.Replacement | 77570 12.48% 12.48% | 77517 12.48% 24.96% | 77620 12.49% 37.45% | 77919 12.54% 49.99% | 77649 12.50% 62.49% | 77814 12.52% 75.01% | 77543 12.48% 87.49% | 77722 12.51% 100.00% -system.ruby.L1Cache_Controller.M.Replacement::total 621354 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 464 11.94% 11.94% | 472 12.15% 24.09% | 476 12.25% 36.34% | 499 12.84% 49.18% | 479 12.33% 61.50% | 513 13.20% 74.70% | 477 12.27% 86.98% | 506 13.02% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3886 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77106 12.49% 12.49% | 77045 12.48% 24.97% | 77144 12.49% 37.46% | 77418 12.54% 50.00% | 77169 12.50% 62.49% | 77300 12.52% 75.01% | 77066 12.48% 87.49% | 77216 12.51% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 617464 -system.ruby.L1Cache_Controller.IS.Data | 50296 12.48% 12.48% | 50312 12.48% 24.95% | 50601 12.55% 37.51% | 50556 12.54% 50.05% | 50332 12.48% 62.53% | 50363 12.49% 75.02% | 50339 12.49% 87.51% | 50367 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 403166 -system.ruby.L1Cache_Controller.IM.Data | 27826 12.50% 12.50% | 27779 12.48% 24.98% | 27563 12.38% 37.36% | 27941 12.55% 49.90% | 27889 12.53% 62.43% | 28002 12.58% 75.01% | 27753 12.47% 87.47% | 27889 12.53% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 222642 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 220356 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1564.305946 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1542.366929 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 261.913507 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 25 0.01% 0.01% | 2131 0.97% 0.98% | 104482 47.42% 48.39% | 104404 47.38% 95.77% | 9259 4.20% 99.98% | 55 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 220356 +system.ruby.Directory_Controller.GETX 692466 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 618836 0.00% 0.00% +system.ruby.Directory_Controller.PUTX_NotOwner 3793 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 618852 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 618834 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 618868 0.00% 0.00% +system.ruby.Directory_Controller.M.GETX 8365 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 618836 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX_NotOwner 3793 0.00% 0.00% +system.ruby.Directory_Controller.IM.GETX 64870 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 618852 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETX 363 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 618834 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50369 12.47% 12.47% | 50818 12.58% 25.06% | 50345 12.47% 37.52% | 50466 12.50% 50.02% | 50330 12.46% 62.48% | 50594 12.53% 75.01% | 50513 12.51% 87.51% | 50423 12.49% 100.00% +system.ruby.L1Cache_Controller.Load::total 403858 +system.ruby.L1Cache_Controller.Store | 28006 12.54% 12.54% | 27910 12.49% 25.03% | 28082 12.57% 37.60% | 27934 12.51% 50.11% | 27918 12.50% 62.61% | 27778 12.44% 75.04% | 27900 12.49% 87.53% | 27850 12.47% 100.00% +system.ruby.L1Cache_Controller.Store::total 223378 +system.ruby.L1Cache_Controller.Data | 78373 12.50% 12.50% | 78724 12.55% 25.05% | 78423 12.50% 37.55% | 78399 12.50% 50.05% | 78246 12.48% 62.52% | 78370 12.49% 75.02% | 78409 12.50% 87.52% | 78272 12.48% 100.00% +system.ruby.L1Cache_Controller.Data::total 627216 +system.ruby.L1Cache_Controller.Fwd_GETX | 1063 12.71% 12.71% | 1045 12.49% 25.20% | 1039 12.42% 37.62% | 1019 12.18% 49.80% | 1093 13.07% 62.87% | 1075 12.85% 75.72% | 1006 12.03% 87.75% | 1025 12.25% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 8365 +system.ruby.L1Cache_Controller.Replacement | 78371 12.50% 12.50% | 78724 12.55% 25.05% | 78423 12.50% 37.55% | 78396 12.50% 50.05% | 78244 12.48% 62.52% | 78368 12.49% 75.02% | 78409 12.50% 87.52% | 78269 12.48% 100.00% +system.ruby.L1Cache_Controller.Replacement::total 627204 +system.ruby.L1Cache_Controller.Writeback_Ack | 77308 12.49% 12.49% | 77675 12.55% 25.04% | 77381 12.50% 37.55% | 77377 12.50% 50.05% | 77151 12.47% 62.52% | 77293 12.49% 75.01% | 77403 12.51% 87.52% | 77244 12.48% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 618832 +system.ruby.L1Cache_Controller.Writeback_Nack | 494 13.02% 13.02% | 467 12.31% 25.34% | 463 12.21% 37.54% | 445 11.73% 49.27% | 507 13.37% 62.64% | 470 12.39% 75.03% | 458 12.07% 87.11% | 489 12.89% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 3793 +system.ruby.L1Cache_Controller.I.Load | 50369 12.47% 12.47% | 50818 12.58% 25.06% | 50345 12.47% 37.52% | 50466 12.50% 50.02% | 50330 12.46% 62.48% | 50594 12.53% 75.01% | 50513 12.51% 87.51% | 50423 12.49% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 403858 +system.ruby.L1Cache_Controller.I.Store | 28006 12.54% 12.54% | 27910 12.49% 25.03% | 28082 12.57% 37.60% | 27934 12.51% 50.11% | 27918 12.50% 62.61% | 27778 12.44% 75.04% | 27900 12.49% 87.53% | 27850 12.47% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 223378 +system.ruby.L1Cache_Controller.I.Replacement | 569 12.45% 12.45% | 578 12.64% 25.09% | 576 12.60% 37.69% | 574 12.55% 50.24% | 586 12.82% 63.06% | 605 13.23% 76.29% | 548 11.99% 88.28% | 536 11.72% 100.00% +system.ruby.L1Cache_Controller.I.Replacement::total 4572 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 494 13.02% 13.02% | 467 12.31% 25.34% | 463 12.21% 37.54% | 445 11.73% 49.27% | 507 13.37% 62.64% | 470 12.39% 75.03% | 458 12.07% 87.11% | 489 12.89% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3793 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 569 12.45% 12.45% | 578 12.64% 25.09% | 576 12.60% 37.69% | 574 12.55% 50.24% | 586 12.82% 63.06% | 605 13.23% 76.29% | 548 11.99% 88.28% | 536 11.72% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4572 +system.ruby.L1Cache_Controller.M.Replacement | 77802 12.50% 12.50% | 78146 12.55% 25.05% | 77847 12.50% 37.55% | 77822 12.50% 50.05% | 77658 12.47% 62.52% | 77763 12.49% 75.01% | 77861 12.51% 87.52% | 77733 12.48% 100.00% +system.ruby.L1Cache_Controller.M.Replacement::total 622632 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 494 13.02% 13.02% | 467 12.31% 25.34% | 463 12.21% 37.54% | 445 11.73% 49.27% | 507 13.37% 62.64% | 470 12.39% 75.03% | 458 12.07% 87.11% | 489 12.89% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3793 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77308 12.49% 12.49% | 77675 12.55% 25.04% | 77381 12.50% 37.55% | 77377 12.50% 50.05% | 77151 12.47% 62.52% | 77293 12.49% 75.01% | 77403 12.51% 87.52% | 77244 12.48% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 618832 +system.ruby.L1Cache_Controller.IS.Data | 50369 12.47% 12.47% | 50815 12.58% 25.06% | 50341 12.47% 37.52% | 50465 12.50% 50.02% | 50329 12.46% 62.48% | 50593 12.53% 75.01% | 50512 12.51% 87.51% | 50422 12.49% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 403846 +system.ruby.L1Cache_Controller.IM.Data | 28004 12.54% 12.54% | 27909 12.49% 25.03% | 28082 12.57% 37.60% | 27934 12.51% 50.11% | 27917 12.50% 62.61% | 27777 12.44% 75.04% | 27897 12.49% 87.53% | 27850 12.47% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 223370 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index c01cc2902..96f88f923 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1809 +1,1817 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000790 # Number of seconds simulated -sim_ticks 789792500 # Number of ticks simulated -final_tick 789792500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000889 # Number of seconds simulated +sim_ticks 888991000 # Number of ticks simulated +final_tick 888991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 129975147 # Simulator tick rate (ticks/s) -host_mem_usage 221936 # Number of bytes of host memory used -host_seconds 6.08 # Real time elapsed on the host +host_tick_rate 170326912 # Simulator tick rate (ticks/s) +host_mem_usage 278304 # Number of bytes of host memory used +host_seconds 5.22 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 78179 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 78681 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 79146 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 76465 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 76157 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 75918 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79229 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 81414 # Number of bytes read from this memory -system.physmem.bytes_read::total 625189 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 393152 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5414 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5436 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5494 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5519 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5358 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5447 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5462 # Number of bytes written to this memory -system.physmem.bytes_written::total 436740 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10874 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87862 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6143 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5414 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5494 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5519 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5358 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5447 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5462 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 98986759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 99622369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 100211131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 96816569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 96426593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 96123982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 100316222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 103082772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 791586398 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 497791509 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 6854965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6882820 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 6956257 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6987911 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6784060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 6910676 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 6896748 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 6915741 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 552980688 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 497791509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 105841724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 106505190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 107167389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 103804480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 103210653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 103034658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 107212970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 109998512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1344567086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 77301 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 77008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 78427 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 77571 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 81605 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 77234 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 80454 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 78765 # Number of bytes read from this memory +system.physmem.bytes_read::total 628365 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 396032 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5354 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5486 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5463 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5457 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5585 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5519 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5444 # Number of bytes written to this memory +system.physmem.bytes_written::total 439804 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10773 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10795 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11043 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10839 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10977 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87447 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6188 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5354 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5486 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5463 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5457 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5585 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5519 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49960 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 86953636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 86624049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 88220241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 87257351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 91795080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 86878270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 90500354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 88600447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 706829428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 445484825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 6022558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6171041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 6145169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6138420 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6146294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 6282403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 6208162 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 6123797 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 494722669 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 445484825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 92976194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 92795090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 94365410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 93395771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 97941374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 93160673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 96708516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 94724244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1201552097 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99211 # number of read accesses completed -system.cpu0.num_writes 54990 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22470 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.865816 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13332 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22858 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.583253 # Average number of references to valid blocks. +system.cpu0.num_reads 99131 # number of read accesses completed +system.cpu0.num_writes 55164 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22535 # number of replacements +system.cpu0.l1c.tags.tagsinuse 395.025918 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13450 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.586338 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.865816 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.769269 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.769269 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337265 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337265 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8594 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8594 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9737 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9737 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9737 # number of overall hits -system.cpu0.l1c.overall_hits::total 9737 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36367 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36367 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24030 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24030 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60397 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60397 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60397 # number of overall misses -system.cpu0.l1c.overall_misses::total 60397 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1097985534 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1097985534 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1003527320 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1003527320 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2101512854 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2101512854 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2101512854 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2101512854 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44961 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44961 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25173 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25173 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70134 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70134 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70134 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70134 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808857 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.808857 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954594 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954594 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861166 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861166 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861166 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861166 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 30191.809443 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 30191.809443 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 41761.436538 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 41761.436538 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 34794.987400 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 34794.987400 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 34794.987400 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 34794.987400 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1144726 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 395.025918 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.771535 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.771535 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338659 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338659 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8591 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8591 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1192 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1192 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9783 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9783 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9783 # number of overall hits +system.cpu0.l1c.overall_hits::total 9783 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36665 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36665 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23983 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23983 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60648 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60648 # number of overall misses +system.cpu0.l1c.overall_misses::total 60648 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1205183022 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1205183022 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1064148669 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1064148669 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2269331691 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2269331691 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2269331691 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2269331691 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45256 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45256 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25175 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70431 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70431 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70431 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70431 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810169 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.810169 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952651 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952651 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861098 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861098 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861098 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861098 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 32870.121969 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 32870.121969 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 44370.957303 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 44370.957303 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 37418.079590 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 37418.079590 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 37418.079590 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 37418.079590 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1129963 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61078 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 56549 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 18.742035 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 19.982016 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9946 # number of writebacks -system.cpu0.l1c.writebacks::total 9946 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36367 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36367 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24030 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24030 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60397 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60397 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60397 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60397 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9956 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5416 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5416 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15372 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15372 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1042449014 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1042449014 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 966947420 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 966947420 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2009396434 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2009396434 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2009396434 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2009396434 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 778948863 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 778948863 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 2127994240 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 2127994240 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2906943103 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2906943103 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808857 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808857 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954594 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954594 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861166 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861166 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 28664.696401 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 28664.696401 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 40239.176862 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 40239.176862 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78239.138509 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78239.138509 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 392908.833087 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392908.833087 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 189106.368918 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 189106.368918 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9979 # number of writebacks +system.cpu0.l1c.writebacks::total 9979 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36665 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36665 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23983 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60648 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60648 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9718 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9718 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5355 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5355 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15073 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1168518022 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1168518022 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1040166669 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1040166669 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2208684691 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2208684691 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2208684691 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2208684691 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 789521900 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 789521900 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1493953369 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1493953369 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2283475269 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2283475269 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810169 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810169 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952651 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952651 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861098 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861098 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 31870.121969 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 31870.121969 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 43370.998999 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 43370.998999 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 81243.249640 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81243.249640 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 278982.888702 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 278982.888702 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 151494.411796 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 151494.411796 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 55318 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22177 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.980771 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13598 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22566 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.602588 # Average number of references to valid blocks. +system.cpu1.num_reads 99860 # number of read accesses completed +system.cpu1.num_writes 55211 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22541 # number of replacements +system.cpu1.l1c.tags.tagsinuse 395.711444 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13500 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22934 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.588646 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.980771 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.769494 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.769494 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338430 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338430 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8884 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8884 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1068 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1068 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9952 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9952 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9952 # number of overall hits -system.cpu1.l1c.overall_hits::total 9952 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36538 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36538 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23930 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23930 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60468 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60468 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60468 # number of overall misses -system.cpu1.l1c.overall_misses::total 60468 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1108002821 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1108002821 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 993849096 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 993849096 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2101851917 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2101851917 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2101851917 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2101851917 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45422 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45422 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24998 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24998 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70420 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70420 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70420 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70420 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804412 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.804412 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.957277 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.957277 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858677 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858677 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858677 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858677 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 30324.670781 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 30324.670781 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 41531.512578 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 41531.512578 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 34759.739317 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 34759.739317 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 34759.739317 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 34759.739317 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1147241 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 395.711444 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.772874 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.772874 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338432 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338432 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8752 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8752 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1139 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1139 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9891 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9891 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9891 # number of overall hits +system.cpu1.l1c.overall_hits::total 9891 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36537 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36537 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23971 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23971 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60508 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60508 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60508 # number of overall misses +system.cpu1.l1c.overall_misses::total 60508 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1195916774 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1195916774 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1059745891 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1059745891 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2255662665 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2255662665 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2255662665 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2255662665 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45289 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45289 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25110 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70399 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70399 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70399 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70399 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806752 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.806752 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954640 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954640 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859501 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859501 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859501 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859501 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 32731.663081 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 32731.663081 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 44209.498602 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 44209.498602 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 37278.750992 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 37278.750992 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 37278.750992 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 37278.750992 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1120827 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 61428 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 56192 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 18.676190 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 19.946380 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu1.l1c.writebacks::total 9780 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36538 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36538 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23930 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23930 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60468 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60468 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60468 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 10010 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 10010 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5438 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15448 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15448 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1052180887 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1052180887 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 957433148 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 957433148 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2009614035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2009614035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2009614035 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2009614035 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 780874824 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 780874824 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 2141613646 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 2141613646 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2922488470 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2922488470 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804412 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804412 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.957277 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.957277 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858677 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858677 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 28796.893289 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 28796.893289 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 40009.742917 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 40009.742917 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78009.472927 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78009.472927 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 393823.767194 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 393823.767194 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 189182.319394 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 189182.319394 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9897 # number of writebacks +system.cpu1.l1c.writebacks::total 9897 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36537 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36537 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23971 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60508 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60508 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60508 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60508 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5487 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5487 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15231 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15231 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1159382774 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1159382774 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1035775891 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1035775891 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2195158665 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2195158665 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2195158665 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2195158665 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 792485431 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 792485431 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1532713252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1532713252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2325198683 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2325198683 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806752 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806752 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954640 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954640 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859501 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859501 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 31731.745190 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 31731.745190 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 43209.540320 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 43209.540320 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 81330.606630 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81330.606630 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 279335.383999 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279335.383999 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 152662.246931 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 152662.246931 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99906 # number of read accesses completed -system.cpu2.num_writes 55186 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22429 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.168243 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13360 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.585605 # Average number of references to valid blocks. +system.cpu2.num_reads 99820 # number of read accesses completed +system.cpu2.num_writes 54950 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22307 # number of replacements +system.cpu2.l1c.tags.tagsinuse 395.344704 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13648 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22708 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.168243 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.769860 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.769860 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338029 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338029 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8660 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1124 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1124 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9784 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9784 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9784 # number of overall hits -system.cpu2.l1c.overall_hits::total 9784 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36507 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36507 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24000 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24000 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60507 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60507 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60507 # number of overall misses -system.cpu2.l1c.overall_misses::total 60507 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1106428919 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1106428919 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1000960978 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1000960978 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2107389897 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2107389897 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2107389897 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2107389897 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45167 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45167 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70291 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70291 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70291 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70291 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808267 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.808267 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955262 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955262 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.860807 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.860807 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.860807 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.860807 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 30307.308708 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 30307.308708 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 41706.707417 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 41706.707417 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 34828.861074 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 34828.861074 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 34828.861074 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 34828.861074 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1143492 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 395.344704 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.772158 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.772158 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 339436 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 339436 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8860 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8860 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1133 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1133 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits +system.cpu2.l1c.overall_hits::total 9993 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36664 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36664 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23971 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23971 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60635 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60635 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60635 # number of overall misses +system.cpu2.l1c.overall_misses::total 60635 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1194013761 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1194013761 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1064419870 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1064419870 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2258433631 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2258433631 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2258433631 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2258433631 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45524 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45524 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25104 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25104 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70628 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70628 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70628 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70628 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805377 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805377 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954868 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858512 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858512 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858512 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858512 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 32566.380128 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 32566.380128 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 44404.483334 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 44404.483334 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 37246.369770 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 37246.369770 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 37246.369770 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 37246.369770 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1131174 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 56579 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 18.666514 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 19.992824 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9834 # number of writebacks -system.cpu2.l1c.writebacks::total 9834 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36507 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36507 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24000 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60507 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60507 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60507 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60507 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9899 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9899 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5496 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5496 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15395 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1050702877 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1050702877 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 964435030 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 964435030 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2015137907 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2015137907 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2015137907 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2015137907 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 774345338 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 774345338 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 2129438676 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 2129438676 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2903784014 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2903784014 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808267 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808267 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955262 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955262 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.860807 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.860807 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 28780.860575 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 28780.860575 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 40184.792917 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 40184.792917 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78224.602283 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78224.602283 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 387452.451965 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 387452.451965 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 188618.643326 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 188618.643326 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks +system.cpu2.l1c.writebacks::total 9745 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36664 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36664 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23971 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60635 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60635 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60635 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60635 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9885 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5464 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15349 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15349 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1157350761 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1157350761 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040448870 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040448870 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2197799631 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2197799631 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2197799631 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2197799631 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 800475880 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 800475880 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1507844825 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1507844825 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2308320705 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2308320705 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805377 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805377 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954868 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858512 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858512 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 31566.407402 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 31566.407402 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 43404.483334 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 43404.483334 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 80978.844714 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80978.844714 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 275959.887445 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 275959.887445 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 150388.996352 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 150388.996352 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99687 # number of read accesses completed -system.cpu3.num_writes 54914 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22514 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.486423 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13398 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22905 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.584938 # Average number of references to valid blocks. +system.cpu3.num_reads 99181 # number of read accesses completed +system.cpu3.num_writes 54913 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22385 # number of replacements +system.cpu3.l1c.tags.tagsinuse 394.599023 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13320 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.584749 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.486423 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770481 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770481 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 351 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337490 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337490 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8775 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8775 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1091 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1091 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9866 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9866 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9866 # number of overall hits -system.cpu3.l1c.overall_hits::total 9866 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36393 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36393 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23929 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23929 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60322 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60322 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60322 # number of overall misses -system.cpu3.l1c.overall_misses::total 60322 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1101223942 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1101223942 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 999641040 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 999641040 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2100864982 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2100864982 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2100864982 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2100864982 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45168 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25020 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25020 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70188 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70188 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70188 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70188 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805725 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805725 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956395 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.956395 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859435 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859435 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859435 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859435 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 30259.224082 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 30259.224082 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 41775.295248 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 41775.295248 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 34827.508736 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 34827.508736 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 34827.508736 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 34827.508736 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1140042 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 394.599023 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.770701 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.770701 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337671 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337671 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8526 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8526 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1172 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1172 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9698 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9698 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9698 # number of overall hits +system.cpu3.l1c.overall_hits::total 9698 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36662 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36662 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23851 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23851 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60513 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60513 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60513 # number of overall misses +system.cpu3.l1c.overall_misses::total 60513 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1194465114 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1194465114 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1056306776 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1056306776 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2250771890 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2250771890 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2250771890 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2250771890 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45188 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45188 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25023 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25023 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70211 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70211 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70211 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70211 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811322 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.811322 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953163 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953163 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861873 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861873 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861873 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861873 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 32580.467896 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 32580.467896 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 44287.735357 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 44287.735357 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 37194.848875 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 37194.848875 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 37194.848875 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 37194.848875 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1130263 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 60968 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 56535 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 18.699022 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 19.992270 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9981 # number of writebacks -system.cpu3.l1c.writebacks::total 9981 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36393 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36393 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23929 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60322 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60322 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60322 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60322 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9906 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5522 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15428 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1045674368 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1045674368 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 963227618 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 963227618 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2008901986 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2008901986 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2008901986 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2008901986 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 776644993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 776644993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 2134037166 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 2134037166 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2910682159 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2910682159 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805725 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805725 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956395 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956395 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859435 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859435 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 28732.843349 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 28732.843349 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 40253.567554 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 40253.567554 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78401.473148 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78401.473148 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 386460.913799 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 386460.913799 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 188662.312613 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 188662.312613 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9719 # number of writebacks +system.cpu3.l1c.writebacks::total 9719 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36662 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36662 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23851 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60513 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60513 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60513 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60513 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9988 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5458 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15446 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15446 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1157803114 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1157803114 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1032457776 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1032457776 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2190260890 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2190260890 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2190260890 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2190260890 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 807637161 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 807637161 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1532365329 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1532365329 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2340002490 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2340002490 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811322 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811322 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953163 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953163 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861873 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861873 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 31580.467896 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 31580.467896 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 43287.819211 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 43287.819211 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 80860.748999 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80860.748999 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 280755.831623 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 280755.831623 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 151495.694031 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 151495.694031 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99646 # number of read accesses completed -system.cpu4.num_writes 55076 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22475 # number of replacements -system.cpu4.l1c.tags.tagsinuse 394.666578 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13432 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.587243 # Average number of references to valid blocks. +system.cpu4.num_reads 99531 # number of read accesses completed +system.cpu4.num_writes 55217 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22414 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.784167 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.591720 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 394.666578 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.770833 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.770833 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338590 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338590 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8683 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8683 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1163 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1163 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9846 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9846 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9846 # number of overall hits -system.cpu4.l1c.overall_hits::total 9846 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36657 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36657 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23918 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23918 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60575 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60575 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60575 # number of overall misses -system.cpu4.l1c.overall_misses::total 60575 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1108449638 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1108449638 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 999797609 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 999797609 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2108247247 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2108247247 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2108247247 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2108247247 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45340 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45340 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25081 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25081 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70421 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70421 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70421 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70421 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808491 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.808491 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953630 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953630 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860184 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860184 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860184 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860184 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 30238.416619 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 30238.416619 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 41801.053976 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 41801.053976 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 34803.916583 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 34803.916583 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 34803.916583 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 34803.916583 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1151337 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 393.784167 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.769110 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.769110 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 47 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337660 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337660 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8661 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8661 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1197 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1197 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9858 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9858 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9858 # number of overall hits +system.cpu4.l1c.overall_hits::total 9858 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36381 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36381 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24008 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24008 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60389 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60389 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60389 # number of overall misses +system.cpu4.l1c.overall_misses::total 60389 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1185615268 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1185615268 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1062060825 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1062060825 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2247676093 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2247676093 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2247676093 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2247676093 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45042 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45042 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25205 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25205 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70247 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70247 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70247 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70247 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807713 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952509 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952509 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859667 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859667 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859667 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859667 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 32588.858690 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 32588.858690 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 44237.788446 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 44237.788446 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 37219.958817 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 37219.958817 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 37219.958817 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 37219.958817 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1133314 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61602 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 56676 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 18.689929 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 19.996365 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9802 # number of writebacks -system.cpu4.l1c.writebacks::total 9802 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36657 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36657 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23918 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60575 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60575 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60575 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60575 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9982 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5360 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5360 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15342 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15342 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1052462662 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1052462662 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 963409159 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 963409159 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2015871821 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2015871821 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2015871821 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2015871821 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 780487806 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 780487806 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 2113182760 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 2113182760 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2893670566 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2893670566 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808491 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808491 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953630 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953630 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860184 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860184 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 28711.096435 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 28711.096435 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 40279.670499 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 40279.670499 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78189.521739 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78189.521739 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 394250.514925 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 394250.514925 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 188611.039369 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 188611.039369 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9784 # number of writebacks +system.cpu4.l1c.writebacks::total 9784 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36381 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36381 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24008 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24008 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60389 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60389 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60389 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60389 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 10053 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15517 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1149238268 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1149238268 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1038052825 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1038052825 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2187291093 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2187291093 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2187291093 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2187291093 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 813079130 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 813079130 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1517158795 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1517158795 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2330237925 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2330237925 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807713 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952509 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952509 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859667 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859667 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 31588.968637 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 31588.968637 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 43237.788446 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 43237.788446 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 80879.252959 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80879.252959 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 277664.493960 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 277664.493960 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 150173.224528 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 150173.224528 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99659 # number of read accesses completed -system.cpu5.num_writes 54989 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22353 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.762821 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13360 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22726 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.587873 # Average number of references to valid blocks. +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 55296 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22532 # number of replacements +system.cpu5.l1c.tags.tagsinuse 395.145821 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13497 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22906 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.589234 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.762821 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.767115 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.767115 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 325 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.728516 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337942 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337942 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8666 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8666 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1136 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1136 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9802 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9802 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9802 # number of overall hits -system.cpu5.l1c.overall_hits::total 9802 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36641 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36641 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23834 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23834 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60475 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60475 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60475 # number of overall misses -system.cpu5.l1c.overall_misses::total 60475 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1106472248 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1106472248 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 994607245 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 994607245 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2101079493 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2101079493 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2101079493 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2101079493 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45307 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45307 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24970 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24970 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70277 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70277 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70277 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70277 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808727 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808727 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954505 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954505 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.860523 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.860523 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.860523 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.860523 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 30197.654212 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 30197.654212 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 41730.605228 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 41730.605228 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 34742.943249 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 34742.943249 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 34742.943249 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 34742.943249 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1144155 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 395.145821 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.771769 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.771769 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337979 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337979 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8739 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8739 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1202 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1202 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9941 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9941 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9941 # number of overall hits +system.cpu5.l1c.overall_hits::total 9941 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36450 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36450 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23918 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23918 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60368 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60368 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60368 # number of overall misses +system.cpu5.l1c.overall_misses::total 60368 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1193062548 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1193062548 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1058341769 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1058341769 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2251404317 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2251404317 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2251404317 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2251404317 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45189 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45189 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25120 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25120 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70309 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70309 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70309 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70309 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806612 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806612 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952150 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952150 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858610 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858610 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858610 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858610 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 32731.482798 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 32731.482798 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 44248.756961 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 44248.756961 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 37294.664673 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 37294.664673 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 37294.664673 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 37294.664673 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1121436 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61191 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 56172 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 18.698093 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 19.964324 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9829 # number of writebacks -system.cpu5.l1c.writebacks::total 9829 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36641 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23834 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23834 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60475 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60475 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5460 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5460 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15394 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15394 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1050521774 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1050521774 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 958365245 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 958365245 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2008887019 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2008887019 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2008887019 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2008887019 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 778256892 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 778256892 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 2141596587 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 2141596587 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2919853479 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2919853479 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808727 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808727 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954505 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954505 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.860523 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.860523 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 28670.663301 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 28670.663301 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 40210.004405 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 40210.004405 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78342.751359 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78342.751359 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 392233.807143 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392233.807143 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 189674.774523 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 189674.774523 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9981 # number of writebacks +system.cpu5.l1c.writebacks::total 9981 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36450 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36450 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23918 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60368 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60368 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9842 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5587 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5587 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15429 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15429 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1156614548 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1156614548 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1034424769 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1034424769 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2191039317 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2191039317 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2191039317 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2191039317 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 798681353 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 798681353 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1559836698 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1559836698 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2358518051 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2358518051 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806612 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806612 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952150 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952150 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858610 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858610 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 31731.537668 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 31731.537668 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 43248.798771 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 43248.798771 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 81150.310201 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81150.310201 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 279190.388044 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279190.388044 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 152862.664528 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 152862.664528 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99691 # number of read accesses completed -system.cpu6.num_writes 55108 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22433 # number of replacements -system.cpu6.l1c.tags.tagsinuse 394.732703 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13465 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.590234 # Average number of references to valid blocks. +system.cpu6.num_reads 99879 # number of read accesses completed +system.cpu6.num_writes 55426 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22371 # number of replacements +system.cpu6.l1c.tags.tagsinuse 395.326557 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13543 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22792 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.594200 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 394.732703 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.770962 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.770962 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 339043 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 339043 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8806 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8806 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9950 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9950 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9950 # number of overall hits -system.cpu6.l1c.overall_hits::total 9950 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36628 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36628 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23944 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23944 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60572 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60572 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60572 # number of overall misses -system.cpu6.l1c.overall_misses::total 60572 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1115774950 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1115774950 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 994580574 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 994580574 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2110355524 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2110355524 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2110355524 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2110355524 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45434 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45434 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25088 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25088 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70522 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70522 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70522 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70522 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806180 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806180 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954401 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954401 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858909 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858909 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858909 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858909 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 30462.349842 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 30462.349842 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 41537.778734 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 41537.778734 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 34840.446477 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 34840.446477 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 34840.446477 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 34840.446477 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1141787 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 395.326557 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.772122 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.772122 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 339285 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 339285 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8751 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8751 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1170 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1170 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9921 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9921 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9921 # number of overall hits +system.cpu6.l1c.overall_hits::total 9921 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36633 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36633 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24021 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24021 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60654 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60654 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60654 # number of overall misses +system.cpu6.l1c.overall_misses::total 60654 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1194061806 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1194061806 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1068136243 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1068136243 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2262198049 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2262198049 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2262198049 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2262198049 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45384 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45384 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25191 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25191 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70575 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70575 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70575 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70575 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807179 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807179 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953555 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953555 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859426 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859426 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859426 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859426 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 32595.250348 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 32595.250348 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 44466.768369 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 44466.768369 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 37296.766067 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 37296.766067 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 37296.766067 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 37296.766067 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1121671 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61213 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 56232 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 18.652688 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 19.947201 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9839 # number of writebacks -system.cpu6.l1c.writebacks::total 9839 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36628 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36628 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23944 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60572 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60572 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60572 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60572 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5449 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15239 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1059827480 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1059827480 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 958175570 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 958175570 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2018003050 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2018003050 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2018003050 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2018003050 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767222409 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767222409 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 2138123651 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 2138123651 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2905346060 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2905346060 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806180 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806180 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954401 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954401 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858909 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858909 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 28934.898984 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 28934.898984 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 40017.355914 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 40017.355914 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78367.968233 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78367.968233 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 392388.264085 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392388.264085 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 190652.015224 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 190652.015224 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9808 # number of writebacks +system.cpu6.l1c.writebacks::total 9808 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36633 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36633 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24021 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24021 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60654 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60654 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60654 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60654 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9734 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15253 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1157429806 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1157429806 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1044117243 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1044117243 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2201547049 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2201547049 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2201547049 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2201547049 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 789209928 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 789209928 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1545234814 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1545234814 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2334444742 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2334444742 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807179 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807179 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953555 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953555 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859426 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859426 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 31595.277646 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 31595.277646 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 43466.851630 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 43466.851630 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 81077.658517 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81077.658517 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 279984.564957 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279984.564957 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 153048.235888 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 153048.235888 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99881 # number of read accesses completed -system.cpu7.num_writes 55258 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22490 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.773487 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13394 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22887 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.585223 # Average number of references to valid blocks. +system.cpu7.num_reads 99237 # number of read accesses completed +system.cpu7.num_writes 54706 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22568 # number of replacements +system.cpu7.l1c.tags.tagsinuse 396.130968 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13545 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22967 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.589759 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.773487 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.771042 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.771042 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 361 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338728 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338728 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8705 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8705 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1114 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1114 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9819 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9819 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9819 # number of overall hits -system.cpu7.l1c.overall_hits::total 9819 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36637 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36637 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23983 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23983 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60620 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60620 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60620 # number of overall misses -system.cpu7.l1c.overall_misses::total 60620 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1106293724 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1106293724 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1002572296 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1002572296 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2108866020 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2108866020 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2108866020 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2108866020 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45342 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45342 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25097 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25097 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70439 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70439 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70439 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70439 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808015 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.808015 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955612 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955612 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860603 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860603 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860603 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860603 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 30196.078391 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 30196.078391 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 41803.456448 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 41803.456448 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 34788.288024 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 34788.288024 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 34788.288024 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 34788.288024 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1141532 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 396.130968 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.773693 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.773693 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 336 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337631 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337631 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8763 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8763 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1110 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1110 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9873 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9873 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9873 # number of overall hits +system.cpu7.l1c.overall_hits::total 9873 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36422 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36422 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23951 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23951 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60373 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60373 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60373 # number of overall misses +system.cpu7.l1c.overall_misses::total 60373 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1187262746 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1187262746 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1066556279 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1066556279 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2253819025 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2253819025 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2253819025 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2253819025 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45185 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45185 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25061 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70246 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70246 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70246 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70246 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806064 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.806064 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955708 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955708 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859451 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859451 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859451 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859451 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 32597.406677 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 32597.406677 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 44530.761931 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 44530.761931 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 37331.572474 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 37331.572474 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 37331.572474 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 37331.572474 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1126172 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61288 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 56351 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 18.625702 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 19.984951 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9784 # number of writebacks -system.cpu7.l1c.writebacks::total 9784 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36637 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23983 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60620 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60620 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60620 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60620 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9862 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5465 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5465 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15327 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15327 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1050368666 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1050368666 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 966121280 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 966121280 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2016489946 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2016489946 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2016489946 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2016489946 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 770060879 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 770060879 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 2135523645 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 2135523645 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2905584524 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2905584524 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808015 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808015 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955612 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955612 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860603 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860603 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 28669.614488 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 28669.614488 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 40283.587541 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 40283.587541 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78083.642162 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78083.642162 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 390763.704483 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 390763.704483 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 189572.944738 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 189572.944738 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9950 # number of writebacks +system.cpu7.l1c.writebacks::total 9950 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36422 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36422 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23951 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23951 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60373 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60373 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60373 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60373 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9901 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9901 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5444 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15345 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15345 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1150841746 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1150841746 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1042608279 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1042608279 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2193450025 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2193450025 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2193450025 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2193450025 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 802753372 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 802753372 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1502766880 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1502766880 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2305520252 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2305520252 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806064 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806064 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955708 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955708 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859451 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859451 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 31597.434133 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 31597.434133 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 43530.887186 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 43530.887186 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 81078.009494 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81078.009494 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 276040.940485 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 276040.940485 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 150245.699055 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 150245.699055 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12865 # number of replacements -system.l2c.tags.tagsinuse 778.482244 # Cycle average of tags in use -system.l2c.tags.total_refs 150454 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13664 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.010978 # Average number of references to valid blocks. +system.l2c.tags.replacements 13238 # number of replacements +system.l2c.tags.tagsinuse 783.486176 # Cycle average of tags in use +system.l2c.tags.total_refs 163749 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14027 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.673843 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 726.215945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 5.941011 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.607450 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.516565 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.767835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.065793 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.555833 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.650782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.161030 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.709195 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.005802 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006453 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006364 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006609 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.005924 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006402 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006495 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006993 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.760237 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 799 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 529 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.780273 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1961721 # 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accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.713342 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.726877 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.722422 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.723266 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.714984 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.727835 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.730572 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.723218 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.059584 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.058895 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.060645 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.059211 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.063947 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.059320 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.061640 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.060037 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.060408 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.298272 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.291916 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2 0.298855 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.298473 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.294470 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.300525 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.291909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.303873 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.297448 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.296240 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.295239 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu3 0.295660 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.301397 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.297218 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.301521 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.301729 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298321 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.298272 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.291916 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2 0.298855 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.298473 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.294470 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.300525 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.291909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.303873 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.297448 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60390.740506 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61394.381368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 61453.606368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61192.859112 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 60431.632777 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 61890.053812 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61174.914706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 60878.852436 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61108.128143 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 30275.160635 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 30610.754810 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 30825.884086 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 30288.479902 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28343.454455 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 30092.078708 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29379.632301 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29716.782717 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29945.839634 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54781.955130 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54618.652404 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54659.601702 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54677.013734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54851.685137 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54590.629296 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54679.671648 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54794.138511 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54706.996788 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55460.636416 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55510.229841 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55549.921676 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55489.007443 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55550.636951 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55507.683756 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55535.136549 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55580.935532 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55523.253539 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55460.636416 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55510.229841 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55549.921676 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55489.007443 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55550.636951 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55507.683756 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55535.136549 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55580.935532 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55523.253539 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 8422 # number of cycles access was blocked +system.l2c.overall_miss_rate::cpu3 0.295660 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.301397 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.297218 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.301521 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.301729 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.298321 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29972.358121 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 30263.732620 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 30704.012422 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29711.153003 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 29288.762447 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29602.095029 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29495.889265 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29497.087379 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29816.566733 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54515.956634 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54589.978606 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54599.434773 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54578.288282 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54533.253863 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54454.277291 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54767.848214 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54681.721168 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54590.372681 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 60282.178886 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 60444.527326 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 60422.884451 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 60581.166911 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 60926.122951 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61696.370968 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 59855.144068 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 59990.412281 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 60524.869526 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55255.577393 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55350.586836 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55358.638460 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55351.866792 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55401.128524 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55375.237181 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55433.370288 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55357.282977 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55360.731373 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55255.577393 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55350.586836 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55358.638460 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55351.866792 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55401.128524 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55375.237181 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55433.370288 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55357.282977 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55360.731373 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 8992 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1138 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1204 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.400703 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.468439 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6144 # number of writebacks -system.l2c.writebacks::total 6144 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.writebacks::writebacks 6188 # number of writebacks +system.l2c.writebacks::total 6188 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 23 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 63 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 628 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 680 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 688 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 646 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 652 # number of ReadReq MSHR misses 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number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4588 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4530 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4579 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4586 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4599 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4651 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4482 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4697 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36712 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5216 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5210 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5267 # number of demand (read+write) MSHR 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-system.l2c.overall_mshr_misses::cpu6 5158 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5390 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42041 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 10009 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9898 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 79337 # number of ReadReq MSHR uncacheable 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of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420391962 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 422439462 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417792957 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 418505281 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 421118468 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 419294453 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413123964 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416090788 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3348757335 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 237106474 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237782975 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 241705476 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 241076980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 235943478 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 241042480 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 238750464 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 240064477 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1913472804 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 657498436 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 660222437 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 659498433 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 659582261 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 657061946 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 660336933 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 651874428 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 656155265 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5262230139 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055477 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.059623 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.060499 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.057530 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.056918 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058876 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061338 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.058679 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886593 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877489 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.886275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885033 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.873803 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875055 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.875445 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878841 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.879829 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726985 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.721452 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730070 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.724830 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717361 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.725925 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.715746 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.726415 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.723603 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297002 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297002 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48501.511146 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49560.205882 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49494.098837 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49356.716718 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48690.865031 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49984.903904 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49255.828402 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 48963.115440 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49232.696003 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42023.052058 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42024.665022 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41973.691740 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.872059 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42061.253984 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42026.234107 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41929.365346 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42011.484515 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41999.219866 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42667.819093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42532.000221 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42548.219043 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42572.928914 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42752.761252 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42518.913352 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42577.411200 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42711.187992 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42610.576487 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42224.986139 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42205.960835 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42209.836027 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42247.656067 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42187.784813 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42208.018220 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42198.566292 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42191.319002 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42209.276063 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 43795.063539 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 43742.269132 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 43994.444121 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 43681.279217 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44035.736842 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44163.151337 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 43823.506608 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 43951.753387 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 43898.066118 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 42778.037476 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 42746.677695 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 42846.831666 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 42760.600389 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 42833.242894 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 42901.308017 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 42779.526710 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 42818.798290 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 42808.113328 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 26 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 12 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 6 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 6 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 46 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1198 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1198 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2044 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2057 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2093 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2098 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2109 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2051 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2068 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2059 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16579 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4532 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4674 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4616 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4656 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4680 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4700 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4687 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 37172 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0 678 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1 673 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2 700 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3 679 # number of ReadSharedReq MSHR misses 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of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5365 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42675 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5305 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5205 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5374 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5295 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5376 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5353 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5402 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5365 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42675 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9717 # number of ReadReq MSHR uncacheable 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248490489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 246535993 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 247729989 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 247792491 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 253848482 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 250349488 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 246216989 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1985291905 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 674024963 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 679200451 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 683178468 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 689016970 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 691800463 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 688094460 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 680352960 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 683847290 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5469516025 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880276 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877186 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.899441 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.893526 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.898977 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.884433 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.877759 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885591 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.887147 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725235 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713027 # mshr miss rate for ReadExReq accesses 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# mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062899 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.058537 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061118 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059510 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059908 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for demand accesses 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+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43986.820074 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44573.473093 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44604.912621 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44600.868207 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44580.796577 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44544.665808 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44462.600855 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44780.204043 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44713.559633 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 44607.895405 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 50505.820059 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 50619.531947 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 50442.060000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 50725.974963 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51454.061111 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52219.799406 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 50096.783476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 50259.501475 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50789.933309 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44221.156633 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44202.582307 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44181.167156 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44181.716159 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44166.713618 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44121.720992 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44175.413191 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44200.616200 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44181.280211 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45634.662682 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45295.386256 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45128.316493 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45396.736119 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45350.016654 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45451.832050 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45361.385758 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45227.220610 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45355.293452 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44723.307213 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44596.221339 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44518.341457 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44611.004856 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44583.390024 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44603.257924 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44604.534190 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44564.828283 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 44600.323116 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 252480 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 249408 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 253876 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 250804 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 84654 # Transaction distribution -system.membus.trans_dist::ReadResp 84652 # Transaction distribution -system.membus.trans_dist::WriteReq 43588 # Transaction distribution -system.membus.trans_dist::WriteResp 43585 # Transaction distribution -system.membus.trans_dist::Writeback 6143 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60492 # Transaction distribution -system.membus.trans_dist::UpgradeResp 49595 # Transaction distribution -system.membus.trans_dist::ReadExReq 50638 # Transaction distribution -system.membus.trans_dist::ReadExResp 3207 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 426554 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1061863 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1061863 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58325 # Total snoops (count) -system.membus.snoop_fanout::samples 252480 # Request fanout histogram +system.membus.trans_dist::ReadReq 78861 # Transaction distribution +system.membus.trans_dist::ReadResp 84355 # Transaction distribution +system.membus.trans_dist::WriteReq 43772 # Transaction distribution +system.membus.trans_dist::WriteResp 43770 # Transaction distribution +system.membus.trans_dist::Writeback 6188 # Transaction distribution +system.membus.trans_dist::CleanEvict 1234 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61487 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50676 # Transaction distribution +system.membus.trans_dist::ReadExReq 49401 # Transaction distribution +system.membus.trans_dist::ReadExResp 3090 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5496 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 428330 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1068167 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1068167 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57121 # Total snoops (count) +system.membus.snoop_fanout::samples 253876 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 252480 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253876 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 252480 # Request fanout histogram -system.membus.reqLayer0.occupancy 472884580 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 59.9 # Layer utilization (%) -system.membus.respLayer0.occupancy 313892142 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 39.7 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 684630 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 383351 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 298207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 371695 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371689 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43589 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43585 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75954 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29169 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29167 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162397 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162391 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120783 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120664 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120646 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120853 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120726 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120516 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120736 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 965538 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1750933 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1748576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754368 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1762730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757509 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1755676 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14042920 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 324098 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 684630 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.384232 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.250303 # Request fanout histogram +system.membus.snoop_fanout::total 253876 # Request fanout histogram +system.membus.reqLayer0.occupancy 481009549 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 317350499 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 35.7 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 783985 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 389410 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 391503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 13238 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 4575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 8663 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78862 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371257 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43772 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43769 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83329 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20018 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29498 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29497 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162169 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162167 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292402 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122283 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122863 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122791 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122959 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122669 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122503 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 981417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781215 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778494 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776817 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1770963 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1771805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1794946 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778453 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1777585 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14230278 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335326 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 797223 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.523507 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.320965 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 176832 25.83% 25.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 250927 36.65% 62.48% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141295 20.64% 83.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 69195 10.11% 93.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 30377 4.44% 97.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11672 1.70% 99.37% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3607 0.53% 99.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 725 0.11% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 184121 23.10% 23.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 277567 34.82% 57.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 172653 21.66% 79.57% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 93165 11.69% 91.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 44731 5.61% 96.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 17914 2.25% 99.11% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 5826 0.73% 99.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 1211 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 35 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 684630 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 782327755 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100591456 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 12.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100721944 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 100768962 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100555978 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 12.7 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100847968 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100723976 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 100740497 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 12.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100846524 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 12.8 # Layer utilization (%) +system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 797223 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 882991225 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 99.3 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100686388 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100571959 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100903359 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 11.4 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100786975 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100705827 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100586898 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100884775 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 11.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100465612 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index ff9b64e46..d439f20bd 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1766 +1,1775 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000473 # Number of seconds simulated -sim_ticks 473398500 # Number of ticks simulated -final_tick 473398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000517 # Number of seconds simulated +sim_ticks 516502000 # Number of ticks simulated +final_tick 516502000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 74773462 # Simulator tick rate (ticks/s) -host_mem_usage 221944 # Number of bytes of host memory used -host_seconds 6.33 # Real time elapsed on the host +host_tick_rate 87177041 # Simulator tick rate (ticks/s) +host_mem_usage 277532 # Number of bytes of host memory used +host_seconds 5.92 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 85610 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 86349 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 81279 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 82686 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83314 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 81031 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 83113 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 86498 # Number of bytes read from this memory -system.physmem.bytes_read::total 669880 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 430080 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5517 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5460 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5549 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5366 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5497 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5427 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5336 # Number of bytes written to this memory -system.physmem.bytes_written::total 473601 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10845 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10992 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10927 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10898 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87697 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6720 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5517 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5460 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5549 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5366 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5497 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5427 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5336 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50241 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 180841300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 182402352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 171692559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 174664685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 175991263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 171168688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 175566674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 182717098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1415044619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 908494640 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 11654029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 11533623 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 11721626 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 11335059 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 11341396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 11611782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 11463915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 11271688 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1000427758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 908494640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 192495329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 193935976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 183414185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 185999744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 187332659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 182780469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 187030588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 193988785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2415472377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 77818 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 80958 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 77616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 81564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 77320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 77018 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 77760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 78103 # Number of bytes read from this memory +system.physmem.bytes_read::total 628157 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 397760 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5585 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5520 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5375 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5451 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5446 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5475 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5563 # Number of bytes written to this memory +system.physmem.bytes_written::total 441591 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10975 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10902 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11130 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10918 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10819 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87365 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6215 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5585 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5520 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5375 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5451 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5416 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5446 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5475 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5563 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50046 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 150663502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 156742859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 150272409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 157916136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 149699324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 149114621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 150551208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 151215291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1216175349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 770103504 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10813124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10687277 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10406542 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10553686 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10485923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10544006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10600153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10770529 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 854964744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 770103504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 161476625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 167430136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 160678952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 168469822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 160185246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 159658627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 161151360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 161985820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2071140092 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99308 # number of read accesses completed -system.cpu0.num_writes 55247 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22271 # number of replacements -system.cpu0.l1c.tags.tagsinuse 390.476059 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13537 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22673 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.597054 # Average number of references to valid blocks. +system.cpu0.num_reads 99458 # number of read accesses completed +system.cpu0.num_writes 55230 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22190 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.694293 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13468 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22585 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.596325 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 390.476059 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.762649 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.762649 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337706 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337706 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8778 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8778 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1202 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1202 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9980 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9980 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9980 # number of overall hits -system.cpu0.l1c.overall_hits::total 9980 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36312 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36312 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23969 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23969 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60281 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60281 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60281 # number of overall misses -system.cpu0.l1c.overall_misses::total 60281 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 585914746 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 585914746 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 661973304 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 661973304 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1247888050 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1247888050 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1247888050 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1247888050 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45090 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45090 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25171 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25171 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70261 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70261 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70261 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70261 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805323 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.805323 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952247 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.952247 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.857958 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.857958 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.857958 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.857958 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16135.568022 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16135.568022 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27617.894113 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 27617.894113 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20701.183623 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20701.183623 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20701.183623 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20701.183623 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 772989 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.694293 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765028 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765028 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337088 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337088 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1212 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1212 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9897 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9897 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9897 # number of overall hits +system.cpu0.l1c.overall_hits::total 9897 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36327 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36327 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23903 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23903 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60230 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60230 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60230 # number of overall misses +system.cpu0.l1c.overall_misses::total 60230 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 590238894 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 590238894 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 671544552 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 671544552 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1261783446 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1261783446 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1261783446 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1261783446 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45012 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45012 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25115 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25115 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70127 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70127 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70127 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70127 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807051 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807051 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951742 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.951742 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858870 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858870 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858870 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858870 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16247.939384 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16247.939384 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28094.571895 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 28094.571895 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20949.417998 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20949.417998 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20949.417998 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20949.417998 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 738586 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66053 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 60679 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.702557 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.172020 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9819 # number of writebacks -system.cpu0.l1c.writebacks::total 9819 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36312 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36312 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23969 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60281 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60281 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60281 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60281 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9835 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9835 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5519 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15354 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15354 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 529167946 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 529167946 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 625061532 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 625061532 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1154229478 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1154229478 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1154229478 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1154229478 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 639072193 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 639072193 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 970312557 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 970312557 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1609384750 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1609384750 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805323 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805323 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952247 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952247 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857958 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.857958 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857958 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.857958 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14572.811908 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14572.811908 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 26077.914473 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 26077.914473 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19147.483917 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19147.483917 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 64979.379054 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64979.379054 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 175813.110527 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175813.110527 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 104818.597760 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 104818.597760 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9780 # number of writebacks +system.cpu0.l1c.writebacks::total 9780 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36327 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23903 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60230 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60230 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60230 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60230 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9914 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9914 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5586 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5586 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15500 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15500 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 553912894 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 553912894 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 647643552 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 647643552 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1201556446 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1201556446 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1201556446 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1201556446 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 648458134 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 648458134 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 875575663 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 875575663 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1524033797 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1524033797 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807051 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807051 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951742 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951742 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858870 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858870 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858870 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858870 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15247.966912 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15247.966912 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27094.655566 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27094.655566 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19949.467807 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19949.467807 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19949.467807 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19949.467807 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65408.324995 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65408.324995 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 156744.658611 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156744.658611 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 98324.761097 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 98324.761097 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98972 # number of read accesses completed -system.cpu1.num_writes 54740 # number of write accesses completed -system.cpu1.l1c.tags.replacements 21894 # number of replacements -system.cpu1.l1c.tags.tagsinuse 389.013692 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13227 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22299 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.593166 # Average number of references to valid blocks. +system.cpu1.num_reads 99343 # number of read accesses completed +system.cpu1.num_writes 54840 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22376 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.102021 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13319 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.585142 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 389.013692 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.759792 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.759792 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 335323 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 335323 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8521 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8521 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9673 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9673 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9673 # number of overall hits -system.cpu1.l1c.overall_hits::total 9673 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36191 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36191 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23860 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23860 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60051 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60051 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60051 # number of overall misses -system.cpu1.l1c.overall_misses::total 60051 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 587357926 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 587357926 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 665550173 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 665550173 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1252908099 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1252908099 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1252908099 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1252908099 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44712 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44712 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25012 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 69724 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 69724 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 69724 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 69724 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809425 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.809425 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953942 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.861267 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.861267 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.861267 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.861267 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16229.392004 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16229.392004 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27893.972045 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 27893.972045 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20864.067193 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20864.067193 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20864.067193 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20864.067193 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 781068 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.102021 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.767777 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.767777 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 337670 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 337670 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8618 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8618 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1175 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1175 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9793 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9793 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9793 # number of overall hits +system.cpu1.l1c.overall_hits::total 9793 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36716 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36716 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23707 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23707 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60423 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60423 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60423 # number of overall misses +system.cpu1.l1c.overall_misses::total 60423 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 601446212 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 601446212 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 664813201 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 664813201 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1266259413 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1266259413 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1266259413 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1266259413 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45334 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45334 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24882 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24882 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70216 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70216 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70216 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70216 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809900 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.809900 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.952777 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.952777 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860530 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860530 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860530 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860530 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16381.038566 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16381.038566 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28042.907200 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 28042.907200 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20956.579663 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20956.579663 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20956.579663 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20956.579663 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 733404 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 60457 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.805922 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.131002 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9676 # number of writebacks -system.cpu1.l1c.writebacks::total 9676 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36191 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36191 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23860 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60051 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60051 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60051 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60051 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9870 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9870 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5462 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5462 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15332 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15332 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 530766130 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 530766130 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 628779775 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 628779775 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1159545905 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1159545905 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1159545905 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1159545905 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 639204350 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 639204350 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 954877634 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 954877634 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1594081984 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1594081984 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809425 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809425 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953942 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861267 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.861267 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861267 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.861267 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14665.693957 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14665.693957 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 26352.882439 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 26352.882439 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19309.352134 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19309.352134 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19309.352134 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19309.352134 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 64762.345491 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64762.345491 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 174821.976199 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174821.976199 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103970.909470 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103970.909470 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9757 # number of writebacks +system.cpu1.l1c.writebacks::total 9757 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36716 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36716 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23707 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23707 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60423 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60423 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9790 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5520 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5520 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15310 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15310 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 564731212 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 564731212 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 641108201 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 641108201 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1205839413 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1205839413 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1205839413 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1205839413 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 639869720 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 639869720 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 879270140 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 879270140 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1519139860 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1519139860 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809900 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809900 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952777 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952777 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860530 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860530 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860530 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860530 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15381.065802 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15381.065802 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27042.991564 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27042.991564 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19956.629313 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19956.629313 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19956.629313 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19956.629313 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65359.521961 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65359.521961 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159288.068841 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159288.068841 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 99225.333769 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 99225.333769 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99459 # number of read accesses completed -system.cpu2.num_writes 55455 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22538 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.681778 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22938 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.590810 # Average number of references to valid blocks. +system.cpu2.num_reads 99555 # number of read accesses completed +system.cpu2.num_writes 54722 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22333 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.011664 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13583 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22742 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.597265 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.681778 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.766957 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337495 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337495 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8694 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8694 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1182 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1182 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9876 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9876 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9876 # number of overall hits -system.cpu2.l1c.overall_hits::total 9876 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36455 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36455 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23891 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23891 # number of WriteReq misses +system.cpu2.l1c.tags.occ_blocks::cpu2 393.011664 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.767601 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.767601 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337922 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337922 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8790 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8790 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1177 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9967 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9967 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9967 # number of overall hits +system.cpu2.l1c.overall_hits::total 9967 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36445 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36445 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23901 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23901 # number of WriteReq misses system.cpu2.l1c.demand_misses::cpu2 60346 # number of demand (read+write) misses system.cpu2.l1c.demand_misses::total 60346 # number of demand (read+write) misses system.cpu2.l1c.overall_misses::cpu2 60346 # number of overall misses system.cpu2.l1c.overall_misses::total 60346 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 592802045 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 592802045 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 663383699 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 663383699 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1256185744 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1256185744 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1256185744 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1256185744 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45149 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45149 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25073 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70222 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70222 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70222 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70222 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807438 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.807438 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952858 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.952858 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859360 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859360 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859360 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859360 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16261.199973 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16261.199973 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27767.096354 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 27767.096354 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 20816.387896 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 20816.387896 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 20816.387896 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 20816.387896 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 773062 # number of cycles access was blocked +system.cpu2.l1c.ReadReq_miss_latency::cpu2 601110816 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 601110816 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 668105531 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 668105531 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1269216347 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1269216347 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1269216347 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1269216347 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45235 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45235 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25078 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25078 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70313 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70313 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70313 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70313 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805681 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805681 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953066 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953066 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858248 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858248 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858248 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858248 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16493.642914 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16493.642914 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27953.036735 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 27953.036735 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21032.319408 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21032.319408 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21032.319408 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21032.319408 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 742378 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66064 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 60996 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.701713 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.170929 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9793 # number of writebacks -system.cpu2.l1c.writebacks::total 9793 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36455 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36455 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23891 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23891 # number of WriteReq MSHR misses +system.cpu2.l1c.writebacks::writebacks 9726 # number of writebacks +system.cpu2.l1c.writebacks::total 9726 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36445 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36445 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23901 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23901 # number of WriteReq MSHR misses system.cpu2.l1c.demand_mshr_misses::cpu2 60346 # number of demand (read+write) MSHR misses system.cpu2.l1c.demand_mshr_misses::total 60346 # number of demand (read+write) MSHR misses system.cpu2.l1c.overall_mshr_misses::cpu2 60346 # number of overall MSHR misses system.cpu2.l1c.overall_mshr_misses::total 60346 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9727 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9727 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5550 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5550 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15277 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535820289 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535820289 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 626605165 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 626605165 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162425454 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1162425454 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162425454 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1162425454 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 629981617 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 629981617 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 971621622 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 971621622 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1601603239 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1601603239 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807438 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807438 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952858 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952858 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859360 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859360 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859360 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859360 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14698.128899 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14698.128899 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26227.665857 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26227.665857 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19262.676134 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19262.676134 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19262.676134 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19262.676134 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 64766.281176 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64766.281176 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 175066.958919 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175066.958919 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 104837.549192 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 104837.549192 # average overall mshr uncacheable latency +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9904 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5377 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5377 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15281 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 564666816 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 564666816 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 644204531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 644204531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1208871347 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1208871347 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1208871347 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1208871347 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 647672238 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 647672238 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 840893759 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 840893759 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1488565997 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1488565997 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805681 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805681 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953066 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953066 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858248 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858248 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858248 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858248 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15493.670353 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15493.670353 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26953.036735 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26953.036735 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20032.335979 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20032.335979 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20032.335979 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20032.335979 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65395.015953 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65395.015953 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 156387.159940 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156387.159940 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97412.865454 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97412.865454 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99575 # number of read accesses completed -system.cpu3.num_writes 55091 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22304 # number of replacements -system.cpu3.l1c.tags.tagsinuse 392.069306 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13533 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22710 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.595905 # Average number of references to valid blocks. +system.cpu3.num_reads 99759 # number of read accesses completed +system.cpu3.num_writes 54933 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22211 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.604025 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13361 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22604 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.591090 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 392.069306 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.765760 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.765760 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 336765 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 336765 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8633 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8633 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1152 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1152 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9785 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9785 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9785 # number of overall hits -system.cpu3.l1c.overall_hits::total 9785 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36428 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36428 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23860 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23860 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60288 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60288 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60288 # number of overall misses -system.cpu3.l1c.overall_misses::total 60288 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 584499068 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 584499068 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 664565432 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 664565432 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1249064500 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1249064500 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1249064500 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1249064500 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45061 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45061 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25012 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70073 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70073 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70073 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70073 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808415 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.808415 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953942 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860360 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860360 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860360 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860360 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16045.324146 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16045.324146 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27852.700419 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 27852.700419 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20718.293856 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20718.293856 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20718.293856 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20718.293856 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 775679 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.604025 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.764852 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.764852 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336889 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336889 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8685 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8685 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1067 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1067 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9752 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9752 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9752 # number of overall hits +system.cpu3.l1c.overall_hits::total 9752 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36549 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36549 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23764 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23764 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60313 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60313 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60313 # number of overall misses +system.cpu3.l1c.overall_misses::total 60313 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 596458593 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 596458593 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 667670467 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 667670467 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1264129060 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1264129060 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1264129060 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1264129060 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45234 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24831 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24831 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70065 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70065 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70065 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70065 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807998 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807998 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.957030 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.957030 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860815 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860815 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860815 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860815 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16319.423049 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16319.423049 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28095.878935 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 28095.878935 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20959.479051 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20959.479051 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20959.479051 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20959.479051 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 744732 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66211 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61238 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.715259 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.161272 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9857 # number of writebacks -system.cpu3.l1c.writebacks::total 9857 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36428 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36428 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23860 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60288 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60288 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60288 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60288 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9854 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9854 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5367 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5367 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15221 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 527611348 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 527611348 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 627817964 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 627817964 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155429312 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1155429312 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155429312 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1155429312 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639378023 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639378023 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962583192 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962583192 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1601961215 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1601961215 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808415 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808415 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953942 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860360 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860360 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860360 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860360 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14483.675964 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14483.675964 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 26312.571836 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 26312.571836 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19165.162420 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19165.162420 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19165.162420 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19165.162420 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 64885.125127 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64885.125127 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 179352.187814 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179352.187814 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 105246.778464 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 105246.778464 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9780 # number of writebacks +system.cpu3.l1c.writebacks::total 9780 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36549 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36549 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23764 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23764 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60313 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60313 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60313 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60313 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 10012 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 10012 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5455 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15467 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15467 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559909593 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559909593 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 643907467 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 643907467 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1203817060 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1203817060 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1203817060 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1203817060 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 654349566 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 654349566 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 848349724 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 848349724 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1502699290 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1502699290 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807998 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807998 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.957030 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.957030 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860815 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860815 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860815 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860815 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15319.423049 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15319.423049 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27095.921015 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27095.921015 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19959.495631 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19959.495631 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19959.495631 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19959.495631 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65356.528765 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65356.528765 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155517.822915 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155517.822915 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97155.187819 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97155.187819 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99348 # number of read accesses completed -system.cpu4.num_writes 54723 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22403 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.522543 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13385 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.587448 # Average number of references to valid blocks. +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 55127 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22421 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.948683 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13931 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22818 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.610527 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.522543 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.764692 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.764692 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 382 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.746094 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337332 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337332 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8635 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8635 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1108 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1108 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9743 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9743 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9743 # number of overall hits -system.cpu4.l1c.overall_hits::total 9743 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36706 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36706 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23706 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23706 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60412 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60412 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60412 # number of overall misses -system.cpu4.l1c.overall_misses::total 60412 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 597809741 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 597809741 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 658168265 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 658168265 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1255978006 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1255978006 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1255978006 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1255978006 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45341 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45341 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24814 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24814 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70155 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70155 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809554 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.809554 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955348 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.955348 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.861122 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.861122 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.861122 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.861122 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16286.431128 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16286.431128 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27763.784063 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 27763.784063 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20790.207343 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20790.207343 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20790.207343 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20790.207343 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 777995 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.948683 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.767478 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.767478 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 339409 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 339409 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 9015 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 9015 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1217 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1217 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 10232 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 10232 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 10232 # number of overall hits +system.cpu4.l1c.overall_hits::total 10232 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36534 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36534 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23911 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23911 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60445 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60445 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60445 # number of overall misses +system.cpu4.l1c.overall_misses::total 60445 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 594216920 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 594216920 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 670376038 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 670376038 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1264592958 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1264592958 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1264592958 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1264592958 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45549 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45549 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25128 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25128 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70677 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70677 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70677 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70677 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.802081 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.802081 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.951568 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.951568 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.855229 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.855229 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.855229 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.855229 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16264.764877 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16264.764877 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28036.302873 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 28036.302873 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20921.382381 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20921.382381 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20921.382381 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20921.382381 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 737141 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66371 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 60832 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.721912 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.117652 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9776 # number of writebacks -system.cpu4.l1c.writebacks::total 9776 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36706 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36706 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23706 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23706 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60412 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60412 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60412 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60412 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9778 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5370 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5370 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15148 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15148 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 540346315 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 540346315 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 621672271 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 621672271 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1162018586 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1162018586 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1162018586 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1162018586 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 636494546 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636494546 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 958781259 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 958781259 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1595275805 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1595275805 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809554 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809554 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955348 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955348 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861122 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.861122 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861122 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.861122 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14720.926143 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14720.926143 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 26224.258458 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 26224.258458 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65094.553692 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65094.553692 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 178543.996089 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 178543.996089 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 105312.635661 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 105312.635661 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9985 # number of writebacks +system.cpu4.l1c.writebacks::total 9985 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36534 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36534 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23911 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23911 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60445 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60445 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60445 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60445 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9865 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9865 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5418 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5418 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15283 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15283 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 557683920 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 557683920 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 646466038 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 646466038 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1204149958 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1204149958 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1204149958 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1204149958 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 645821695 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 645821695 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 857369844 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 857369844 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1503191539 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1503191539 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.802081 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802081 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.951568 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.951568 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855229 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.855229 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855229 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.855229 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15264.792248 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15264.792248 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27036.344695 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27036.344695 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19921.415469 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19921.415469 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19921.415469 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19921.415469 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65465.959959 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65465.959959 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 158244.710963 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158244.710963 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 98357.098672 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 98357.098672 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99076 # number of read accesses completed -system.cpu5.num_writes 54802 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22210 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.101349 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13412 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22600 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.593451 # Average number of references to valid blocks. +system.cpu5.num_reads 99788 # number of read accesses completed +system.cpu5.num_writes 55138 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22475 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.735284 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13651 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.596817 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.101349 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.765823 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.765823 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 335763 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 335763 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8687 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8687 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1188 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1188 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9875 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9875 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9875 # number of overall hits -system.cpu5.l1c.overall_hits::total 9875 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36386 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36386 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23589 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23589 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59975 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59975 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59975 # number of overall misses -system.cpu5.l1c.overall_misses::total 59975 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 587220514 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 587220514 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 653847941 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 653847941 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1241068455 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1241068455 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1241068455 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1241068455 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45073 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45073 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24777 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24777 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69850 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69850 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69850 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69850 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807268 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952052 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952052 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858626 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858626 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858626 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858626 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16138.638872 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16138.638872 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27718.340794 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 27718.340794 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20693.096373 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20693.096373 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20693.096373 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20693.096373 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 773798 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.735284 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.767061 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.767061 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 340255 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 340255 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8878 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8878 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1131 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1131 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 10009 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 10009 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 10009 # number of overall hits +system.cpu5.l1c.overall_hits::total 10009 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36858 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36858 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23929 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23929 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60787 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60787 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60787 # number of overall misses +system.cpu5.l1c.overall_misses::total 60787 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 604018831 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 604018831 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 667551562 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 667551562 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1271570393 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1271570393 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1271570393 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1271570393 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45736 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45736 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25060 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25060 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70796 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70796 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70796 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70796 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805886 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.805886 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954868 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858622 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858622 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858622 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858622 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16387.726708 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16387.726708 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27897.177567 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 27897.177567 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20918.459424 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20918.459424 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20918.459424 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20918.459424 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 731203 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 65921 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 60676 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.738262 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.050943 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9805 # number of writebacks -system.cpu5.l1c.writebacks::total 9805 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36386 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36386 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23589 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23589 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59975 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59975 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59975 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59975 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9927 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9927 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5497 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5497 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15424 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15424 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 530387712 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 530387712 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 617501507 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 617501507 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1147889219 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1147889219 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1147889219 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1147889219 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 644126924 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 644126924 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 971277615 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 971277615 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1615404539 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1615404539 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807268 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952052 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952052 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858626 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858626 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858626 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858626 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14576.697411 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14576.697411 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26177.519479 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26177.519479 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19139.461759 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19139.461759 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 64886.362849 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64886.362849 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 176692.307622 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176692.307622 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 104733.178099 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 104733.178099 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9872 # number of writebacks +system.cpu5.l1c.writebacks::total 9872 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36858 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36858 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23929 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60787 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60787 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60787 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60787 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9627 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9627 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5446 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5446 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15073 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567160831 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567160831 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 643622562 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 643622562 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1210783393 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1210783393 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1210783393 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1210783393 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632098852 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632098852 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 869172204 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 869172204 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1501271056 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1501271056 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805886 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805886 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954868 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858622 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858622 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858622 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858622 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15387.726708 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15387.726708 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26897.177567 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26897.177567 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19918.459424 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19918.459424 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19918.459424 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19918.459424 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65658.964579 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65658.964579 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 159598.274697 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159598.274697 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 99600.016984 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 99600.016984 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 55196 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22166 # number of replacements -system.cpu6.l1c.tags.tagsinuse 390.500017 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13797 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22571 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.611271 # Average number of references to valid blocks. +system.cpu6.num_reads 99577 # number of read accesses completed +system.cpu6.num_writes 55267 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22184 # number of replacements +system.cpu6.l1c.tags.tagsinuse 392.209079 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13575 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22573 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.601382 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 390.500017 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.762695 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.762695 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338189 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338189 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8999 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8999 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1089 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1089 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 10088 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 10088 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 10088 # number of overall hits -system.cpu6.l1c.overall_hits::total 10088 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36489 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36489 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23831 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23831 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60320 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60320 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60320 # number of overall misses -system.cpu6.l1c.overall_misses::total 60320 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 591265797 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 591265797 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 669884291 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 669884291 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1261150088 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1261150088 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1261150088 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1261150088 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45488 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45488 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24920 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24920 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70408 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70408 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70408 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70408 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.802168 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.802168 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956300 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956300 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.856721 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.856721 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.856721 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.856721 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16203.946313 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16203.946313 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28109.785196 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 28109.785196 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 20907.660610 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 20907.660610 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 20907.660610 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 20907.660610 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 779089 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 392.209079 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.766033 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.766033 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337224 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337224 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8787 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8787 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1092 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1092 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9879 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9879 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9879 # number of overall hits +system.cpu6.l1c.overall_hits::total 9879 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36436 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36436 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23858 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23858 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60294 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60294 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60294 # number of overall misses +system.cpu6.l1c.overall_misses::total 60294 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 592887114 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 592887114 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 676055850 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 676055850 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1268942964 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1268942964 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1268942964 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1268942964 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45223 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45223 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24950 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70173 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70173 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70173 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70173 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805696 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805696 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956232 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.956232 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859219 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859219 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859219 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859219 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16272.014326 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16272.014326 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28336.652276 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28336.652276 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21045.924371 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21045.924371 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21045.924371 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21045.924371 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 742965 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66360 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61020 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.740341 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.175762 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9642 # number of writebacks -system.cpu6.l1c.writebacks::total 9642 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36489 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36489 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23831 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60320 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60320 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60320 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60320 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9769 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9769 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5428 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15197 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15197 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 534211155 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 534211155 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 633170857 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 633170857 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1167382012 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1167382012 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1167382012 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1167382012 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 633249047 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 633249047 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 972097686 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 972097686 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1605346733 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1605346733 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.802168 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.802168 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956300 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956300 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.856721 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.856721 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.856721 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.856721 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14640.334210 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14640.334210 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 26569.210566 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 26569.210566 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19353.150066 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19353.150066 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 64822.299826 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64822.299826 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 179089.477892 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179089.477892 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 105635.765809 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 105635.765809 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9883 # number of writebacks +system.cpu6.l1c.writebacks::total 9883 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36436 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36436 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23858 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23858 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60294 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60294 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9920 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9920 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5475 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15395 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 556451114 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 556451114 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652198850 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652198850 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1208649964 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1208649964 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1208649964 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1208649964 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 646733639 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 646733639 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 847369233 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 847369233 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494102872 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494102872 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805696 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805696 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956232 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956232 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859219 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859219 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859219 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859219 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15272.014326 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15272.014326 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27336.694191 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27336.694191 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20045.940956 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20045.940956 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20045.940956 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20045.940956 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65194.923286 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65194.923286 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154770.636164 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154770.636164 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97051.177135 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97051.177135 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99558 # number of read accesses completed -system.cpu7.num_writes 55171 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22301 # number of replacements -system.cpu7.l1c.tags.tagsinuse 392.314330 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13511 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22696 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.595303 # Average number of references to valid blocks. +system.cpu7.num_reads 99427 # number of read accesses completed +system.cpu7.num_writes 55134 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22242 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.816785 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13453 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22633 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.594398 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 392.314330 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.766239 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.766239 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337937 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337937 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8724 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8724 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1105 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1105 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9829 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9829 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9829 # number of overall hits -system.cpu7.l1c.overall_hits::total 9829 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36568 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36568 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23906 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23906 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses -system.cpu7.l1c.overall_misses::total 60474 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 596090233 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 596090233 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 664580608 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 664580608 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1260670841 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1260670841 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1260670841 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1260670841 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45292 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45292 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25011 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25011 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70303 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70303 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70303 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70303 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807383 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807383 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955819 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955819 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860191 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860191 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860191 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860191 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16300.870515 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16300.870515 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27799.740986 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 27799.740986 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 20846.493386 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 20846.493386 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 20846.493386 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 20846.493386 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 776345 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 391.816785 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.765267 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.765267 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338054 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338054 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8636 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8636 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9784 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9784 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9784 # number of overall hits +system.cpu7.l1c.overall_hits::total 9784 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36700 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36700 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23832 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23832 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60532 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60532 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60532 # number of overall misses +system.cpu7.l1c.overall_misses::total 60532 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 601580634 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 601580634 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 672036114 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 672036114 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1273616748 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1273616748 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1273616748 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1273616748 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45336 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45336 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24980 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70316 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70316 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70316 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70316 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809511 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.809511 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954043 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954043 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860857 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860857 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860857 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860857 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16391.842888 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16391.842888 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28198.897029 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 28198.897029 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21040.387696 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21040.387696 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21040.387696 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21040.387696 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 739183 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66228 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 60836 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.722308 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.150421 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9814 # number of writebacks -system.cpu7.l1c.writebacks::total 9814 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36568 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36568 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23906 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23906 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9700 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9700 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5336 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5336 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15036 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15036 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538984883 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538984883 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 627714786 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 627714786 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1166699669 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1166699669 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1166699669 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1166699669 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 629180127 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 629180127 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 945700289 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 945700289 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574880416 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574880416 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807383 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807383 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955819 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955819 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860191 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860191 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860191 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860191 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14739.249699 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14739.249699 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 26257.625115 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 26257.625115 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19292.583077 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19292.583077 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19292.583077 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19292.583077 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 64863.930619 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64863.930619 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 177230.189093 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 177230.189093 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 104740.650173 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 104740.650173 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9689 # number of writebacks +system.cpu7.l1c.writebacks::total 9689 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36700 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36700 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23832 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60532 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60532 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60532 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60532 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9751 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9751 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5566 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5566 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15317 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15317 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 564880634 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 564880634 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 648206114 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 648206114 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1213086748 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1213086748 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1213086748 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1213086748 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 637373819 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 637373819 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 878019147 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 878019147 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1515392966 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1515392966 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809511 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809511 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954043 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954043 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860857 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860857 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860857 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860857 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15391.842888 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15391.842888 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27198.980950 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27198.980950 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20040.420736 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20040.420736 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20040.420736 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20040.420736 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65364.969644 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65364.969644 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157746.882321 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157746.882321 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98935.363714 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98935.363714 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 14031 # number of replacements -system.l2c.tags.tagsinuse 784.967814 # Cycle average of tags in use -system.l2c.tags.total_refs 150152 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14812 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.137186 # Average number of references to valid blocks. +system.l2c.tags.replacements 13635 # number of replacements +system.l2c.tags.tagsinuse 787.795797 # Cycle average of tags in use +system.l2c.tags.total_refs 163881 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14421 # Sample count of references to valid blocks. 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occupancy -system.l2c.tags.occ_percent::cpu0 0.007470 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007829 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007318 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007447 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007945 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.766570 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 781 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 686 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 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number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 249579925 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 257995414 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 252050416 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2017800866 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 42779912 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 43250421 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 44195907 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 44710425 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 41223921 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 40317415 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 42323414 # number of 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2282 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2312 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2343 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2340 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2308 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2363 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18606 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6389 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6296 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6392 # number of ReadExReq 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miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54660.045339 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54769.755758 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54760.119030 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 62180.104651 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61435.257102 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62247.756338 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61079.815574 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61436.543964 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61931.513057 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62516.121123 # average ReadSharedReq miss latency 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(read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 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MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1959 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2034 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2073 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2095 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2074 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1984 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2101 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2050 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16370 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4565 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4622 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4503 # number of ReadExReq MSHR misses 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ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9869 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9727 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9854 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9778 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9927 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9769 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9700 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78458 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5517 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5460 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5550 # number of WriteReq MSHR uncacheable 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# number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 693563158 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 196462368 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 199050885 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 193595340 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 197409379 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 192312836 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 193341369 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 199367330 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 195358866 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1566898373 # number of ReadExReq MSHR miss cycles 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miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 237472777 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 230347762 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 233353305 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 229526757 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 228801780 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 235812748 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 234305765 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1863165170 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 419590422 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 420411799 # number of ReadReq MSHR uncacheable cycles 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-system.l2c.overall_mshr_uncacheable_latency::cpu2 662031124 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 657709027 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 655784643 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 667858655 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 658726650 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 650841130 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5281485764 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064409 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068118 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064166 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.063348 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.062695 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.062428 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063504 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067369 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.064498 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.878082 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883579 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.873946 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.874009 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.888603 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878654 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.878712 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.869750 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.878125 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.716416 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726730 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.716696 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.732448 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716669 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.712268 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723065 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.708853 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.719124 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.297420 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.304078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.295508 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.299966 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287701 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.294946 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.299062 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.297235 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.296970 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.297420 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.304078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.295508 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.299966 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287701 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.294946 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.299062 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.297235 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.296970 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50246.487805 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49512.747423 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50071.419619 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49646.306630 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49951.571812 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.211048 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49856.932969 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50318.990956 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49977.529858 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42357.817254 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42399.187316 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42330.422576 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42412.786158 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42342.867406 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42338.437500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42291.746311 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42470.716098 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42367.938790 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43036.663308 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43065.963868 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42992.524983 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43102.484498 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43051.899709 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43079.627674 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43115.772059 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42954.895778 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 43050.206693 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 44040.029417 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 43992.733790 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43984.678633 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43995.721154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 44038.134497 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 44051.170581 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 44035.994024 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 44025.885945 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 44020.441110 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 44040.029417 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 43992.733790 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43984.678633 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43995.721154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 44038.134497 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 44051.170581 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 44035.994024 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 44025.885945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 44020.441110 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42667.319707 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42599.229811 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42615.990336 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42633.914857 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42683.498364 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42615.370404 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42614.826901 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42563.427216 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42624.258495 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 44371.922603 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 44639.636813 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 44595.565045 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 44269.504379 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44399.515084 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44536.269420 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 44669.689700 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 44598.179535 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 44510.423927 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 43279.937398 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 43325.997521 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 43335.152451 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 43210.631824 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 43291.830143 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 43299.964665 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 43348.687155 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 43285.523410 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 43297.255038 # average overall mshr uncacheable latency +system.l2c.overall_mshr_hits::total 87 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1195 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1195 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2064 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2004 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2022 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2044 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2053 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2028 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2097 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2076 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16388 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4548 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4577 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4615 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4579 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4556 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4715 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4599 # number of ReadExReq MSHR misses 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ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.722875 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059844 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.059777 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.061384 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062039 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057598 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.055671 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058885 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060846 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059510 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.295384 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for overall accesses 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UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44126.387725 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44141.018245 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44148.535527 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44114.156069 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44143.052905 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44845.994381 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44851.673483 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44703.501857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44814.176381 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44823.200262 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44734.180202 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44683.120679 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44790.805827 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 44780.567362 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52327.836018 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51742.355811 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52404.123404 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 51409.993084 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51785.054463 # average ReadSharedReq mshr miss latency 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miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 45767.365682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 45731.320523 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 45707.540090 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 45701.403626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 45652.180962 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44434.574642 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44385.022778 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44375.893074 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44381.776768 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44449.804846 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44425.871923 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44369.744556 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44358.191365 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44397.556218 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45566.328559 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45522.452536 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45629.941953 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45783.280264 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45522.884970 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45504.485678 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45710.947032 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45702.306849 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45617.859258 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44842.397445 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44795.121555 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44817.054977 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44875.891943 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44830.158377 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44815.584024 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44846.723027 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44846.457947 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 44833.789624 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 84372 # Transaction distribution -system.membus.trans_dist::ReadResp 84365 # Transaction distribution -system.membus.trans_dist::WriteReq 43521 # Transaction distribution -system.membus.trans_dist::WriteResp 43519 # Transaction distribution -system.membus.trans_dist::Writeback 6720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60428 # Transaction distribution -system.membus.trans_dist::UpgradeResp 49463 # Transaction distribution -system.membus.trans_dist::ReadExReq 49409 # Transaction distribution -system.membus.trans_dist::ReadExResp 3325 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 425122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 425122 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1143411 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1143411 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57048 # Total snoops (count) -system.membus.snoop_fanout::samples 253034 # Request fanout histogram +system.membus.trans_dist::ReadReq 78781 # Transaction distribution +system.membus.trans_dist::ReadResp 84254 # Transaction distribution +system.membus.trans_dist::WriteReq 43831 # Transaction distribution +system.membus.trans_dist::WriteResp 43828 # Transaction distribution +system.membus.trans_dist::Writeback 6215 # Transaction distribution +system.membus.trans_dist::CleanEvict 1216 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61094 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50117 # Transaction distribution +system.membus.trans_dist::ReadExReq 49522 # Transaction distribution +system.membus.trans_dist::ReadExResp 3101 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5483 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427442 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1069738 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1069738 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57394 # Total snoops (count) +system.membus.snoop_fanout::samples 254906 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253034 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 254906 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253034 # Request fanout histogram -system.membus.reqLayer0.occupancy 288296633 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 60.9 # Layer utilization (%) -system.membus.respLayer0.occupancy 308136269 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 65.1 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 369990 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 369967 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43524 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43518 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 76544 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29606 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29605 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161002 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 160999 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120638 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120231 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120464 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120699 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120288 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120457 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120419 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 963786 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1770551 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1763883 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1765044 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785450 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756799 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1766043 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1776312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14141746 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 320975 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 687560 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::total 254906 # Request fanout histogram +system.membus.reqLayer0.occupancy 291050214 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 309370624 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 59.9 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 78782 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371328 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43832 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43827 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83405 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20435 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29579 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29579 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161223 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161218 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292561 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122537 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122267 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122810 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122614 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122506 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122579 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 980614 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769994 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778957 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1770860 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783783 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1787183 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1781792 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778193 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14229418 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335158 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 800908 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7.017024 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.129362 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram @@ -1769,29 +1778,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 687560 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 787273 98.30% 98.30% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 13635 1.70% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 687560 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 445191055 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 94.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101323906 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101013875 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 21.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101243878 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101066643 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 21.3 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101367492 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100955896 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101182766 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101290842 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%) +system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 800908 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 495395322 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101110391 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101309873 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101121441 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101199500 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101216377 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101535375 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101020631 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101318353 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 987ba828d..8965da370 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133634 # Number of seconds simulated -sim_ticks 133634149500 # Number of ticks simulated -final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133625 # Number of seconds simulated +sim_ticks 133625300500 # Number of ticks simulated +final_tick 133625300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1329181 # Simulator instruction rate (inst/s) -host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2010669405 # Simulator tick rate (ticks/s) -host_mem_usage 301232 # Number of bytes of host memory used -host_seconds 66.46 # Real time elapsed on the host +host_inst_rate 1195401 # Simulator instruction rate (inst/s) +host_op_rate 1195401 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1808178963 # Simulator tick rate (ticks/s) +host_mem_usage 302688 # Number of bytes of host memory used +host_seconds 73.90 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory -system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory -system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory -system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 419712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10136000 # Number of bytes read from this memory +system.physmem.bytes_read::total 10555712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 419712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 419712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7316416 # Number of bytes written to this memory +system.physmem.bytes_written::total 7316416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158375 # Number of read requests responded to by this memory +system.physmem.num_reads::total 164933 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114319 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114319 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3140962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75853899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 78994861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3140962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3140962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54753224 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54753224 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54753224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3140962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75853899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 133748085 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267268299 # number of cpu cycles simulated +system.cpu.numCycles 267250601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267268299 # Number of busy cycles +system.cpu.num_busy_cycles 267250601 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched @@ -129,12 +129,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4078.862376 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 936464500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.862376 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363527000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7363527000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9308954000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9308954000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9308954000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9308954000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1944960000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1944960000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363504500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7363504500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9308464500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9308464500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9308464500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9308464500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32007.372544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32007.372544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.743638 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.743638 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45552.913225 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45552.913225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45552.913225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45552.913225 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks -system.cpu.dcache.writebacks::total 168375 # number of writebacks +system.cpu.dcache.writebacks::writebacks 168314 # number of writebacks +system.cpu.dcache.writebacks::total 168314 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1854278000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1854278000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7148160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7148160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9002438000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1884194000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1884194000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7219926500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7219926500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9104120500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9104120500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9104120500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9104120500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -226,27 +226,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31007.372544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31007.372544 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50285.743638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50285.743638 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44552.913225 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44552.913225 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44552.913225 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44552.913225 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1871.687345 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686268 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.687345 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913910 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913910 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1277887500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1277887500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1277887500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1269528000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1269528000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1269528000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1269528000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1269528000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1269528000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16609.032393 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16609.032393 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16609.032393 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16609.032393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16609.032393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16609.032393 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,117 +302,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1163233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1163233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1163233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1163233500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1193092000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1193092000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1193092000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1193092000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1193092000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1193092000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15609.032393 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15609.032393 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15609.032393 # average overall mshr miss latency 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+system.cpu.l2cache.tags.total_refs 246631 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163072 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.512406 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.509533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853974 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.833082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937769 # 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+system.cpu.l2cache.writebacks::writebacks 114319 # number of writebacks +system.cpu.l2cache.writebacks::total 114319 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1879 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1879 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130880 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130880 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6558 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6558 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27495 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27495 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6558 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158375 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 164933 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6558 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158375 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 164933 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5562430500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5562430500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 279096500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 279096500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1168749500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1168749500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 279096500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6731180000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7010276500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 279096500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6731180000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7010276500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911560 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911560 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452473 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452473 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.587410 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.587410 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.233038 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.233038 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42558.173224 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42558.173224 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42507.710493 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42507.710493 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42558.173224 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42558.173224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 282633 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 123022 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23850112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28742016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 131016 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 686435 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.190864 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.392983 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 555419 80.91% 80.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 131016 19.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 686435 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 446023500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 34272 # Transaction distribution -system.membus.trans_dist::ReadResp 34272 # Transaction distribution -system.membus.trans_dist::Writeback 113982 # Transaction distribution -system.membus.trans_dist::ReadExReq 130881 # Transaction distribution -system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34053 # Transaction distribution +system.membus.trans_dist::Writeback 114319 # Transaction distribution +system.membus.trans_dist::CleanEvict 14713 # Transaction distribution +system.membus.trans_dist::ReadExReq 130880 # Transaction distribution +system.membus.trans_dist::ReadExResp 130880 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34053 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 458898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 458898 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17872128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17872128 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 279135 # Request fanout histogram +system.membus.snoop_fanout::samples 294098 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294098 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 279135 # Request fanout histogram -system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294098 # Request fanout histogram +system.membus.reqLayer0.occupancy 751484676 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 824727676 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 90d753109..22fc38403 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.127293 # Number of seconds simulated -sim_ticks 127293406500 # Number of ticks simulated -final_tick 127293406500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 127292683500 # Number of ticks simulated +final_tick 127292683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 627920 # Simulator instruction rate (inst/s) -host_op_rate 801678 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1135795886 # Simulator tick rate (ticks/s) -host_mem_usage 312172 # Number of bytes of host memory used -host_seconds 112.07 # Real time elapsed on the host +host_inst_rate 884807 # Simulator instruction rate (inst/s) +host_op_rate 1129650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1600449674 # Simulator tick rate (ticks/s) +host_mem_usage 320712 # Number of bytes of host memory used +host_seconds 79.54 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 252800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory -system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory -system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 8177280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 252800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 252800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5511360 # Number of bytes written to this memory +system.physmem.bytes_written::total 5511360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3950 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62253656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64260736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42187385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42187385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42187385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62253656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106448121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1985974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62254010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64239984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1985974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1985974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43296754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43296754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43296754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1985974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62254010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107536738 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254586813 # number of cpu cycles simulated +system.cpu.numCycles 254585367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373629 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254586812.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254585366.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741486 # Number of branches fetched @@ -215,53 +215,53 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690084 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389329 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.389202 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061071000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389329 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061071500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389202 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 857 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3190 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22749833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749833 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83618 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits -system.cpu.dcache.overall_hits::total 42576331 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42492702 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492702 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576320 # number of overall hits +system.cpu.dcache.overall_hits::total 42576320 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30234 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30234 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses -system.cpu.dcache.overall_misses::total 177381 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles +system.cpu.dcache.SoftPFReq_misses::cpu.data 40126 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40126 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137266 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses +system.cpu.dcache.overall_misses::total 177392 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 516863000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 516863000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6205992500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6205992500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6205992500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6205992500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -280,20 +280,20 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324266 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324266 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45211.432547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34984.624448 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,14 +302,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks -system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 128193 # number of writebacks +system.cpu.dcache.writebacks::total 128193 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1126 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1126 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1126 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1126 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 472117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 472117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6054214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6054214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7124591000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7124591000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,24 +340,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.672960 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.672092 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672960 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672092 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 412325000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 412325000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 412325000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 412325000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 412325000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 412325000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21806.907129 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21806.907129 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,117 +418,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 393417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 393417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393417000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 393417000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20806.907129 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20806.907129 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30351.005772 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 94651 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30350.488546 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 114091 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 125746 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.907313 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27796.867853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768393 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369526 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27670.394493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.496373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.597680 # Average occupied blocks per requestor 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40575.185701 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18444224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 94651 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.212056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.408765 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 351698 78.79% 78.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 94651 21.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 25532 # Transaction distribution -system.membus.trans_dist::ReadResp 25532 # Transaction distribution -system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadResp 25490 # Transaction distribution +system.membus.trans_dist::Writeback 86115 # Transaction distribution +system.membus.trans_dist::CleanEvict 6526 # Transaction distribution system.membus.trans_dist::ReadExReq 102280 # Transaction distribution system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 25490 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 348181 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13688640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13688640 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214640 # Request fanout histogram +system.membus.snoop_fanout::samples 220592 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 220592 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214640 # Request fanout histogram -system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 220592 # Request fanout histogram +system.membus.reqLayer0.occupancy 568748288 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 641607492 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 718e317fa..e9eb9ae35 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202242 # Number of seconds simulated -sim_ticks 202242028500 # Number of ticks simulated -final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202233 # Number of seconds simulated +sim_ticks 202232894500 # Number of ticks simulated +final_tick 202232894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1201078 # Simulator instruction rate (inst/s) -host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1807368744 # Simulator tick rate (ticks/s) -host_mem_usage 300888 # Number of bytes of host memory used -host_seconds 111.90 # Real time elapsed on the host +host_inst_rate 1204132 # Simulator instruction rate (inst/s) +host_op_rate 1219723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1811881435 # Simulator tick rate (ticks/s) +host_mem_usage 302340 # Number of bytes of host memory used +host_seconds 111.61 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory -system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory -system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory -system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 575680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7827008 # Number of bytes read from this memory +system.physmem.bytes_read::total 8402688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 575680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 575680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5453120 # Number of bytes written to this memory +system.physmem.bytes_written::total 5453120 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122297 # Number of read requests responded to by this memory +system.physmem.num_reads::total 131292 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 85205 # Number of write requests responded to by this memory +system.physmem.num_writes::total 85205 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2846619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38702942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41549561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2846619 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2846619 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26964555 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26964555 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26964555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2846619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38702942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68514116 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404484057 # number of cpu cycles simulated +system.cpu.numCycles 404465789 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -57,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles +system.cpu.num_busy_cycles 404465788.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12719095 # Number of branches fetched @@ -97,18 +97,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293798 # Class of executed instruction system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4087.647933 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 769041500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647933 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3529 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses @@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1475000000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619674000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5619674000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475169000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475169000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5620115500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5620115500 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7094674000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7094674000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7094674000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7094674000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7095284500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7095284500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7095284500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7095284500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47089.690236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47093.742326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47093.742326 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -180,8 +180,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks -system.cpu.dcache.writebacks::total 123970 # number of writebacks +system.cpu.dcache.writebacks::writebacks 123896 # number of writebacks +system.cpu.dcache.writebacks::total 123896 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -192,16 +192,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1406751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1406751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5461928000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5461928000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 382500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 382500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6868679500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6868679500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6868679500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6868679500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5514951500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5514951500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 390000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 390000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944621500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6944621500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944621500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6944621500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -212,29 +212,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 26000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 26000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 2004.814775 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143972077000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.warmup_cycle 143962972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814775 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id @@ -253,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819561500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2819561500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2819561500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2819561500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2819561500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2819561500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809817000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2809817000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2809817000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2809817000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2809817000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2809817000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -271,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15075.934105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15075.934105 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15023.831166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15023.831166 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,117 +291,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2539025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2539025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2539025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2539025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2539025500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2539025500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622793000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2622793000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622793000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2622793000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622793000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2622793000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14023.831166 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14023.831166 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98540 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30850.758845 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 98298 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30848.444766 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 433066 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129294 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.349467 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.945467 # Average occupied blocks per requestor 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-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945862 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3928089 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3928089 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 123970 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 123970 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3923 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3923 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 177782 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 28387 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 206169 # 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accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45499 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 45499 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.049416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.462318 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.130211 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962702 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.962702 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.049416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.811605 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.389494 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941 # average overall miss latency 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rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.388781 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52503.115772 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52503.115772 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52539.688716 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52539.688716 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.087841 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.087841 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52539.688716 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.282991 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52505.777199 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52539.688716 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.282991 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52505.777199 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,105 +416,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks -system.cpu.l2cache.writebacks::total 82868 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses 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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 374386000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4952828500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5327214500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 85205 # number of writebacks +system.cpu.l2cache.writebacks::total 85205 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1630 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1630 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101259 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101259 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8995 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8995 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21038 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21038 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8995 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122297 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 131292 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8995 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122297 # number of overall MSHR misses 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# mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462384 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462384 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811645 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.388781 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811645 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.388781 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42503.115772 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42503.115772 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42539.688716 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42539.688716 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.087841 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.087841 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42539.688716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42539.688716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 209101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 220689 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558971 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447925 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1006896 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17572736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29542272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 98298 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 767558 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.128066 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.334163 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 669260 87.19% 87.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 98298 12.81% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 767558 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 458526000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 30277 # Transaction distribution -system.membus.trans_dist::ReadResp 30277 # Transaction distribution -system.membus.trans_dist::Writeback 82868 # Transaction distribution -system.membus.trans_dist::ReadExReq 101256 # Transaction distribution -system.membus.trans_dist::ReadExResp 101256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 30033 # Transaction distribution +system.membus.trans_dist::Writeback 85205 # Transaction distribution +system.membus.trans_dist::CleanEvict 11182 # Transaction distribution +system.membus.trans_dist::ReadExReq 101259 # Transaction distribution +system.membus.trans_dist::ReadExResp 101259 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30033 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 358971 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 358971 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13855808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13855808 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214401 # Request fanout histogram +system.membus.snoop_fanout::samples 227790 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 227790 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214401 # Request fanout histogram -system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 227790 # Request fanout histogram +system.membus.reqLayer0.occupancy 569073488 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 656842488 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index b30732380..45eadd1aa 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000180 # Number of seconds simulated -sim_ticks 180391 # Number of ticks simulated -final_tick 180391 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000182 # Number of seconds simulated +sim_ticks 181651 # Number of ticks simulated +final_tick 181651 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2115130 # Simulator tick rate (ticks/s) -host_mem_usage 447992 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 2259116 # Simulator tick rate (ticks/s) +host_mem_usage 450116 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54784 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 54784 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49408 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 49408 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 856 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 856 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 772 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 772 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 303695861 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 303695861 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 273893930 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 273893930 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 577589791 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 577589791 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 856 # Number of read requests accepted -system.mem_ctrls.writeReqs 772 # Number of write requests accepted -system.mem_ctrls.readBursts 856 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 772 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 46080 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55232 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 55232 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49600 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 49600 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 863 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 863 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 775 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 775 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 304055579 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 304055579 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 273051070 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 273051070 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 577106650 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 577106650 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 863 # Number of read requests accepted +system.mem_ctrls.writeReqs 775 # Number of write requests accepted +system.mem_ctrls.readBursts 863 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 775 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 46400 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 8832 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 41792 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 54784 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 49408 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 92 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytesReadSys 55232 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 49600 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 94 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 208 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 240 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 209 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 243 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 49 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts @@ -51,8 +51,8 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 188 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 213 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 190 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 211 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 206 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 46 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts @@ -69,23 +69,23 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 180206 # Total gap between requests +system.mem_ctrls.totGap 181412 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 856 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 863 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 772 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 595 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 121 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 775 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 599 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 122 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 4 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -143,7 +143,7 @@ system.mem_ctrls.wrQLenPdf::23 38 # Wh system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 37 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 37 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 37 # What write queue length does an incoming req see @@ -181,16 +181,16 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 136 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 643.294118 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 479.730496 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 374.748392 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 644.235294 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 480.374054 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 374.900762 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 10 7.35% 7.35% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-255 25 18.38% 25.74% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-383 7 5.15% 30.88% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 10 7.35% 38.24% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 8 5.88% 44.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 7 5.15% 49.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 10 7.35% 56.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 4.41% 48.53% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 11 8.09% 56.62% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 7 5.15% 61.76% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 52 38.24% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 136 # Bytes accessed per row activation @@ -216,38 +216,38 @@ system.mem_ctrls.wrPerTurnAround::17 1 2.70% 24.32% # Wr system.mem_ctrls.wrPerTurnAround::18 24 64.86% 89.19% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::19 4 10.81% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 37 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6996 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 20676 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3600 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 9.72 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 6696 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 20471 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3625 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 9.24 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 28.72 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 255.45 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 231.67 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 303.70 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 273.89 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 28.24 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 255.43 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 230.07 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 304.06 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 273.05 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 3.81 # Data bus utilization in percentage +system.mem_ctrls.busUtil 3.79 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 2.00 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 1.81 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtilWrite 1.80 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.28 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.66 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 589 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 24.68 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 593 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 645 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.81 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 94.85 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 110.69 # Average gap between requests -system.mem_ctrls.pageHitRate 88.14 # Row buffer hit rate, read and write combined +system.mem_ctrls.readRowHitRate 81.79 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 94.71 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 110.75 # Average gap between requests +system.mem_ctrls.pageHitRate 88.05 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 1028160 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 571200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 8910720 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8935680 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 6770304 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 11696880 # Energy for refresh commands per rank (pJ) system.mem_ctrls_0.actBackEnergy 121998240 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 586800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 151562304 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 845.120967 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 348 # Time in different power states +system.mem_ctrls_0.totalEnergy 151587264 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 845.260146 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 392 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 5980 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT 173024 # Time in different power states @@ -269,172 +269,172 @@ system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 1008 -system.ruby.outstanding_req_hist::mean 15.793651 -system.ruby.outstanding_req_hist::gmean 15.695353 -system.ruby.outstanding_req_hist::stdev 1.131423 -system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.69% | 2 0.20% 0.89% | 2 0.20% 1.09% | 2 0.20% 1.29% | 88 8.73% 10.02% | 907 89.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 1008 +system.ruby.outstanding_req_hist::samples 1014 +system.ruby.outstanding_req_hist::mean 15.795858 +system.ruby.outstanding_req_hist::gmean 15.698068 +system.ruby.outstanding_req_hist::stdev 1.128795 +system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.49% | 2 0.20% 0.69% | 2 0.20% 0.89% | 2 0.20% 1.08% | 2 0.20% 1.28% | 86 8.48% 9.76% | 915 90.24% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 1014 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 993 -system.ruby.latency_hist::mean 2869.644512 -system.ruby.latency_hist::gmean 1439.923884 -system.ruby.latency_hist::stdev 1437.510562 -system.ruby.latency_hist | 203 20.44% 20.44% | 6 0.60% 21.05% | 136 13.70% 34.74% | 530 53.37% 88.12% | 116 11.68% 99.80% | 2 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 993 +system.ruby.latency_hist::samples 1000 +system.ruby.latency_hist::mean 2871.187000 +system.ruby.latency_hist::gmean 1437.111770 +system.ruby.latency_hist::stdev 1430.830977 +system.ruby.latency_hist | 202 20.20% 20.20% | 6 0.60% 20.80% | 139 13.90% 34.70% | 535 53.50% 88.20% | 116 11.60% 99.80% | 2 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 1000 system.ruby.hit_latency_hist::bucket_size 512 system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 140 -system.ruby.hit_latency_hist::mean 712.971429 -system.ruby.hit_latency_hist::gmean 27.405302 -system.ruby.hit_latency_hist::stdev 1358.773103 -system.ruby.hit_latency_hist | 110 78.57% 78.57% | 2 1.43% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 0.71% 80.71% | 9 6.43% 87.14% | 10 7.14% 94.29% | 4 2.86% 97.14% | 4 2.86% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 140 +system.ruby.hit_latency_hist::samples 141 +system.ruby.hit_latency_hist::mean 724.687943 +system.ruby.hit_latency_hist::gmean 26.569121 +system.ruby.hit_latency_hist::stdev 1368.603016 +system.ruby.hit_latency_hist | 110 78.01% 78.01% | 2 1.42% 79.43% | 0 0.00% 79.43% | 0 0.00% 79.43% | 1 0.71% 80.14% | 10 7.09% 87.23% | 10 7.09% 94.33% | 4 2.84% 97.16% | 4 2.84% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 141 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 853 -system.ruby.miss_latency_hist::mean 3223.611958 -system.ruby.miss_latency_hist::gmean 2758.799775 -system.ruby.miss_latency_hist::stdev 1102.294906 -system.ruby.miss_latency_hist | 91 10.67% 10.67% | 6 0.70% 11.37% | 126 14.77% 26.14% | 516 60.49% 86.64% | 112 13.13% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 853 -system.ruby.Directory.incomplete_times 853 +system.ruby.miss_latency_hist::samples 859 +system.ruby.miss_latency_hist::mean 3223.522701 +system.ruby.miss_latency_hist::gmean 2766.758930 +system.ruby.miss_latency_hist::stdev 1093.907352 +system.ruby.miss_latency_hist | 90 10.48% 10.48% | 6 0.70% 11.18% | 128 14.90% 26.08% | 521 60.65% 86.73% | 112 13.04% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 859 +system.ruby.Directory.incomplete_times 859 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 80 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 854 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 934 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 82 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 941 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 58 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 58 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 57 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 855 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 912 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.L1Icache.demand_misses 57 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 55 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 861 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 916 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 8 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 2.513845 -system.ruby.network.routers0.msg_count.Request_Control::2 858 -system.ruby.network.routers0.msg_count.Response_Data::4 856 -system.ruby.network.routers0.msg_count.Writeback_Data::5 772 -system.ruby.network.routers0.msg_count.Writeback_Control::2 851 -system.ruby.network.routers0.msg_count.Writeback_Control::3 849 -system.ruby.network.routers0.msg_count.Writeback_Control::5 77 -system.ruby.network.routers0.msg_count.Unblock_Control::5 852 -system.ruby.network.routers0.msg_bytes.Request_Control::2 6864 -system.ruby.network.routers0.msg_bytes.Response_Data::4 61632 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 55584 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6808 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6792 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6816 -system.ruby.network.routers1.percent_links_utilized 2.513291 -system.ruby.network.routers1.msg_count.Request_Control::2 856 -system.ruby.network.routers1.msg_count.Response_Data::4 856 -system.ruby.network.routers1.msg_count.Writeback_Data::5 772 -system.ruby.network.routers1.msg_count.Writeback_Control::2 850 -system.ruby.network.routers1.msg_count.Writeback_Control::3 849 -system.ruby.network.routers1.msg_count.Writeback_Control::5 77 -system.ruby.network.routers1.msg_count.Unblock_Control::5 851 -system.ruby.network.routers1.msg_bytes.Request_Control::2 6848 -system.ruby.network.routers1.msg_bytes.Response_Data::4 61632 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 55584 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6800 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6792 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6808 -system.ruby.network.routers2.percent_links_utilized 2.513429 -system.ruby.network.routers2.msg_count.Request_Control::2 856 -system.ruby.network.routers2.msg_count.Response_Data::4 856 -system.ruby.network.routers2.msg_count.Writeback_Data::5 772 -system.ruby.network.routers2.msg_count.Writeback_Control::2 851 -system.ruby.network.routers2.msg_count.Writeback_Control::3 849 -system.ruby.network.routers2.msg_count.Writeback_Control::5 77 -system.ruby.network.routers2.msg_count.Unblock_Control::5 851 -system.ruby.network.routers2.msg_bytes.Request_Control::2 6848 -system.ruby.network.routers2.msg_bytes.Response_Data::4 61632 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 55584 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6808 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6792 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6808 -system.ruby.network.msg_count.Request_Control 2570 -system.ruby.network.msg_count.Response_Data 2568 -system.ruby.network.msg_count.Writeback_Data 2316 -system.ruby.network.msg_count.Writeback_Control 5330 -system.ruby.network.msg_count.Unblock_Control 2554 -system.ruby.network.msg_byte.Request_Control 20560 -system.ruby.network.msg_byte.Response_Data 184896 -system.ruby.network.msg_byte.Writeback_Data 166752 -system.ruby.network.msg_byte.Writeback_Control 42640 -system.ruby.network.msg_byte.Unblock_Control 20432 -system.ruby.network.routers0.throttle0.link_utilization 2.370684 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 856 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 849 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 61632 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6792 -system.ruby.network.routers0.throttle1.link_utilization 2.657006 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 858 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 772 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 851 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+system.ruby.network.routers2.percent_links_utilized 2.513061 +system.ruby.network.routers2.msg_count.Request_Control::2 863 +system.ruby.network.routers2.msg_count.Response_Data::4 863 +system.ruby.network.routers2.msg_count.Writeback_Data::5 776 +system.ruby.network.routers2.msg_count.Writeback_Control::2 856 +system.ruby.network.routers2.msg_count.Writeback_Control::3 855 +system.ruby.network.routers2.msg_count.Writeback_Control::5 78 +system.ruby.network.routers2.msg_count.Unblock_Control::5 857 +system.ruby.network.routers2.msg_bytes.Request_Control::2 6904 +system.ruby.network.routers2.msg_bytes.Response_Data::4 62136 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 55872 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6848 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 624 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6856 +system.ruby.network.msg_count.Request_Control 2589 +system.ruby.network.msg_count.Response_Data 2589 +system.ruby.network.msg_count.Writeback_Data 2329 +system.ruby.network.msg_count.Writeback_Control 5366 +system.ruby.network.msg_count.Unblock_Control 2570 +system.ruby.network.msg_byte.Request_Control 20712 +system.ruby.network.msg_byte.Response_Data 186408 +system.ruby.network.msg_byte.Writeback_Data 167688 +system.ruby.network.msg_byte.Writeback_Control 42928 +system.ruby.network.msg_byte.Unblock_Control 20560 +system.ruby.network.routers0.throttle0.link_utilization 2.373232 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 863 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 855 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 62136 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6840 +system.ruby.network.routers0.throttle1.link_utilization 2.655367 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+system.ruby.network.routers2.throttle0.link_utilization 2.373232 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 863 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 855 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 62136 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6840 +system.ruby.network.routers2.throttle1.link_utilization 2.652889 +system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 863 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 776 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 856 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 78 +system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 857 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 6904 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 55872 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6848 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 624 +system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6856 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 42 -system.ruby.LD.latency_hist::mean 3027.476190 -system.ruby.LD.latency_hist::gmean 1653.479867 -system.ruby.LD.latency_hist::stdev 1407.091452 -system.ruby.LD.latency_hist | 5 11.90% 11.90% | 2 4.76% 16.67% | 1 2.38% 19.05% | 0 0.00% 19.05% | 0 0.00% 19.05% | 5 11.90% 30.95% | 11 26.19% 57.14% | 14 33.33% 90.48% | 1 2.38% 92.86% | 3 7.14% 100.00% -system.ruby.LD.latency_hist::total 42 +system.ruby.LD.latency_hist::samples 43 +system.ruby.LD.latency_hist::mean 2957.116279 +system.ruby.LD.latency_hist::gmean 1414.337715 +system.ruby.LD.latency_hist::stdev 1464.799632 +system.ruby.LD.latency_hist | 6 13.95% 13.95% | 2 4.65% 18.60% | 1 2.33% 20.93% | 0 0.00% 20.93% | 0 0.00% 20.93% | 5 11.63% 32.56% | 11 25.58% 58.14% | 14 32.56% 90.70% | 1 2.33% 93.02% | 3 6.98% 100.00% +system.ruby.LD.latency_hist::total 43 system.ruby.LD.hit_latency_hist::bucket_size 64 system.ruby.LD.hit_latency_hist::max_bucket 639 -system.ruby.LD.hit_latency_hist::samples 4 -system.ruby.LD.hit_latency_hist::mean 142 -system.ruby.LD.hit_latency_hist::gmean 6.410729 -system.ruby.LD.hit_latency_hist::stdev 280.668250 -system.ruby.LD.hit_latency_hist | 3 75.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 4 +system.ruby.LD.hit_latency_hist::samples 5 +system.ruby.LD.hit_latency_hist::mean 114 +system.ruby.LD.hit_latency_hist::gmean 5.078459 +system.ruby.LD.hit_latency_hist::stdev 251 +system.ruby.LD.hit_latency_hist | 4 80.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 5 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 system.ruby.LD.miss_latency_hist::samples 38 @@ -445,36 +445,36 @@ system.ruby.LD.miss_latency_hist | 2 5.26% 5.26% | system.ruby.LD.miss_latency_hist::total 38 system.ruby.ST.latency_hist::bucket_size 1024 system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 890 -system.ruby.ST.latency_hist::mean 3023.052809 -system.ruby.ST.latency_hist::gmean 1627.027590 -system.ruby.ST.latency_hist::stdev 1328.502697 -system.ruby.ST.latency_hist | 138 15.51% 15.51% | 5 0.56% 16.07% | 131 14.72% 30.79% | 503 56.52% 87.30% | 111 12.47% 99.78% | 2 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 890 +system.ruby.ST.latency_hist::samples 896 +system.ruby.ST.latency_hist::mean 3023.541295 +system.ruby.ST.latency_hist::gmean 1629.541922 +system.ruby.ST.latency_hist::stdev 1321.027864 +system.ruby.ST.latency_hist | 137 15.29% 15.29% | 5 0.56% 15.85% | 134 14.96% 30.80% | 507 56.58% 87.39% | 111 12.39% 99.78% | 2 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 896 system.ruby.ST.hit_latency_hist::bucket_size 512 system.ruby.ST.hit_latency_hist::max_bucket 5119 -system.ruby.ST.hit_latency_hist::samples 122 -system.ruby.ST.hit_latency_hist::mean 712.459016 -system.ruby.ST.hit_latency_hist::gmean 27.014946 -system.ruby.ST.hit_latency_hist::stdev 1340.432607 -system.ruby.ST.hit_latency_hist | 96 78.69% 78.69% | 1 0.82% 79.51% | 0 0.00% 79.51% | 0 0.00% 79.51% | 1 0.82% 80.33% | 9 7.38% 87.70% | 10 8.20% 95.90% | 2 1.64% 97.54% | 3 2.46% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 122 +system.ruby.ST.hit_latency_hist::samples 121 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+system.ruby.ST.miss_latency_hist::samples 775 +system.ruby.ST.miss_latency_hist::mean 3384.810323 +system.ruby.ST.miss_latency_hist::gmean 3117.032073 +system.ruby.ST.miss_latency_hist::stdev 878.738069 +system.ruby.ST.miss_latency_hist | 41 5.29% 5.29% | 5 0.65% 5.94% | 123 15.87% 21.81% | 496 64.00% 85.81% | 108 13.94% 99.74% | 2 0.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 775 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 58 -system.ruby.IFETCH.latency_hist::mean 343.913793 -system.ruby.IFETCH.latency_hist::gmean 189.679476 -system.ruby.IFETCH.latency_hist::stdev 245.446052 -system.ruby.IFETCH.latency_hist | 14 24.14% 24.14% | 9 15.52% 39.66% | 10 17.24% 56.90% | 11 18.97% 75.86% | 6 10.34% 86.21% | 6 10.34% 96.55% | 1 1.72% 98.28% | 1 1.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 58 +system.ruby.IFETCH.latency_hist::samples 57 +system.ruby.IFETCH.latency_hist::mean 343.526316 +system.ruby.IFETCH.latency_hist::gmean 188.406917 +system.ruby.IFETCH.latency_hist::stdev 245.127161 +system.ruby.IFETCH.latency_hist | 14 24.56% 24.56% | 8 14.04% 38.60% | 10 17.54% 56.14% | 12 21.05% 77.19% | 5 8.77% 85.96% | 6 10.53% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 57 system.ruby.IFETCH.hit_latency_hist::bucket_size 16 system.ruby.IFETCH.hit_latency_hist::max_bucket 159 system.ruby.IFETCH.hit_latency_hist::samples 11 @@ -485,60 +485,60 @@ system.ruby.IFETCH.hit_latency_hist | 8 72.73% 72.73% | system.ruby.IFETCH.hit_latency_hist::total 11 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 47 -system.ruby.IFETCH.miss_latency_hist::mean 416.127660 -system.ruby.IFETCH.miss_latency_hist::gmean 348.839643 -system.ruby.IFETCH.miss_latency_hist::stdev 214.528058 -system.ruby.IFETCH.miss_latency_hist | 3 6.38% 6.38% | 9 19.15% 25.53% | 10 21.28% 46.81% | 11 23.40% 70.21% | 6 12.77% 82.98% | 6 12.77% 95.74% | 1 2.13% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 47 +system.ruby.IFETCH.miss_latency_hist::samples 46 +system.ruby.IFETCH.miss_latency_hist::mean 417.217391 +system.ruby.IFETCH.miss_latency_hist::gmean 350.554490 +system.ruby.IFETCH.miss_latency_hist::stdev 213.226527 +system.ruby.IFETCH.miss_latency_hist | 3 6.52% 6.52% | 8 17.39% 23.91% | 10 21.74% 45.65% | 12 26.09% 71.74% | 5 10.87% 82.61% | 6 13.04% 95.65% | 1 2.17% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 46 system.ruby.FLUSH.latency_hist::bucket_size 512 system.ruby.FLUSH.latency_hist::max_bucket 5119 -system.ruby.FLUSH.latency_hist::samples 3 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+system.ruby.L1Cache.hit_mach_latency_hist::total 86 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 512 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L2Cache.hit_mach_latency_hist::samples 57 -system.ruby.L2Cache.hit_mach_latency_hist::mean 1508.035088 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 242.175752 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 1635.914870 -system.ruby.L2Cache.hit_mach_latency_hist | 30 52.63% 52.63% | 2 3.51% 56.14% | 0 0.00% 56.14% | 0 0.00% 56.14% | 1 1.75% 57.89% | 9 15.79% 73.68% | 10 17.54% 91.23% | 2 3.51% 94.74% | 3 5.26% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 57 +system.ruby.L2Cache.hit_mach_latency_hist::samples 55 +system.ruby.L2Cache.hit_mach_latency_hist::mean 1543.636364 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 242.142059 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 1640.017066 +system.ruby.L2Cache.hit_mach_latency_hist | 28 50.91% 50.91% | 2 3.64% 54.55% | 0 0.00% 54.55% | 0 0.00% 54.55% | 1 1.82% 56.36% | 10 18.18% 74.55% | 9 16.36% 90.91% | 2 3.64% 94.55% | 3 5.45% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 55 system.ruby.Directory.miss_mach_latency_hist::bucket_size 1024 system.ruby.Directory.miss_mach_latency_hist::max_bucket 10239 -system.ruby.Directory.miss_mach_latency_hist::samples 853 -system.ruby.Directory.miss_mach_latency_hist::mean 3223.611958 -system.ruby.Directory.miss_mach_latency_hist::gmean 2758.799775 -system.ruby.Directory.miss_mach_latency_hist::stdev 1102.294906 -system.ruby.Directory.miss_mach_latency_hist | 91 10.67% 10.67% | 6 0.70% 11.37% | 126 14.77% 26.14% | 516 60.49% 86.64% | 112 13.13% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 853 +system.ruby.Directory.miss_mach_latency_hist::samples 859 +system.ruby.Directory.miss_mach_latency_hist::mean 3223.522701 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 3 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 4 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1.750000 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1.565085 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::stdev 0.957427 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 2 50.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 4 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 64 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 639 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1 @@ -557,28 +557,28 @@ system.ruby.LD.Directory.miss_type_mach_latency_hist | 2 5.26% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 38 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 16 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 159 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 77 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 24.857143 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 5.046843 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev 43.930781 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 61 79.22% 79.22% | 0 0.00% 79.22% | 0 0.00% 79.22% | 0 0.00% 79.22% | 0 0.00% 79.22% | 0 0.00% 79.22% | 9 11.69% 90.91% | 7 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 77 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 78 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 24.576923 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 5.013300 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::stdev 43.714695 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 62 79.49% 79.49% | 0 0.00% 79.49% | 0 0.00% 79.49% | 0 0.00% 79.49% | 0 0.00% 79.49% | 0 0.00% 79.49% | 9 11.54% 91.03% | 7 8.97% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 78 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 45 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1889.022222 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 476.752241 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 1641.523495 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 19 42.22% 42.22% | 1 2.22% 44.44% | 0 0.00% 44.44% | 0 0.00% 44.44% | 1 2.22% 46.67% | 9 20.00% 66.67% | 10 22.22% 88.89% | 2 4.44% 93.33% | 3 6.67% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 45 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 43 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1952.279070 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 491.923320 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 1633.364659 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 17 39.53% 39.53% | 1 2.33% 41.86% | 0 0.00% 41.86% | 0 0.00% 41.86% | 1 2.33% 44.19% | 10 23.26% 67.44% | 9 20.93% 88.37% | 2 4.65% 93.02% | 3 6.98% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 43 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 1024 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 10239 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 768 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3390.100260 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 3119.766603 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 882.096753 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 41 5.34% 5.34% | 5 0.65% 5.99% | 121 15.76% 21.74% | 491 63.93% 85.68% | 108 14.06% 99.74% | 2 0.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 768 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 775 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3384.810323 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 3117.032073 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 878.738069 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 41 5.29% 5.29% | 5 0.65% 5.94% | 123 15.87% 21.81% | 496 64.00% 85.81% | 108 13.94% 99.74% | 2 0.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 775 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 16 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 159 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 11 @@ -589,96 +589,96 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 8 72.73% system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 11 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 128 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 1279 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 47 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 416.127660 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 348.839643 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 214.528058 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 3 6.38% 6.38% | 9 19.15% 25.53% | 10 21.28% 46.81% | 11 23.40% 70.21% | 6 12.77% 82.98% | 6 12.77% 95.74% | 1 2.13% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 47 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 46 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 417.217391 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 350.554490 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 213.226527 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 3 6.52% 6.52% | 8 17.39% 23.91% | 10 21.74% 45.65% | 12 26.09% 71.74% | 5 10.87% 82.61% | 6 13.04% 95.65% | 1 2.17% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 46 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples 3 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 3979.666667 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 3955.937145 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 544.674521 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 3 -system.ruby.Directory_Controller.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.GETS 88 0.00% 0.00% -system.ruby.Directory_Controller.PUT 927 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 851 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 77 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 772 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 772 0.00% 0.00% -system.ruby.Directory_Controller.GETF 3 0.00% 0.00% -system.ruby.Directory_Controller.PUTF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 846 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 85 0.00% 0.00% -system.ruby.Directory_Controller.E.GETF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 81 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 851 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 853 0.00% 0.00% +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::samples 4 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::mean 3839.250000 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 3813.994404 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 525.972987 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 4 +system.ruby.Directory_Controller.GETX 775 0.00% 0.00% +system.ruby.Directory_Controller.GETS 87 0.00% 0.00% +system.ruby.Directory_Controller.PUT 933 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 856 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 78 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 775 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 863 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 775 0.00% 0.00% +system.ruby.Directory_Controller.GETF 4 0.00% 0.00% +system.ruby.Directory_Controller.PUTF 4 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 851 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 775 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 84 0.00% 0.00% +system.ruby.Directory_Controller.E.GETF 4 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 82 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 856 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 859 0.00% 0.00% system.ruby.Directory_Controller.WB.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 77 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 772 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 78 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 775 0.00% 0.00% system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 772 0.00% 0.00% -system.ruby.Directory_Controller.NO_F.PUTF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_F_W.Memory_Data 3 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 44 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 65 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 914 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 848 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 15989 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 46 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 775 0.00% 0.00% +system.ruby.Directory_Controller.NO_F.PUTF 4 0.00% 0.00% +system.ruby.Directory_Controller.NO_F_W.Memory_Data 4 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 45 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 64 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 920 0.00% 0.00% +system.ruby.L1Cache_Controller.L2_Replacement 854 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_to_L2 16018 0.00% 0.00% +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 44 0.00% 0.00% system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 11 0.00% 0.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1 57 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 856 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 849 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 856 0.00% 0.00% -system.ruby.L1Cache_Controller.Flush_line 3 0.00% 0.00% +system.ruby.L1Cache_Controller.Complete_L2_to_L1 55 0.00% 0.00% +system.ruby.L1Cache_Controller.Exclusive_Data 863 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 855 0.00% 0.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers 862 0.00% 0.00% +system.ruby.L1Cache_Controller.Flush_line 4 0.00% 0.00% system.ruby.L1Cache_Controller.I.Load 38 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 47 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 770 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Flush_line 3 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 74 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 84 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 10 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 2 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 77 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement 774 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2 823 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 46 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 777 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Flush_line 4 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L2_Replacement 75 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_to_L2 83 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 8 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Load 3 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 78 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement 779 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2 828 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 36 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 11 0.00% 0.00% system.ruby.L1Cache_Controller.MR.Load 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Store 9 0.00% 0.00% +system.ruby.L1Cache_Controller.MR.Store 7 0.00% 0.00% system.ruby.L1Cache_Controller.MR.L1_to_L2 40 0.00% 0.00% system.ruby.L1Cache_Controller.MMR.Ifetch 11 0.00% 0.00% system.ruby.L1Cache_Controller.MMR.Store 36 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2 63 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2 9575 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 768 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.L1_to_L2 61 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2 9608 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data 775 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.L1_to_L2 412 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 85 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 83 0.00% 0.00% system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 4225 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 768 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 4233 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 775 0.00% 0.00% system.ruby.L1Cache_Controller.IS.L1_to_L2 594 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 85 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data 84 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Load 2 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Ifetch 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 846 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 851 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Store 2 0.00% 0.00% system.ruby.L1Cache_Controller.MT.L1_to_L2 52 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 10 0.00% 0.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 8 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Ifetch 1 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Store 20 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2 121 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.L1_to_L2 107 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 47 0.00% 0.00% -system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 3 0.00% 0.00% -system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 3 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 3 0.00% 0.00% +system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 4 0.00% 0.00% +system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 4 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 4 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 5b3332128..e85a7a6f9 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 8616438631 # Simulator tick rate (ticks/s) -host_mem_usage 263800 # Number of bytes of host memory used -host_seconds 11.61 # Real time elapsed on the host +host_tick_rate 8340026204 # Simulator tick rate (ticks/s) +host_mem_usage 263964 # Number of bytes of host memory used +host_seconds 11.99 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -29,7 +29,7 @@ system.physmem.readBursts 1666397 # Nu system.physmem.writeBursts 1666879 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 106648000 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue -system.physmem.bytesWritten 106676864 # Total number of bytes written to DRAM +system.physmem.bytesWritten 106676992 # Total number of bytes written to DRAM system.physmem.bytesReadSys 106649408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 106680256 # Total written bytes from the system interface side system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue @@ -40,14 +40,14 @@ system.physmem.perBankRdBursts::1 103995 # Pe system.physmem.perBankRdBursts::2 104918 # Per bank write bursts system.physmem.perBankRdBursts::3 104597 # Per bank write bursts system.physmem.perBankRdBursts::4 103869 # Per bank write bursts -system.physmem.perBankRdBursts::5 103935 # Per bank write bursts -system.physmem.perBankRdBursts::6 103648 # Per bank write bursts -system.physmem.perBankRdBursts::7 104313 # Per bank write bursts -system.physmem.perBankRdBursts::8 103868 # Per bank write bursts +system.physmem.perBankRdBursts::5 103934 # Per bank write bursts +system.physmem.perBankRdBursts::6 103649 # Per bank write bursts +system.physmem.perBankRdBursts::7 104312 # Per bank write bursts +system.physmem.perBankRdBursts::8 103869 # Per bank write bursts system.physmem.perBankRdBursts::9 104354 # Per bank write bursts system.physmem.perBankRdBursts::10 103835 # Per bank write bursts -system.physmem.perBankRdBursts::11 104272 # Per bank write bursts -system.physmem.perBankRdBursts::12 104077 # Per bank write bursts +system.physmem.perBankRdBursts::11 104273 # Per bank write bursts +system.physmem.perBankRdBursts::12 104076 # Per bank write bursts system.physmem.perBankRdBursts::13 104035 # Per bank write bursts system.physmem.perBankRdBursts::14 104583 # Per bank write bursts system.physmem.perBankRdBursts::15 104046 # Per bank write bursts @@ -56,17 +56,17 @@ system.physmem.perBankWrBursts::1 104091 # Pe system.physmem.perBankWrBursts::2 104175 # Per bank write bursts system.physmem.perBankWrBursts::3 103885 # Per bank write bursts system.physmem.perBankWrBursts::4 104730 # Per bank write bursts -system.physmem.perBankWrBursts::5 104507 # Per bank write bursts -system.physmem.perBankWrBursts::6 104082 # Per bank write bursts +system.physmem.perBankWrBursts::5 104509 # Per bank write bursts +system.physmem.perBankWrBursts::6 104084 # Per bank write bursts system.physmem.perBankWrBursts::7 104226 # Per bank write bursts -system.physmem.perBankWrBursts::8 104320 # Per bank write bursts +system.physmem.perBankWrBursts::8 104319 # Per bank write bursts system.physmem.perBankWrBursts::9 104219 # Per bank write bursts -system.physmem.perBankWrBursts::10 104228 # Per bank write bursts -system.physmem.perBankWrBursts::11 103702 # Per bank write bursts -system.physmem.perBankWrBursts::12 104104 # Per bank write bursts -system.physmem.perBankWrBursts::13 103983 # Per bank write bursts +system.physmem.perBankWrBursts::10 104227 # Per bank write bursts +system.physmem.perBankWrBursts::11 103701 # Per bank write bursts +system.physmem.perBankWrBursts::12 104102 # Per bank write bursts +system.physmem.perBankWrBursts::13 103984 # Per bank write bursts system.physmem.perBankWrBursts::14 104296 # Per bank write bursts -system.physmem.perBankWrBursts::15 103921 # Per bank write bursts +system.physmem.perBankWrBursts::15 103923 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 99999956143 # Total gap between requests @@ -84,20 +84,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1666879 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 750686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 769672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 84683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 753402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 771059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 83025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -131,33 +131,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 37870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 87757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 105663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 108535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 113878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 112245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 107898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 126067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 108001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 100239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 100135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 100039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 39564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 91518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 104735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 104786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 114835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 116330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 106236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 102201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 124996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 116244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 105513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 101800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 100156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 100074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 99950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 99852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -180,12 +180,12 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3296308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 64.716127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 64.192082 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 23.993116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3288370 99.76% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5783 0.18% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 3296341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.715538 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.191659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 23.992392 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3288436 99.76% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5750 0.17% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 32 0.00% 99.94% # Bytes accessed per row activation @@ -193,41 +193,41 @@ system.physmem.bytesPerActivate::640-767 32 0.00% 99.94% # By system.physmem.bytesPerActivate::768-895 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 1963 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3296308 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 99265 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.787065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 15.442881 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 105.996031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 99264 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 3296341 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 99183 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.800984 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 15.462609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.039262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 99182 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 99265 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 99265 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.791679 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.710831 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.758038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 78980 79.56% 79.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3022 3.04% 82.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3011 3.03% 85.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1773 1.79% 87.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1415 1.43% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8615 8.68% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2003 2.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 293 0.30% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 66 0.07% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 33 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 21 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 21 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 99265 # Writes before turning the bus around for reads -system.physmem.totQLat 60762575042 # Total ticks spent queuing -system.physmem.totMemAccLat 92007106292 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 99183 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 99183 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.805582 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.725629 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.745457 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 77723 78.36% 78.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3827 3.86% 82.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3399 3.43% 85.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1646 1.66% 87.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 640 0.65% 87.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 10486 10.57% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1261 1.27% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 65 0.07% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 41 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 31 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 25 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 19 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 99183 # Writes before turning the bus around for reads +system.physmem.totQLat 59888739257 # Total ticks spent queuing +system.physmem.totMemAccLat 91133270507 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 8331875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36463.93 # Average queueing delay per DRAM burst +system.physmem.avgQLat 35939.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55213.93 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 54689.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1066.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1066.77 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1066.49 # Average system read bandwidth in MiByte/s @@ -236,41 +236,41 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 16.67 # Data bus utilization in percentage system.physmem.busUtilRead 8.33 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 8.33 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.44 # Average write queue length when enqueuing -system.physmem.readRowHits 32179 # Number of row buffer hits during reads -system.physmem.writeRowHits 4705 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing +system.physmem.readRowHits 32158 # Number of row buffer hits during reads +system.physmem.writeRowHits 4696 # Number of row buffer hits during writes system.physmem.readRowHitRate 1.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 0.28 # Row buffer hit rate for writes system.physmem.avgGap 30000.50 # Average gap between requests system.physmem.pageHitRate 1.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 12463295040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 6800409000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6499701000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5404592160 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 12463748640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6800656500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6499693200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5404585680 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6531436080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67776382665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 546474000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 106022289945 # Total energy per rank (pJ) -system.physmem_0.averagePower 1060.232773 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 531628571 # Time in different power states +system.physmem_0.actBackEnergy 67774130595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 548449500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 106022700195 # Total energy per rank (pJ) +system.physmem_0.averagePower 1060.236875 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 533126864 # Time in different power states system.physmem_0.memoryStateTime::REF 3339180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 96128273929 # Time in different power states +system.physmem_0.memoryStateTime::ACT 96126775636 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 12456559080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 6796733625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6497875800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5396304240 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 12456264240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 6796572750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6497883600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5396252400 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6531436080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 67774932585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 547746000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 106001587410 # Total energy per rank (pJ) -system.physmem_1.averagePower 1060.025746 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 534269274 # Time in different power states +system.physmem_1.actBackEnergy 67770272835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 551833500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 106000515405 # Total energy per rank (pJ) +system.physmem_1.averagePower 1060.015025 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 539825532 # Time in different power states system.physmem_1.memoryStateTime::REF 3339180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 96125633226 # Time in different power states +system.physmem_1.memoryStateTime::ACT 96120321460 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.numPackets 3333276 # Number of packets generated system.cpu.numRetries 0 # Number of retries @@ -285,7 +285,7 @@ system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11028299087 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11025639931 # Layer occupancy (ticks) system.membus.respLayer0.utilization 11.0 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets @@ -339,8 +339,8 @@ system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1063154851.723305 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107909478.113936 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154807.297242 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107909912.518316 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -392,34 +392,34 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 78736.863581 # Read request-response latency -system.monitor.readLatencyHist::gmean 73318.978124 # Read request-response latency -system.monitor.readLatencyHist::stdev 40691.515724 # Read request-response latency +system.monitor.readLatencyHist::mean 80828.076592 # Read request-response latency +system.monitor.readLatencyHist::gmean 75646.741335 # Read request-response latency +system.monitor.readLatencyHist::stdev 40157.798719 # Read request-response latency system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 439224 26.36% 26.36% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1018381 61.11% 87.47% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 80826 4.85% 92.32% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 59766 3.59% 95.91% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 27643 1.66% 97.57% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 9933 0.60% 98.16% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7785 0.47% 98.63% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 7834 0.47% 99.10% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7851 0.47% 99.57% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 3709 0.22% 99.79% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1488 0.09% 99.88% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 851 0.05% 99.93% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 701 0.04% 99.98% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 330 0.02% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 51 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::524288-557055 2 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 453129 27.19% 27.19% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1001108 60.08% 87.27% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 83302 5.00% 92.27% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 62543 3.75% 96.02% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 26583 1.60% 97.62% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 8788 0.53% 98.14% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7679 0.46% 98.61% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 7849 0.47% 99.08% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7873 0.47% 99.55% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 4044 0.24% 99.79% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1554 0.09% 99.88% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 891 0.05% 99.94% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 671 0.04% 99.98% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 316 0.02% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 44 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::524288-557055 1 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency system.monitor.writeLatencyHist::samples 1666878 # Write request-response latency -system.monitor.writeLatencyHist::mean 17579.367741 # Write request-response latency -system.monitor.writeLatencyHist::gmean 17571.346759 # Write request-response latency -system.monitor.writeLatencyHist::stdev 555.431458 # Write request-response latency +system.monitor.writeLatencyHist::mean 19578.682028 # Write request-response latency +system.monitor.writeLatencyHist::gmean 19571.486505 # Write request-response latency +system.monitor.writeLatencyHist::stdev 552.701557 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency @@ -428,11 +428,11 @@ system.monitor.writeLatencyHist::8192-10239 0 0.00% 0.00% # system.monitor.writeLatencyHist::10240-12287 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::12288-14335 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::14336-16383 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::16384-18431 1620268 97.20% 97.20% # Write request-response latency -system.monitor.writeLatencyHist::18432-20479 30675 1.84% 99.04% # Write request-response latency -system.monitor.writeLatencyHist::20480-22527 12936 0.78% 99.82% # Write request-response latency -system.monitor.writeLatencyHist::22528-24575 2999 0.18% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::24576-26623 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::16384-18431 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::18432-20479 1622054 97.31% 97.31% # Write request-response latency +system.monitor.writeLatencyHist::20480-22527 29447 1.77% 99.08% # Write request-response latency +system.monitor.writeLatencyHist::22528-24575 12825 0.77% 99.85% # Write request-response latency +system.monitor.writeLatencyHist::24576-26623 2552 0.15% 100.00% # Write request-response latency system.monitor.writeLatencyHist::26624-28671 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::28672-30719 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency @@ -526,15 +526,15 @@ system.monitor.ittReqReq::min_value 28000 # Re system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.260000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.290000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.284091 # Outstanding read transactions -system.monitor.outstandingReadsHist::0 26 26.00% 26.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 43 43.00% 69.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 22 22.00% 91.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 4 4.00% 95.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::4 1 1.00% 96.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::5 3 3.00% 99.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.216843 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 22 22.00% 22.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 46 46.00% 68.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 23 23.00% 91.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 5 5.00% 96.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 1 1.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 2 2.00% 99.00% # Outstanding read transactions system.monitor.outstandingReadsHist::6 0 0.00% 99.00% # Outstanding read transactions system.monitor.outstandingReadsHist::7 0 0.00% 99.00% # Outstanding read transactions system.monitor.outstandingReadsHist::8 1 1.00% 100.00% # Outstanding read transactions @@ -551,11 +551,11 @@ system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions -system.monitor.outstandingWritesHist::mean 0.320000 # Outstanding write transactions +system.monitor.outstandingWritesHist::mean 0.340000 # Outstanding write transactions system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions -system.monitor.outstandingWritesHist::stdev 0.468826 # Outstanding write transactions -system.monitor.outstandingWritesHist::0 68 68.00% 68.00% # Outstanding write transactions -system.monitor.outstandingWritesHist::1 32 32.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::stdev 0.476095 # Outstanding write transactions +system.monitor.outstandingWritesHist::0 66 66.00% 66.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::1 34 34.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt index e54e02dca..2416b8ce8 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 31050955853 # Simulator tick rate (ticks/s) -host_mem_usage 209576 # Number of bytes of host memory used -host_seconds 3.22 # Real time elapsed on the host +host_tick_rate 16305869412 # Simulator tick rate (ticks/s) +host_mem_usage 265756 # Number of bytes of host memory used +host_seconds 6.13 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory @@ -191,8 +191,8 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 8533120 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 853312 # Number of bytes written system.monitor.readLatencyHist::samples 1 # Read request-response latency -system.monitor.readLatencyHist::mean 30000 # Read request-response latency -system.monitor.readLatencyHist::gmean 30000.000000 # Read request-response latency +system.monitor.readLatencyHist::mean 32000 # Read request-response latency +system.monitor.readLatencyHist::gmean 32000.000000 # Read request-response latency system.monitor.readLatencyHist::stdev nan # Read request-response latency system.monitor.readLatencyHist::0-2047 0 0.00% 0.00% # Read request-response latency system.monitor.readLatencyHist::2048-4095 0 0.00% 0.00% # Read request-response latency @@ -208,16 +208,16 @@ system.monitor.readLatencyHist::20480-22527 0 0.00% 0.00% # system.monitor.readLatencyHist::22528-24575 0 0.00% 0.00% # Read request-response latency system.monitor.readLatencyHist::24576-26623 0 0.00% 0.00% # Read request-response latency system.monitor.readLatencyHist::26624-28671 0 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::28672-30719 1 100.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::30720-32767 0 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::28672-30719 0 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::30720-32767 1 100.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::32768-34815 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::34816-36863 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1 # Read request-response latency system.monitor.writeLatencyHist::samples 13333 # Write request-response latency -system.monitor.writeLatencyHist::mean 30000.024601 # Write request-response latency -system.monitor.writeLatencyHist::gmean 30000.024467 # Write request-response latency +system.monitor.writeLatencyHist::mean 32000.024601 # Write request-response latency +system.monitor.writeLatencyHist::gmean 32000.024475 # Write request-response latency system.monitor.writeLatencyHist::stdev 2.840599 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency @@ -233,8 +233,8 @@ system.monitor.writeLatencyHist::20480-22527 0 0.00% 0.00% system.monitor.writeLatencyHist::22528-24575 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::24576-26623 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::26624-28671 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::28672-30719 13333 100.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::28672-30719 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::30720-32767 13333 100.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 85445221a..925ba174e 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316500 # Number of ticks simulated final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1507080 # Simulator instruction rate (inst/s) -host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1946992285 # Simulator tick rate (ticks/s) -host_mem_usage 297820 # Number of bytes of host memory used -host_seconds 60.98 # Real time elapsed on the host +host_inst_rate 1465795 # Simulator instruction rate (inst/s) +host_op_rate 1465795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1893656296 # Simulator tick rate (ticks/s) +host_mem_usage 298240 # Number of bytes of host memory used +host_seconds 62.70 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1442.043368 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043368 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id @@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23424000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23424000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 93300000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 93300000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116724000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 116724000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116724000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 116724000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -221,22 +221,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53375.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1418.052751 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052759 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052751 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id @@ -298,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 207947500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 207947500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 207947500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 207947500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 207947500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 207947500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 212202500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 212202500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 212202500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 212202500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 212202500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 212202500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24935.663925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24935.663925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24935.663925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24935.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24935.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24935.663925 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070538 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2074.070486 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017985 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017940 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257369 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy @@ -337,72 +337,78 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 91577 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 91577 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5889 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits system.cpu.l2cache.overall_hits::total 5968 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2621 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2621 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 422 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 422 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses 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-system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8510 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 475 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 475 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.307991 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888421 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888421 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.190767 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency @@ -417,84 +423,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2621 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2621 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 422 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 422 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73185000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73185000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 111393000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 111393000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17935000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17935000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111393000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 202513000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111393000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 202513000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.307991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888421 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.190767 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.190767 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.190767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.190767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 17571 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10840 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 17571 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10840 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 17571 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8892500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3043 # Transaction distribution system.membus.trans_dist::ReadResp 3043 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3043 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index c495da061..dfc2f4ccb 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230173 # Nu sim_ticks 230173358500 # Number of ticks simulated final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 794003 # Simulator instruction rate (inst/s) -host_op_rate 837080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1063522318 # Simulator tick rate (ticks/s) -host_mem_usage 308720 # Number of bytes of host memory used -host_seconds 216.43 # Real time elapsed on the host +host_inst_rate 1194511 # Simulator instruction rate (inst/s) +host_op_rate 1259316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1599980237 # Simulator tick rate (ticks/s) +host_mem_usage 316228 # Number of bytes of host memory used +host_seconds 143.86 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619271 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.619267 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619271 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619267 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34437000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58544500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58544500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59094500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59094500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93875500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 93875500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93929500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 93929500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52503.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52503.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52503.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52503.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992594 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992590 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992594 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992590 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id @@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 107794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 107794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107794500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109320000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 109320000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109320000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 109320000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109320000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 109320000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35830.875123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35830.875123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663342 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1675.663321 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588816 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036732 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588811 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -447,72 +447,78 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 42317 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 42317 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 57 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 57 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 1322 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 65 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1387 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits system.cpu.l2cache.overall_hits::total 1387 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2361 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1092 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1092 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1729 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1729 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 90862500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33203000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 124065500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90862500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 90862500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33203000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33203000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 3051 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 689 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 689 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 3051 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1789 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 4840 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 3051 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.566699 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52552.053210 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52536.392405 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52536.392405 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency @@ -527,84 +533,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46440500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46440500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73572500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73572500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 26883000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 26883000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73572500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73323500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 146896000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73572500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73323500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 146896000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42552.053210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42552.053210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42536.392405 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42536.392405 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6386 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6386 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2361 # Transaction distribution system.membus.trans_dist::ReadResp 2361 # Transaction distribution system.membus.trans_dist::ReadExReq 1092 # Transaction distribution system.membus.trans_dist::ReadExResp 1092 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index e9f2af2a4..221e57a79 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu sim_ticks 270563082500 # Number of ticks simulated final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1283602 # Simulator instruction rate (inst/s) -host_op_rate 1283603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1795321724 # Simulator tick rate (ticks/s) -host_mem_usage 297332 # Number of bytes of host memory used -host_seconds 150.70 # Real time elapsed on the host +host_inst_rate 1293394 # Simulator instruction rate (inst/s) +host_op_rate 1293395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1809017316 # Simulator tick rate (ticks/s) +host_mem_usage 297764 # Number of bytes of host memory used +host_seconds 149.56 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.203936 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1237.203933 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203933 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id @@ -187,16 +187,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1575 system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26643000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26643000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57619500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57619500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 53500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84262500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 84262500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84262500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 54000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 54000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 85050000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 85050000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 85050000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 85050000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses @@ -207,24 +207,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 54000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 54000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579164 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.579161 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579161 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id @@ -286,34 +286,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292386500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 292386500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292386500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 292386500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292386500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 292386500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298530500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 298530500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298530500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 298530500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298530500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 298530500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23794.474284 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23794.474284 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.474284 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.474284 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340853 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2678.340822 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy @@ -325,67 +325,72 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits 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number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188843000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26145000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 214988000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 188843000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 188843000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 26145000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 26145000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.122100 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.139005 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency @@ -400,84 +405,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145678500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20169000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 165847500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43659000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43659000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145678500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63828000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 209506500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145678500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63828000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 209506500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45815000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45815000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 152873000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 152873000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 21165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 21165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 152873000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66980000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 219853000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 152873000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66980000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 219853000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.139005 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.139005 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13866 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13866 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 24228 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13866 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4095 # Transaction distribution system.membus.trans_dist::ReadResp 4095 # Transaction distribution system.membus.trans_dist::ReadExReq 1078 # Transaction distribution system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index af03b59c5..395ca7a25 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957500 # Number of ticks simulated final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 582427 # Simulator instruction rate (inst/s) -host_op_rate 976201 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1106694320 # Simulator tick rate (ticks/s) -host_mem_usage 282016 # Number of bytes of host memory used -host_seconds 226.76 # Real time elapsed on the host +host_inst_rate 750520 # Simulator instruction rate (inst/s) +host_op_rate 1257940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1426094126 # Simulator tick rate (ticks/s) +host_mem_usage 340216 # Number of bytes of host memory used +host_seconds 175.97 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -93,12 +93,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.457561 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457561 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id @@ -176,14 +176,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1905 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17365500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17365500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102451500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 102451500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102451500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 102451500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses @@ -192,22 +192,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.296632 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296632 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id @@ -269,34 +269,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173278500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 173278500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173278500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 173278500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173278500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 173278500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175625500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175625500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175625500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175625500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175625500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175625500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.891351 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37414.891351 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178675 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2058.178650 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978570 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178361 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy @@ -308,72 +308,78 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits system.cpu.l2cache.overall_hits::total 1864 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149117500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16801500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 165919000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 149117500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 149117500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16801500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 16801500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52506.161972 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52504.687500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52504.687500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency @@ -388,84 +394,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66937500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66937500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 120717500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 120717500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13601500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13601500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120717500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 80539000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 201256500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120717500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 80539000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 201256500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42506.161972 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42506.161972 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.687500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.687500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6606 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9476 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3160 # Transaction distribution system.membus.trans_dist::ReadResp 3160 # Transaction distribution system.membus.trans_dist::ReadExReq 1575 # Transaction distribution system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) |