diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/quick/se | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/quick/se')
10 files changed, 1297 insertions, 791 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index b09aafac2..07eaff0f1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 0ff2f61a7..cfed15046 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21065000 # Number of ticks simulated final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31290 # Simulator instruction rate (inst/s) -host_op_rate 31288 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103426086 # Simulator tick rate (ticks/s) -host_mem_usage 226120 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 36663 # Simulator instruction rate (inst/s) +host_op_rate 36659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121177991 # Simulator tick rate (ticks/s) +host_mem_usage 273132 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -214,8 +214,8 @@ system.membus.reqLayer0.occupancy 619000 # La system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.6 # Layer utilization (%) -system.cpu.branchPred.lookups 2884 # Number of BP lookups -system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2883 # Number of BP lookups +system.cpu.branchPred.condPredicted 1697 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups system.cpu.branchPred.BTBHits 756 # Number of BTB hits @@ -259,11 +259,11 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 42131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8531 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2883 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2963 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -271,24 +271,24 @@ system.cpu.fetch.PendingTrapStallCycles 747 # Nu system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.095282 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.492986 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12150 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.10% 82.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 84.05% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.69% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 240 1.59% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.21% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1255 8.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.068429 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.392894 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2764 # Number of cycles decode is running diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 8335373d5..90b395123 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,19 +518,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=MipsInterrupts +eventq_index=0 [system.cpu.isa] type=MipsISA +eventq_index=0 num_threads=1 num_vpes=1 [system.cpu.itb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -484,6 +543,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -506,12 +566,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -521,6 +583,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -530,7 +593,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -544,11 +608,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -568,6 +634,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -579,17 +646,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 1c2de0612..3589948bc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21898500 # Number of ticks simulated final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64871 # Simulator instruction rate (inst/s) -host_op_rate 64859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 275425114 # Simulator tick rate (ticks/s) -host_mem_usage 255508 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 34889 # Simulator instruction rate (inst/s) +host_op_rate 34885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148144968 # Simulator tick rate (ticks/s) +host_mem_usage 274956 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -208,9 +208,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 20.4 # Layer utilization (%) system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted @@ -272,31 +272,31 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 8890 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3026 # Number of cycles decode is running +system.cpu.decode.RunCycles 3025 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 9072 # Number of cycles rename is idle system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2899 # Number of cycles rename is running +system.cpu.rename.RunCycles 2898 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer @@ -423,7 +423,7 @@ system.cpu.iew.iewSquashCycles 868 # Nu system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions @@ -538,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 451 # n system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses system.cpu.icache.overall_misses::total 451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31196500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31196500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31196500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31196500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31196500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31196500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses @@ -556,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69171.840355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69171.840355 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -582,32 +582,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338 system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24201750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24201750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24201750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24201750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24201750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24201750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.801023 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923735 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy @@ -629,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23833750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30860500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23833750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 34674750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23833750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34674750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -662,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71145.522388 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72442.488263 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72693.396226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72693.396226 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index ffa288769..708085ca5 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,20 +518,25 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa0] type=AlphaISA +eventq_index=0 [system.cpu.isa1] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -485,6 +545,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -507,12 +568,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -522,6 +585,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload0] type=LiveProcess @@ -531,7 +595,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -550,7 +615,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -564,11 +630,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -588,6 +656,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -599,17 +668,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 15c806f18..b48213381 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24229500 # Number of ticks simulated final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81251 # Simulator instruction rate (inst/s) -host_op_rate 81244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154440285 # Simulator tick rate (ticks/s) -host_mem_usage 227736 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 38113 # Simulator instruction rate (inst/s) +host_op_rate 38111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72448291 # Simulator tick rate (ticks/s) +host_mem_usage 273720 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory @@ -219,34 +219,34 @@ system.membus.reqLayer0.utilization 5.1 # La system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 37.4 # Layer utilization (%) system.cpu.branchPred.lookups 6676 # Number of BP lookups -system.cpu.branchPred.condPredicted 3773 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 3772 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4746 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 4747 # Number of BTB lookups system.cpu.branchPred.BTBHits 873 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.394437 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 18.390562 # BTB Hit Percentage system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4588 # DTB read hits +system.cpu.dtb.read_hits 4587 # DTB read hits system.cpu.dtb.read_misses 111 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4699 # DTB read accesses +system.cpu.dtb.read_accesses 4698 # DTB read accesses system.cpu.dtb.write_hits 2013 # DTB write hits -system.cpu.dtb.write_misses 87 # DTB write misses +system.cpu.dtb.write_misses 86 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2100 # DTB write accesses -system.cpu.dtb.data_hits 6601 # DTB hits -system.cpu.dtb.data_misses 198 # DTB misses +system.cpu.dtb.write_accesses 2099 # DTB write accesses +system.cpu.dtb.data_hits 6600 # DTB hits +system.cpu.dtb.data_misses 197 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6799 # DTB accesses -system.cpu.itb.fetch_hits 5373 # ITB hits +system.cpu.dtb.data_accesses 6797 # DTB accesses +system.cpu.itb.fetch_hits 5374 # ITB hits system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5430 # ITB accesses +system.cpu.itb.fetch_accesses 5431 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -265,50 +265,50 @@ system.cpu.numCycles 48460 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 37136 # Number of instructions fetch has processed +system.cpu.fetch.Insts 37128 # Number of instructions fetch has processed system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 6222 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5373 # Number of cache lines fetched +system.cpu.fetch.CacheLines 5374 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 29553 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.256590 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.686803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 29555 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.256234 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.686456 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23330 78.94% 78.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23333 78.95% 78.95% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 457 1.55% 87.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 520 1.76% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3046 10.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 457 1.55% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 520 1.76% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3045 10.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 29553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 29555 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.766323 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40475 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9887 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5338 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 491 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2736 # Number of cycles decode is squashing +system.cpu.fetch.rate 0.766158 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40476 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9889 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5340 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2737 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2736 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 41176 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6161 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 2737 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41177 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6164 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 5023 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2246 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30191 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.UnblockCycles 2245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30189 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made @@ -318,31 +318,31 @@ system.cpu.rename.CommittedMaps 9140 # Nu system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 49 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6118 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 6114 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3035 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 3034 # Number of loads inserted to the mem dependence unit. system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26321 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsAdded 26322 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 29553 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.731770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.328577 # Number of insts issued each cycle +system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 29555 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.731721 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.328495 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 20214 68.40% 68.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3351 11.34% 79.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2621 8.87% 88.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1590 5.38% 93.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1011 3.42% 97.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20216 68.40% 68.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3350 11.33% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2622 8.87% 88.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1591 5.38% 93.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1010 3.42% 97.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle @@ -350,7 +350,7 @@ system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 29553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 29555 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available @@ -421,36 +421,36 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10800 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7137 65.92% 65.94% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.95% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.95% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2587 23.90% 89.87% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7138 65.93% 65.95% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.96% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.96% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2586 23.89% 89.87% # Type of FU issued system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued @@ -463,9 +463,9 @@ system.cpu.iq.fu_busy_cnt::total 185 # FU system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 73079 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 73081 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 18684 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses @@ -483,34 +483,34 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 1 # system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1852 # Number of loads squashed +system.cpu.iew.lsq.thread1.squashedLoads 1851 # Number of loads squashed system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 408 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2736 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 2737 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6005 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 6004 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20164 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 20163 # Number of executed instructions system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2366 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1462 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts::1 2365 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed @@ -518,47 +518,47 @@ system.cpu.iew.exec_nop::0 109 # nu system.cpu.iew.exec_nop::1 90 # number of nop insts executed system.cpu.iew.exec_nop::total 199 # number of nop insts executed system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3414 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6831 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3412 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6829 # number of memory reference insts executed system.cpu.iew.exec_branches::0 1584 # Number of branches executed system.cpu.iew.exec_branches::1 1595 # Number of branches executed system.cpu.iew.exec_branches::total 3179 # Number of branches executed system.cpu.iew.exec_stores::0 1066 # Number of stores executed -system.cpu.iew.exec_stores::1 1048 # Number of stores executed -system.cpu.iew.exec_stores::total 2114 # Number of stores executed -system.cpu.iew.exec_rate 0.416096 # Inst execution rate +system.cpu.iew.exec_stores::1 1047 # Number of stores executed +system.cpu.iew.exec_stores::total 2113 # Number of stores executed +system.cpu.iew.exec_rate 0.416075 # Inst execution rate system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9370 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18703 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9371 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18704 # cumulative count of insts written-back system.cpu.iew.wb_producers::0 4798 # num instructions producing a value -system.cpu.iew.wb_producers::1 4829 # num instructions producing a value -system.cpu.iew.wb_producers::total 9627 # num instructions producing a value +system.cpu.iew.wb_producers::1 4830 # num instructions producing a value +system.cpu.iew.wb_producers::total 9628 # num instructions producing a value system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6319 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12566 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6320 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12567 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.193355 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.385947 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.193376 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.385968 # insts written-back per cycle system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.764203 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.766115 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.764241 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.766134 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29486 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.433392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.196069 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 29488 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.196034 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23745 80.53% 80.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23747 80.53% 80.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 3040 10.31% 90.84% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 1123 3.81% 94.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 504 1.71% 96.36% # Number of insts commited each cycle @@ -570,7 +570,7 @@ system.cpu.commit.committed_per_cycle::8 211 0.72% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29488 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6390 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -605,10 +605,10 @@ system.cpu.commit.bw_lim_events 211 # nu system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132694 # The number of ROB reads -system.cpu.rob.rob_writes 55968 # The number of ROB writes +system.cpu.rob.rob_reads 132697 # The number of ROB reads +system.cpu.rob.rob_writes 55969 # The number of ROB writes system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18907 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 18905 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6373 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated @@ -620,8 +620,8 @@ system.cpu.cpi_total 3.802275 # CP system.cpu.ipc::0 0.131511 # IPC: Instructions Per Cycle system.cpu.ipc::1 0.131490 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25291 # number of integer regfile reads -system.cpu.int_regfile_writes 14128 # number of integer regfile writes +system.cpu.int_regfile_reads 25289 # number of integer regfile reads +system.cpu.int_regfile_writes 14129 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -649,19 +649,19 @@ system.cpu.icache.tags.replacements::0 6 # nu system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 6 # number of replacements system.cpu.icache.tags.tagsinuse 312.493120 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4319 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 4320 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.899361 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.900958 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4319 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4319 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4319 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4319 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4319 # number of overall hits -system.cpu.icache.overall_hits::total 4319 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 4320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4320 # number of overall hits +system.cpu.icache.overall_hits::total 4320 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses @@ -674,18 +674,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 69934495 system.cpu.icache.demand_miss_latency::total 69934495 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 69934495 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 69934495 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5368 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5368 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5368 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5368 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195417 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195417 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195417 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195417 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195417 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195417 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 5369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5369 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5369 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5369 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5369 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195381 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195381 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195381 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195381 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195381 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195381 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency @@ -718,12 +718,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46953746 system.cpu.icache.demand_mshr_miss_latency::total 46953746 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46953746 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 46953746 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116617 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116617 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116617 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 80c73e0c8..de3e77970 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bu boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,21 +518,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu0.isa] type=SparcISA +eventq_index=0 [system.cpu0.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu0.workload] type=LiveProcess @@ -487,7 +547,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +eventq_index=0 +executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -527,6 +588,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -591,6 +654,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -606,6 +670,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -628,26 +693,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -656,16 +726,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -674,22 +747,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -698,22 +775,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -722,10 +803,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -734,124 +817,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -860,10 +964,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -872,16 +978,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -890,10 +999,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -904,6 +1015,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -926,21 +1038,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu1.isa] type=SparcISA +eventq_index=0 [system.cpu1.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -971,6 +1088,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -1035,6 +1154,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -1050,6 +1170,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -1072,26 +1193,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu2.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -1100,16 +1226,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -1118,22 +1247,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -1142,22 +1275,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -1166,10 +1303,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -1178,124 +1317,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -1304,10 +1464,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -1316,16 +1478,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -1334,10 +1499,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -1348,6 +1515,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -1370,21 +1538,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu2.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu2.isa] type=SparcISA +eventq_index=0 [system.cpu2.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu3] type=DerivO3CPU @@ -1415,6 +1588,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -1479,6 +1654,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -1494,6 +1670,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -1516,26 +1693,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu3.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 +eventq_index=0 [system.cpu3.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu3.fuPool.FUList0.opList [system.cpu3.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -1544,16 +1726,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 [system.cpu3.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu3.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -1562,22 +1747,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 [system.cpu3.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu3.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu3.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -1586,22 +1775,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 [system.cpu3.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu3.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu3.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -1610,10 +1803,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu3.fuPool.FUList4.opList [system.cpu3.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -1622,124 +1817,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 [system.cpu3.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu3.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu3.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu3.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu3.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu3.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu3.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu3.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu3.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu3.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu3.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu3.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu3.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu3.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu3.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu3.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu3.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu3.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu3.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu3.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -1748,10 +1964,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu3.fuPool.FUList6.opList [system.cpu3.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -1760,16 +1978,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 [system.cpu3.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu3.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -1778,10 +1999,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu3.fuPool.FUList8.opList [system.cpu3.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -1792,6 +2015,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -1814,25 +2038,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu3.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu3.isa] type=SparcISA +eventq_index=0 [system.cpu3.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.l2c] @@ -1841,6 +2071,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1863,12 +2094,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1888,6 +2121,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1899,19 +2133,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1921,5 +2159,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index b78a3e4ce..34d426284 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000111 # Nu sim_ticks 111025500 # Number of ticks simulated final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119782 # Simulator instruction rate (inst/s) -host_op_rate 119782 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12747983 # Simulator tick rate (ticks/s) -host_mem_usage 275656 # Number of bytes of host memory used -host_seconds 8.71 # Real time elapsed on the host +host_inst_rate 77886 # Simulator instruction rate (inst/s) +host_op_rate 77886 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8289137 # Simulator tick rate (ticks/s) +host_mem_usage 295244 # Number of bytes of host memory used +host_seconds 13.39 # Real time elapsed on the host sim_insts 1043212 # Number of instructions simulated sim_ops 1043212 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory @@ -204,14 +204,14 @@ system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # By system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation -system.physmem.totQLat 4010250 # Total ticks spent queuing -system.physmem.totMemAccLat 18159000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4008250 # Total ticks spent queuing +system.physmem.totMemAccLat 18157000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers system.physmem.totBankLat 10848750 # Total ticks spent accessing banks -system.physmem.avgQLat 6076.14 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6073.11 # Average queueing delay per DRAM burst system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27513.64 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27510.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s @@ -242,19 +242,19 @@ system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 931500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 932000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6289925 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6290425 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 417.165472 # Cycle average of tags in use +system.l2c.tags.tagsinuse 417.163639 # Cycle average of tags in use system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 285.088059 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.417692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 285.086488 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.417431 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor @@ -339,38 +339,38 @@ system.l2c.overall_misses::cpu2.data 20 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 674 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24801500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 24802000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 1162500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.inst 5361500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 584250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 583750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 38166000 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 6725000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 958250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9622500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24801500 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 957750 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9622000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 24802000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 12337000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 1162500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.inst 5361500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 584250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 1032750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 47788500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24801500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu3.inst 583750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1032250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 47788000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 24802000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 12337000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 1162500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 5361500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 584250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 1032750 # number of overall miss cycles -system.l2c.overall_miss_latency::total 47788500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 583750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1032250 # number of overall miss cycles +system.l2c.overall_miss_latency::total 47788000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) @@ -447,38 +447,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.800000 # mi system.l2c.overall_miss_rate::cpu3.inst 0.020979 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69084.958217 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69086.350975 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64861.111111 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 70287.292818 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79854.166667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73454.198473 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79812.500000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73450.381679 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70902.818991 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 64861.111111 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 79403.846154 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70902.077151 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70902.818991 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 64861.111111 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 79403.846154 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70902.077151 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,9 +545,9 @@ system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 676500 system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4287250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 30807000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 30806500 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 210021 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 217519 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 170017 # number of UpgradeReq MSHR miss cycles @@ -556,26 +556,26 @@ system.l2c.UpgradeReq_mshr_miss_latency::total 777575 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5552000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807750 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7989500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807250 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7989000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 20238250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 10253500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 676500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 4287250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 369750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 870250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 38796500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 369250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 869750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 38795500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 20238250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 10253500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 676500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 4287250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 369750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 870250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 38796500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 369250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 869750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 38795500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses @@ -619,9 +619,9 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67650 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 58236.294896 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 58235.349716 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10875.950000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency @@ -630,26 +630,26 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59063.829787 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67312.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60988.549618 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67270.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60984.732824 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution @@ -710,7 +710,7 @@ system.cpu0.workload.num_syscalls 89 # Nu system.cpu0.numCycles 222052 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17258 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.icacheStallCycles 17259 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken @@ -720,12 +720,12 @@ system.cpu0.fetch.BlockedCycles 13993 # Nu system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 489 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 197037 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503043 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.216869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 488 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 197038 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503030 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216871 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35208 17.87% 17.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35209 17.87% 17.87% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) @@ -737,17 +737,17 @@ system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Nu system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 197037 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 197038 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17850 # Number of cycles decode is idle +system.cpu0.decode.IdleCycles 17851 # Number of cycles decode is idle system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18506 # Number of cycles rename is idle +system.cpu0.rename.IdleCycles 18507 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running @@ -769,20 +769,20 @@ system.cpu0.memDep0.conflictingLoads 76026 # Nu system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 405049 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued +system.cpu0.iq.iqInstsIssued 405044 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedOperandsExamined 9396 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 197037 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055700 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097210 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 197038 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055664 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097184 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34075 17.29% 17.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34076 17.29% 17.29% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77366 39.26% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1557 0.79% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77371 39.27% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1552 0.79% 99.48% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle @@ -790,7 +790,7 @@ system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Nu system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 197037 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 197038 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available @@ -855,21 +855,21 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155510 38.39% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155505 38.39% 80.69% # Type of FU issued system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 405049 # Type of FU issued -system.cpu0.iq.rate 1.824118 # Inst issue rate +system.cpu0.iq.FU_type_0::total 405044 # Type of FU issued +system.cpu0.iq.rate 1.824095 # Inst issue rate system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1007474 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_reads 1007470 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 403236 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_wakeup_accesses 403231 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 405260 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 405255 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -898,29 +898,29 @@ system.cpu0.iew.predictedNotTakenIncorrect 1114 # system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecSquashedInsts 1066 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 76577 # number of nop insts executed system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed system.cpu0.iew.exec_branches 80250 # Number of branches executed system.cpu0.iew.exec_stores 78134 # Number of stores executed system.cpu0.iew.exec_rate 1.819295 # Inst execution rate -system.cpu0.iew.wb_sent 403577 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 403236 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238895 # num instructions producing a value -system.cpu0.iew.wb_consumers 241362 # num instructions consuming a value +system.cpu0.iew.wb_sent 403557 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 403231 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238890 # num instructions producing a value +system.cpu0.iew.wb_consumers 241357 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.815953 # insts written-back per cycle +system.cpu0.iew.wb_rate 1.815931 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194597 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430500 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136019 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 194598 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430487 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136021 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34534 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34535 17.75% 17.75% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle @@ -932,7 +932,7 @@ system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # N system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194597 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 194598 # Number of insts commited each cycle system.cpu0.commit.committedInsts 472968 # Number of instructions committed system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed @@ -945,10 +945,10 @@ system.cpu0.commit.int_insts 318742 # Nu system.cpu0.commit.function_calls 223 # Number of function calls committed. system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 678234 # The number of ROB reads +system.cpu0.rob.rob_reads 678235 # The number of ROB reads system.cpu0.rob.rob_writes 972657 # The number of ROB writes system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25015 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 25014 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.committedInsts 396861 # Number of Instructions Simulated system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated @@ -957,19 +957,19 @@ system.cpu0.cpi_total 0.559521 # CP system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 722661 # number of integer regfile reads -system.cpu0.int_regfile_writes 325773 # number of integer regfile writes +system.cpu0.int_regfile_writes 325753 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.313735 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 241.312438 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.313735 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471316 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471316 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.312438 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471313 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471313 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits @@ -982,12 +982,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 756 # system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35940245 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35940245 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35940245 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35940245 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35940245 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35940245 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35939745 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35939745 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35939745 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35939745 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35939745 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35939745 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses @@ -1000,12 +1000,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47540.006614 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47540.006614 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47539.345238 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47539.345238 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47539.345238 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47539.345238 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1026,34 +1026,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27686252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686252 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27686252 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686752 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686752 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686752 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27686752 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686752 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27686752 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47086.312925 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.026994 # Cycle average of tags in use +system.cpu0.dcache.tags.tagsinuse 142.026071 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026994 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026071 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277395 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277395 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits @@ -1245,20 +1245,20 @@ system.cpu1.memDep0.conflictingLoads 34021 # Nu system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 211924 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu1.iq.iqInstsIssued 211912 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10911 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedOperandsExamined 10947 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.206019 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.291588 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.205950 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.291467 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 32801 18.67% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3291 1.87% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 32813 18.67% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3279 1.87% 99.13% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle @@ -1331,21 +1331,21 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 75900 35.81% 85.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 75888 35.81% 85.24% # Type of FU issued system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 211924 # Type of FU issued -system.cpu1.iq.rate 1.191033 # Inst issue rate +system.cpu1.iq.FU_type_0::total 211912 # Type of FU issued +system.cpu1.iq.rate 1.190965 # Inst issue rate system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 599908 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_reads 599896 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 210080 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_wakeup_accesses 210068 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 212190 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 212178 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -1374,20 +1374,20 @@ system.cpu1.iew.predictedNotTakenIncorrect 919 # system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecSquashedInsts 1183 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed system.cpu1.iew.exec_nop 34927 # number of nop insts executed system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed system.cpu1.iew.exec_branches 44131 # Number of branches executed system.cpu1.iew.exec_stores 31196 # Number of stores executed system.cpu1.iew.exec_rate 1.184317 # Inst execution rate -system.cpu1.iew.wb_sent 210404 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 210080 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 116723 # num instructions producing a value -system.cpu1.iew.wb_consumers 121388 # num instructions consuming a value +system.cpu1.iew.wb_sent 210356 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 210068 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 116711 # num instructions producing a value +system.cpu1.iew.wb_consumers 121376 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.180669 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.961570 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.180602 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.961566 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards @@ -1434,17 +1434,17 @@ system.cpu1.cpi_total 0.899810 # CP system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads system.cpu1.int_regfile_reads 358439 # number of integer regfile reads -system.cpu1.int_regfile_writes 167816 # number of integer regfile writes +system.cpu1.int_regfile_writes 167768 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.730522 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 76.730517 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730522 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730517 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits @@ -1459,12 +1459,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 476 # system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses system.cpu1.icache.overall_misses::total 476 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7185993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7185993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7185993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7185993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7185993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7185993 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7186493 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7186493 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7186493 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7186493 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7186493 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7186493 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses @@ -1477,12 +1477,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15096.623950 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15096.623950 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15097.674370 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15097.674370 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15097.674370 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15097.674370 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1503,24 +1503,24 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5726006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726006 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5726006 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726506 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726506 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726506 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5726506 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726506 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5726506 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13379.686916 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use @@ -1648,66 +1648,66 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51290 # Number of BP lookups +system.cpu2.branchPred.lookups 51289 # Number of BP lookups system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45092 # Number of BTB lookups +system.cpu2.branchPred.BTBLookups 45091 # Number of BTB lookups system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.465360 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 98.467543 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu2.numCycles 177568 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28807 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 286591 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51290 # Number of branches that fetch encountered +system.cpu2.fetch.icacheStallCycles 28811 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 286582 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51289 # Number of branches that fetch encountered system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 100996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.Cycles 100994 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31176 # Number of cycles fetch has spent blocked +system.cpu2.fetch.BlockedCycles 31174 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19752 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.CacheLines 19751 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.666178 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.140016 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.666126 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.139968 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 71009 41.28% 41.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51379 29.87% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 71011 41.28% 41.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51378 29.87% 71.15% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3272 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3271 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288847 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.613979 # Number of inst fetches per cycle +system.cpu2.fetch.branchRate 0.288841 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.613928 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 27885 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 95101 # Number of cycles decode is running +system.cpu2.decode.BlockedCycles 27886 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 95100 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283083 # Number of instructions handled by decode +system.cpu2.decode.DecodedInsts 283075 # Number of instructions handled by decode system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12251 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90316 # Number of cycles rename is running +system.cpu2.rename.serializeStallCycles 12252 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90315 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 280840 # Number of instructions processed by rename +system.cpu2.rename.RenamedInsts 280839 # Number of instructions processed by rename system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 538434 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 418653 # Number of integer rename lookups +system.cpu2.rename.RenameLookups 538430 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 418650 # Number of integer rename lookups system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed @@ -1719,20 +1719,20 @@ system.cpu2.memDep0.conflictingLoads 37867 # Nu system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234909 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu2.iq.iqInstsIssued 234900 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedOperandsExamined 10850 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.365710 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.313889 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.365658 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313804 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38461 22.36% 97.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3256 1.89% 99.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38470 22.37% 97.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3247 1.89% 99.09% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle @@ -1805,21 +1805,21 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83601 35.59% 84.27% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83592 35.59% 84.27% # Type of FU issued system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234909 # Type of FU issued -system.cpu2.iq.rate 1.322924 # Inst issue rate +system.cpu2.iq.FU_type_0::total 234900 # Type of FU issued +system.cpu2.iq.rate 1.322873 # Inst issue rate system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 642198 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_reads 642189 # Number of integer instruction queue reads system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 233108 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_wakeup_accesses 233099 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 235192 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 235183 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -1848,20 +1848,20 @@ system.cpu2.iew.predictedNotTakenIncorrect 973 # system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1144 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecSquashedInsts 1135 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 38771 # number of nop insts executed system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed system.cpu2.iew.exec_branches 48001 # Number of branches executed system.cpu2.iew.exec_stores 36873 # Number of stores executed system.cpu2.iew.exec_rate 1.316482 # Inst execution rate -system.cpu2.iew.wb_sent 233421 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 233108 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 131942 # num instructions producing a value -system.cpu2.iew.wb_consumers 136650 # num instructions consuming a value +system.cpu2.iew.wb_sent 233385 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 233099 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131933 # num instructions producing a value +system.cpu2.iew.wb_consumers 136641 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.312782 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.965547 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.312731 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965545 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards @@ -1908,55 +1908,55 @@ system.cpu2.cpi_total 0.798482 # CP system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads system.cpu2.int_regfile_reads 404230 # number of integer regfile reads -system.cpu2.int_regfile_writes 188808 # number of integer regfile writes +system.cpu2.int_regfile_writes 188772 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.236622 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19259 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 82.236554 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19258 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.315294 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.312941 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236622 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236554 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 19259 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19259 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19259 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19259 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19259 # number of overall hits -system.cpu2.icache.overall_hits::total 19259 # number of overall hits +system.cpu2.icache.ReadReq_hits::cpu2.inst 19258 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19258 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19258 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19258 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19258 # number of overall hits +system.cpu2.icache.overall_hits::total 19258 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses system.cpu2.icache.overall_misses::total 493 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11620241 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11620241 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11620241 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11620241 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11620241 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11620241 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19752 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19752 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19752 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19752 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19752 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19752 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024959 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024959 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024959 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024959 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024959 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024959 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23570.468560 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23570.468560 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11621241 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11621241 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11621241 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11621241 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11621241 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11621241 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19751 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19751 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19751 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19751 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19751 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19751 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024961 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024961 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024961 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23572.496957 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23572.496957 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23572.496957 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23572.496957 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1977,32 +1977,32 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9299505 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 9299505 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9299505 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 9299505 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9299505 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 9299505 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021517 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021517 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021517 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21881.188235 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9301005 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 9301005 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9301005 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 9301005 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9301005 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 9301005 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021518 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021518 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021518 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21884.717647 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.142582 # Cycle average of tags in use +system.cpu2.dcache.tags.tagsinuse 26.142591 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142582 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142591 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits @@ -2025,16 +2025,16 @@ system.cpu2.dcache.demand_misses::cpu2.data 485 # system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses system.cpu2.dcache.overall_misses::total 485 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5531640 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5531640 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5532140 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5532140 # number of ReadReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8662651 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8662651 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8662651 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8662651 # number of overall miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8663151 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8663151 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8663151 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8663151 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses) @@ -2055,16 +2055,16 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15987.398844 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 15987.398844 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15988.843931 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 15988.843931 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17861.136082 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17861.136082 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17862.167010 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17862.167010 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2134,13 +2134,13 @@ system.cpu3.branchPred.RASInCorrect 232 # Nu system.cpu3.numCycles 177222 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 28850 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.icacheStallCycles 28851 # Number of cycles fetch is stalled on an Icache miss system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 32602 # Number of cycles fetch has spent blocked +system.cpu3.fetch.BlockedCycles 32601 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps @@ -2165,16 +2165,16 @@ system.cpu3.fetch.rateDist::max_value 8 # Nu system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 34476 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 28632 # Number of cycles decode is blocked +system.cpu3.decode.IdleCycles 34477 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28631 # Number of cycles decode is blocked system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 35171 # Number of cycles rename is idle +system.cpu3.rename.IdleCycles 35172 # Number of cycles rename is idle system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11805 # count of cycles rename stalled for serializing inst +system.cpu3.rename.serializeStallCycles 11804 # count of cycles rename stalled for serializing inst system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename @@ -2194,20 +2194,20 @@ system.cpu3.memDep0.conflictingLoads 38893 # Nu system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 239002 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued +system.cpu3.iq.iqInstsIssued 238990 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10694 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedOperandsExamined 10730 # Number of squashed operands that are examined and possibly removed from graph system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.359356 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.308484 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.359288 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.308373 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 39034 22.20% 97.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3259 1.85% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 39046 22.21% 97.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle @@ -2280,21 +2280,21 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Ty system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 85680 35.85% 84.31% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 85668 35.85% 84.31% # Type of FU issued system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 239002 # Type of FU issued -system.cpu3.iq.rate 1.348602 # Inst issue rate +system.cpu3.iq.FU_type_0::total 238990 # Type of FU issued +system.cpu3.iq.rate 1.348535 # Inst issue rate system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 654188 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_reads 654176 # Number of integer instruction queue reads system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 237209 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_wakeup_accesses 237197 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 239276 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 239264 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -2323,20 +2323,20 @@ system.cpu3.iew.predictedNotTakenIncorrect 929 # system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed system.cpu3.iew.exec_nop 39788 # number of nop insts executed system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed system.cpu3.iew.exec_branches 49028 # Number of branches executed system.cpu3.iew.exec_stores 37424 # Number of stores executed system.cpu3.iew.exec_rate 1.342091 # Inst execution rate -system.cpu3.iew.wb_sent 237529 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 237209 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 134044 # num instructions producing a value -system.cpu3.iew.wb_consumers 138720 # num instructions consuming a value +system.cpu3.iew.wb_sent 237481 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 237197 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 134032 # num instructions producing a value +system.cpu3.iew.wb_consumers 138708 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.338485 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.966292 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.338417 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.966289 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards @@ -2383,17 +2383,17 @@ system.cpu3.cpi_total 0.783392 # CP system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads system.cpu3.int_regfile_reads 410473 # number of integer regfile reads -system.cpu3.int_regfile_writes 191401 # number of integer regfile writes +system.cpu3.int_regfile_writes 191353 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 79.942849 # Cycle average of tags in use +system.cpu3.icache.tags.tagsinuse 79.942822 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942849 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942822 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits @@ -2408,12 +2408,12 @@ system.cpu3.icache.demand_misses::cpu3.inst 475 # system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449245 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6449245 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6449245 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6449245 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6449245 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6449245 # number of overall miss cycles +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449745 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6449745 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6449745 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6449745 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6449745 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6449745 # number of overall miss cycles system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses @@ -2426,12 +2426,12 @@ system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13577.357895 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13577.357895 # average overall miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13578.410526 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13578.410526 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13578.410526 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13578.410526 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2452,32 +2452,32 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223255 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223255 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223255 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5223255 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223255 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5223255 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5223755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223755 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5223755 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12176.585082 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.692253 # Cycle average of tags in use +system.cpu3.dcache.tags.tagsinuse 24.692248 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692253 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692248 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits @@ -2500,16 +2500,16 @@ system.cpu3.dcache.demand_misses::cpu3.data 464 # system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses system.cpu3.dcache.overall_misses::total 464 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4249100 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4249100 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3352512 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3352512 # number of WriteReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4248100 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4248100 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3351512 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3351512 # number of WriteReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7601612 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7601612 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7601612 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7601612 # number of overall miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7599612 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7599612 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7599612 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7599612 # number of overall miss cycles system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses) @@ -2530,16 +2530,16 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656 # average WriteReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12757.057057 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12757.057057 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25584.061069 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 25584.061069 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16378.474138 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16378.474138 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2568,14 +2568,14 @@ system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408738 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408738 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408238 # number of WriteReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2411262 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2411262 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2411262 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2411262 # number of overall MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2410762 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2410762 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2410762 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2410762 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses @@ -2588,14 +2588,14 @@ system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14082.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14082.380000 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 51f67db18..fc54ba8f2 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bu boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -93,11 +99,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -106,6 +114,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,21 +137,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu0.isa] type=SparcISA +eventq_index=0 [system.cpu0.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu0.workload] type=LiveProcess @@ -152,7 +166,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +eventq_index=0 +executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -173,6 +188,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts @@ -199,6 +215,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -221,11 +238,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.icache] @@ -234,6 +253,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -256,21 +276,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu1.isa] type=SparcISA +eventq_index=0 [system.cpu1.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=TimingSimpleCPU @@ -282,6 +307,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu2.interrupts @@ -308,6 +334,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -330,11 +357,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu2.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.icache] @@ -343,6 +372,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -365,21 +395,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu2.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu2.isa] type=SparcISA +eventq_index=0 [system.cpu2.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu3] type=TimingSimpleCPU @@ -391,6 +426,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu3.interrupts @@ -417,6 +453,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -439,11 +476,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu3.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.icache] @@ -452,6 +491,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -474,25 +514,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu3.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu3.isa] type=SparcISA +eventq_index=0 [system.cpu3.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.l2c] @@ -501,6 +547,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -523,12 +570,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -541,6 +590,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -551,6 +601,7 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -560,5 +611,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 8ba84a629..8d5cb3498 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu sim_ticks 262794500 # Number of ticks simulated final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 681070 # Simulator instruction rate (inst/s) -host_op_rate 681053 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 269712940 # Simulator tick rate (ticks/s) -host_mem_usage 243700 # Number of bytes of host memory used -host_seconds 0.97 # Real time elapsed on the host +host_inst_rate 200508 # Simulator instruction rate (inst/s) +host_op_rate 200507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79406810 # Simulator tick rate (ticks/s) +host_mem_usage 291148 # Number of bytes of host memory used +host_seconds 3.31 # Real time elapsed on the host sim_insts 663567 # Number of instructions simulated sim_ops 663567 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory @@ -169,36 +169,36 @@ system.l2c.overall_misses::cpu3.data 16 # nu system.l2c.overall_misses::total 592 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) @@ -277,36 +277,36 @@ system.l2c.overall_miss_rate::cpu3.data 0.640000 # mi system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,28 +385,28 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses @@ -459,28 +459,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution @@ -767,17 +767,17 @@ system.cpu1.num_fp_register_writes 0 # nu system.cpu1.num_mem_refs 58020 # number of memory refs system.cpu1.num_load_insts 41540 # Number of load instructions system.cpu1.num_store_insts 16480 # Number of store instructions -system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles -system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles +system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles +system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits @@ -792,12 +792,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 366 # system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses @@ -810,12 +810,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -830,24 +830,24 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use @@ -878,16 +878,16 @@ system.cpu1.dcache.demand_misses::cpu1.data 263 # system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses system.cpu1.dcache.overall_misses::total 263 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) @@ -908,16 +908,16 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -936,16 +936,16 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses @@ -956,16 +956,16 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 525588 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -985,17 +985,17 @@ system.cpu2.num_fp_register_writes 0 # nu system.cpu2.num_mem_refs 59208 # number of memory refs system.cpu2.num_load_insts 42171 # Number of load instructions system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles -system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles +system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles +system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use +system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits @@ -1010,12 +1010,12 @@ system.cpu2.icache.demand_misses::cpu2.inst 366 # system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5255488 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5255488 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5255488 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5255488 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5255488 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5255488 # number of overall miss cycles +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses @@ -1028,12 +1028,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.256831 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14359.256831 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14359.256831 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14359.256831 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1048,32 +1048,32 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4513512 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4513512 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4513512 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4513512 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4513512 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4513512 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12332 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12332 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use +system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits @@ -1096,16 +1096,16 @@ system.cpu2.dcache.demand_misses::cpu2.data 262 # system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses system.cpu2.dcache.overall_misses::total 262 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2129481 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2129481 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1930500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1930500 # number of WriteReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4059981 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4059981 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4059981 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4059981 # number of overall miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) @@ -1126,16 +1126,16 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14009.743421 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 14009.743421 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17550 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17550 # average WriteReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 15496.110687 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 15496.110687 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1154,16 +1154,16 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses @@ -1174,16 +1174,16 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 525588 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started |