diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/se | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/se')
142 files changed, 9294 insertions, 6567 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index b17544f09..afc8aa811 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index ba10334c5..ff8d4bf12 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 4ce82e64f..fc30a21c8 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000021 # Nu sim_ticks 21216000 # Number of ticks simulated final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36015 # Simulator instruction rate (inst/s) -host_tick_rate 119302866 # Simulator tick rate (ticks/s) -host_mem_usage 207132 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 38129 # Simulator instruction rate (inst/s) +host_op_rate 38124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 126288909 # Simulator tick rate (ticks/s) +host_mem_usage 209388 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30016 # Number of bytes read from this memory system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -68,9 +70,10 @@ system.cpu.comNops 17 # Nu system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed -system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 6404 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads @@ -124,26 +127,39 @@ system.cpu.icache.total_refs 581 # To system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 138.882502 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.067814 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 581 # number of ReadReq hits -system.cpu.icache.demand_hits 581 # number of demand (read+write) hits -system.cpu.icache.overall_hits 581 # number of overall hits -system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses -system.cpu.icache.demand_misses 348 # number of demand (read+write) misses -system.cpu.icache.overall_misses 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19241000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19241000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 929 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 929 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.374596 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.374596 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.374596 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55290.229885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55290.229885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55290.229885 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 138.882502 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067814 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067814 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 581 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 581 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 581 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 581 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 581 # number of overall hits +system.cpu.icache.overall_hits::total 581 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses +system.cpu.icache.overall_misses::total 348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19241000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19241000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19241000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 929 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 929 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 929 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 929 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.374596 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.374596 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.374596 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55290.229885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 46 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 302 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.325081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.325081 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.325081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.384106 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 46 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 46 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 46 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16049000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16049000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.384106 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use @@ -180,32 +199,49 @@ system.cpu.dcache.total_refs 1703 # To system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.671807 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025066 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits -system.cpu.dcache.demand_hits 1703 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1703 # number of overall hits -system.cpu.dcache.ReadReq_misses 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 250 # number of WriteReq misses -system.cpu.dcache.demand_misses 347 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 13555500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19064000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.081857 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.289017 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.169268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54222 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54939.481268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54939.481268 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 102.671807 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 615 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1703 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1703 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1703 # number of overall hits +system.cpu.dcache.overall_hits::total 1703 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 347 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses +system.cpu.dcache.overall_misses::total 347 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5508500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5508500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13555500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19064000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19064000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19064000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19064000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56788.659794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54222 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,32 +250,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 177 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 179 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 177 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 177 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 179 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 179 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 179 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5114000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5114000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3910000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3910000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use @@ -247,31 +289,64 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 195.209568 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005957 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 396 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997481 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 138.958412 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.251157 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005957 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1 # 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number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.l2cache.overall_misses::total 469 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15707000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4995000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3822000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3822000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15707000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8817000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24524000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15707000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8817000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24524000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,30 +355,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 396 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15877000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18819500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18819500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18819500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index db5baf5c5..79efc9749 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 6e993ab1c..684d7e9b2 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 3b3d572bb..49671266a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000012 # Nu sim_ticks 12004500 # Number of ticks simulated final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38695 # Simulator instruction rate (inst/s) -host_tick_rate 72731813 # Simulator tick rate (ticks/s) -host_mem_usage 208040 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 42281 # Simulator instruction rate (inst/s) +host_op_rate 42276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79460110 # Simulator tick rate (ticks/s) +host_mem_usage 210060 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated +sim_ops 6386 # Number of ops (including micro ops) simulated system.physmem.bytes_read 31040 # Number of bytes read from this memory system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -270,6 +272,7 @@ system.cpu.iew.wb_rate 0.374511 # in system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions +system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted @@ -290,7 +293,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle -system.cpu.commit.count 6403 # Number of instructions committed +system.cpu.commit.committedInsts 6403 # Number of instructions committed +system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2050 # Number of memory references committed system.cpu.commit.loads 1185 # Number of loads committed @@ -306,6 +310,7 @@ system.cpu.rob.rob_writes 24313 # Th system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated +system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads @@ -323,26 +328,39 @@ system.cpu.icache.total_refs 1606 # To system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 160.112304 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1606 # number of ReadReq hits -system.cpu.icache.demand_hits 1606 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1606 # number of overall hits -system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.icache.demand_misses 433 # number of demand (read+write) misses -system.cpu.icache.overall_misses 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15431000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15431000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.212359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.212359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.212359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35637.413395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35637.413395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35637.413395 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.112304 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078180 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078180 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1606 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1606 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1606 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1606 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1606 # number of overall hits +system.cpu.icache.overall_hits::total 1606 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses +system.cpu.icache.overall_misses::total 433 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15431000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15431000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15431000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15431000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15431000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212359 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212359 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212359 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35637.413395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,27 +369,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11021000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.153016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.153016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.153016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.717949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 121 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 121 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 121 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 121 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11021000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11021000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11021000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35323.717949 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use @@ -379,32 +400,49 @@ system.cpu.dcache.total_refs 2154 # To system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.290272 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits -system.cpu.dcache.demand_hits 2154 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2154 # number of overall hits -system.cpu.dcache.ReadReq_misses 154 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.demand_misses 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17965000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2664 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.085603 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.191441 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.191441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35698.051948 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35225.490196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35225.490196 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 109.290272 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2154 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2154 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2154 # number of overall hits +system.cpu.dcache.overall_hits::total 2154 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 154 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses +system.cpu.dcache.overall_misses::total 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12467500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12467500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17965000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17965000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17965000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17965000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2664 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2664 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2664 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085603 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.191441 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191441 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35698.051948 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35021.067416 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,32 +451,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 336 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056142 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.065315 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.065315 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36183.168317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6266000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6266000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36183.168317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use @@ -446,31 +490,64 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.643066 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006764 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 485 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14163000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16676500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16676500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 413 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997579 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34376.213592 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34384.536082 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34384.536082 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 160.084939 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 61.558127 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004885 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001879 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006764 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6011500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16676500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 312 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 413 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34292.604502 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34633.663366 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34431.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,30 +556,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12850000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15136000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15136000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997579 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.320388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 412 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9672000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3178000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12850000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9672000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15136000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9672000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5464000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15136000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31099.678457 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31465.346535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini index df86e7077..f91bbd9dc 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout index 9f50fe960..2f9b31423 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 7ceb6a8be..97b8faa6b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 3215000 # Number of ticks simulated final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76916 # Simulator instruction rate (inst/s) -host_tick_rate 38606134 # Simulator tick rate (ticks/s) -host_mem_usage 198176 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 35037 # Simulator instruction rate (inst/s) +host_op_rate 35032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17585099 # Simulator tick rate (ticks/s) +host_mem_usage 199940 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 6431 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini index b9fd9c5f2..dd4aa648f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -66,7 +79,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -134,6 +147,7 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer to_l2_latency=1 transitions_per_cycle=32 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index c2d3c97af..d2cdb9ada 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,26 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/23/2012 04:21:55 +Real time: Feb/12/2012 15:33:22 Profiler Stats -------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.38 -Virtual_time_in_minutes: 0.00633333 -Virtual_time_in_hours: 0.000105556 -Virtual_time_in_days: 4.39815e-06 +Virtual_time_in_seconds: 1.01 +Virtual_time_in_minutes: 0.0168333 +Virtual_time_in_hours: 0.000280556 +Virtual_time_in_days: 1.16898e-05 Ruby_current_time: 279353 Ruby_start_time: 0 Ruby_cycles: 279353 -mbytes_resident: 45.5547 -mbytes_total: 214.371 -resident_ratio: 0.212504 +mbytes_resident: 0 +mbytes_total: 0 ruby_cycles_executed: [ 279354 ] @@ -101,9 +100,9 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 20 count: 9645 average: 0.064282 | standard deviation: 0.540462 | 9495 0 1 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ] +Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 | standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ] Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 2725 average: 0.226789 | standard deviation: 0.997795 | 2576 0 0 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average: 0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ] virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ] @@ -119,11 +118,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11862 -page_faults: 127 +page_reclaims: 13214 +page_faults: 148 swaps: 0 -block_inputs: 22816 -block_outputs: 96 +block_inputs: 2 +block_outputs: 4 Network Stats ------------- @@ -320,11 +319,6 @@ M_I Fwd_GETS [0 ] 0 M_I Fwd_GET_INSTR [0 ] 0 M_I WB_Ack [436 ] 436 -E_I Load [0 ] 0 -E_I Ifetch [0 ] 0 -E_I Store [0 ] 0 -E_I L1_Replacement [0 ] 0 - SINK_WB_ACK Load [0 ] 0 SINK_WB_ACK Ifetch [0 ] 0 SINK_WB_ACK Store [0 ] 0 @@ -348,7 +342,7 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory --- L2Cache --- - Event Counts - L1_GET_INSTR [691 ] 691 -L1_GETS [586 ] 586 +L1_GETS [585 ] 585 L1_GETX [216 ] 216 L1_UPGRADE [0 ] 0 L1_PUTX [436 ] 436 @@ -405,7 +399,7 @@ MT L2_Replacement_clean [352 ] 352 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [3 ] 3 +M_I L1_GETS [2 ] 2 M_I L1_GETX [0 ] 0 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index c93c8f8af..a25a5c879 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:44:57 -gem5 started Jan 23 2012 04:21:53 -gem5 executing on zizzer -command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory +gem5 compiled Feb 12 2012 15:33:08 +gem5 started Feb 12 2012 15:33:21 +gem5 executing on Alis-MacBook-Pro.local +command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index 3bba58631..de3976298 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000279 # Nu sim_ticks 279353 # Number of ticks simulated final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 2836 # Simulator instruction rate (inst/s) -host_tick_rate 123728 # Simulator tick rate (ticks/s) -host_mem_usage 219520 # Number of bytes of host memory used -host_seconds 2.26 # Real time elapsed on the host +host_inst_rate 12170 # Simulator instruction rate (inst/s) +host_op_rate 12169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 530781 # Simulator tick rate (ticks/s) +host_mem_usage 270088 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 279353 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index 607ab419c..38b836011 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -132,6 +145,7 @@ number_of_TBEs=256 recycle_latency=10 request_latency=2 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index ed47704f6..aa46612d8 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:47:36 -gem5 started Jan 23 2012 04:22:12 +gem5 compiled Feb 11 2012 13:06:37 +gem5 started Feb 11 2012 13:53:23 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory +command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 44a6426b2..02467cae9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000224 # Nu sim_ticks 223694 # Number of ticks simulated final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19611 # Simulator instruction rate (inst/s) -host_tick_rate 684980 # Simulator tick rate (ticks/s) -host_mem_usage 219636 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 37589 # Simulator instruction rate (inst/s) +host_op_rate 37585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1312743 # Simulator tick rate (ticks/s) +host_mem_usage 221408 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 223694 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index e664ed4cf..0617e8d38 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -141,6 +154,7 @@ number_of_TBEs=256 recycle_latency=10 retry_threshold=1 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index 6ef144b06..0b4972a17 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:50:16 -gem5 started Jan 23 2012 04:22:25 +gem5 compiled Feb 11 2012 13:07:02 +gem5 started Feb 11 2012 13:54:08 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token +command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 4911f0b0e..e1d06acb6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000232 # Nu sim_ticks 231701 # Number of ticks simulated final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23819 # Simulator instruction rate (inst/s) -host_tick_rate 861729 # Simulator tick rate (ticks/s) -host_mem_usage 217800 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 59077 # Simulator instruction rate (inst/s) +host_op_rate 59067 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2136733 # Simulator tick rate (ticks/s) +host_mem_usage 219660 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 231701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index aa987ffa6..15b38dd1a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -147,6 +160,7 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index fa89dfcd6..9412b907c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:42:19 -gem5 started Jan 23 2012 04:21:43 +gem5 compiled Feb 11 2012 13:05:44 +gem5 started Feb 11 2012 13:52:39 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer +command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index dfbcac63c..87ed3fb4b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000208 # Nu sim_ticks 208400 # Number of ticks simulated final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 24253 # Simulator instruction rate (inst/s) -host_tick_rate 789193 # Simulator tick rate (ticks/s) -host_mem_usage 217184 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 64619 # Simulator instruction rate (inst/s) +host_op_rate 64607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2102096 # Simulator tick rate (ticks/s) +host_mem_usage 218760 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 208400 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 0772d2ee5..3d3a73e3a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -131,6 +144,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 9cf822901..05fd4efdd 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index beb747c41..168276764 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000343 # Nu sim_ticks 342698 # Number of ticks simulated final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32385 # Simulator instruction rate (inst/s) -host_tick_rate 1732860 # Simulator tick rate (ticks/s) -host_mem_usage 218476 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 61504 # Simulator instruction rate (inst/s) +host_op_rate 61493 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3290073 # Simulator tick rate (ticks/s) +host_mem_usage 220236 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 342698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index f51983ecf..3b46c790f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index d977e688b..5e2927c57 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 84a161e81..6278fa873 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000033 # Nu sim_ticks 33007000 # Number of ticks simulated final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110064 # Simulator instruction rate (inst/s) -host_tick_rate 566999999 # Simulator tick rate (ticks/s) -host_mem_usage 206896 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 37663 # Simulator instruction rate (inst/s) +host_op_rate 37658 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 194071847 # Simulator tick rate (ticks/s) +host_mem_usage 209060 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28544 # Number of bytes read from this memory system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 66014 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 6136 # To system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits -system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits -system.cpu.icache.overall_hits 6136 # number of overall hits -system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses -system.cpu.icache.demand_misses 279 # number of demand (read+write) misses -system.cpu.icache.overall_misses 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits +system.cpu.icache.overall_hits::total 6136 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses +system.cpu.icache.overall_misses::total 279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 1882 # To system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025313 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits -system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1882 # number of overall hits -system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits +system.cpu.dcache.overall_hits::total 1882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.dcache.overall_misses::total 168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use @@ -198,31 +229,64 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005626 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.l2cache.overall_misses::total 446 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -231,30 +295,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index f0e8b9ebf..d74613835 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 2afd9a6f8..6aed6d3ac 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:23 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d94c5613d..d93b581f0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000007 # Nu sim_ticks 6833000 # Number of ticks simulated final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46364 # Simulator instruction rate (inst/s) -host_tick_rate 132671945 # Simulator tick rate (ticks/s) -host_mem_usage 207164 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 16400 # Simulator instruction rate (inst/s) +host_op_rate 16398 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46934615 # Simulator tick rate (ticks/s) +host_mem_usage 209144 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated +sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read 17280 # Number of bytes read from this memory system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -269,6 +271,7 @@ system.cpu.iew.wb_rate 0.261872 # in system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions +system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted @@ -289,7 +292,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle -system.cpu.commit.count 2576 # Number of instructions committed +system.cpu.commit.committedInsts 2576 # Number of instructions committed +system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 709 # Number of memory references committed system.cpu.commit.loads 415 # Number of loads committed @@ -305,6 +309,7 @@ system.cpu.rob.rob_writes 10410 # Th system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated +system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads @@ -321,26 +326,39 @@ system.cpu.icache.total_refs 700 # To system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 700 # number of ReadReq hits -system.cpu.icache.demand_hits 700 # number of demand (read+write) hits -system.cpu.icache.overall_hits 700 # number of overall hits -system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses -system.cpu.icache.demand_misses 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.256111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.256111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.256111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 91.574139 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.044714 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.044714 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 700 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 700 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 700 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 700 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 700 # number of overall hits +system.cpu.icache.overall_hits::total 700 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses +system.cpu.icache.overall_misses::total 241 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8777500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8777500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8777500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8777500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8777500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 941 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 941 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.256111 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.256111 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.256111 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,27 +367,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.196599 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.196599 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.196599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 185 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 185 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6554500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6554500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6554500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6554500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6554500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6554500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35429.729730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use @@ -377,32 +398,49 @@ system.cpu.dcache.total_refs 765 # To system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 45.439198 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 543 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.demand_hits 765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 765 # number of overall hits -system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3605000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 6421500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 6421500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 644 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 938 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 938 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.156832 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.184435 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.184435 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 37118.497110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 37118.497110 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 45.439198 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 543 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 543 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 765 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 765 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 765 # number of overall hits +system.cpu.dcache.overall_hits::total 765 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 173 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 173 # number of overall misses +system.cpu.dcache.overall_misses::total 173 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3605000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3605000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2816500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6421500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6421500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6421500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 644 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 644 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 938 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 938 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 938 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 938 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.156832 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.184435 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184435 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35693.069307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39118.055556 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,32 +449,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 88 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3041000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.094720 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.090618 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.090618 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 88 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 88 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2169000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2169000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 872000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 872000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3041000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3041000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094720 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35557.377049 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use @@ -444,30 +488,58 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 120.203882 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003668 # Average percentage of cache occupancy -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 8447500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9278500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9278500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34364.814815 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34364.814815 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 91.660485 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.543397 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000871 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 185 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 246 # 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number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6346000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2932500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9278500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6346000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2932500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9278500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 246 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 185 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 270 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 185 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 270 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.702703 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34450.819672 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,30 +548,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # 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average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5756000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1905500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7661500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 756000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 756000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5756000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8417500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5756000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2661500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8417500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index fad1e21b6..d4970301b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout index fdc12b275..8e9c64562 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 23e50fd7f..d3468c0e9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182014 # Simulator instruction rate (inst/s) -host_tick_rate 91451888 # Simulator tick rate (ticks/s) -host_mem_usage 197324 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 24554 # Simulator instruction rate (inst/s) +host_op_rate 24550 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12358328 # Simulator tick rate (ticks/s) +host_mem_usage 199092 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 2596 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index 89c8aeac1..2a33a674c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -66,7 +79,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -134,6 +147,7 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer to_l2_latency=1 transitions_per_cycle=32 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 1c4da6ce4..9c8b2434f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,26 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/23/2012 04:21:58 +Real time: Feb/12/2012 15:33:21 Profiler Stats -------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.71 +Virtual_time_in_minutes: 0.0118333 +Virtual_time_in_hours: 0.000197222 +Virtual_time_in_days: 8.21759e-06 Ruby_current_time: 104867 Ruby_start_time: 0 Ruby_cycles: 104867 -mbytes_resident: 43.0078 -mbytes_total: 212.113 -resident_ratio: 0.202759 +mbytes_resident: 0 +mbytes_total: 0 ruby_cycles_executed: [ 104868 ] @@ -101,9 +100,9 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 20 count: 3612 average: 0.0636766 | standard deviation: 0.653474 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] +Total_delay_cycles: [binsize: 1 max: 18 count: 3612 average: 0.0625692 | standard deviation: 0.620431 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 2644 average: 0.00075643 | standard deviation: 0.0389028 | 2643 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 968 average: 0.235537 | standard deviation: 1.24505 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 968 average: 0.231405 | standard deviation: 1.18112 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ] virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 2213 average: 0.000903751 | standard deviation: 0.0425243 | 2212 0 1 ] @@ -119,11 +118,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11317 -page_faults: 0 +page_reclaims: 12663 +page_faults: 71 swaps: 0 block_inputs: 0 -block_outputs: 88 +block_outputs: 0 Network Stats ------------- @@ -320,11 +319,6 @@ M_I Fwd_GETS [0 ] 0 M_I Fwd_GET_INSTR [0 ] 0 M_I WB_Ack [124 ] 124 -E_I Load [0 ] 0 -E_I Ifetch [0 ] 0 -E_I Store [0 ] 0 -E_I L1_Replacement [0 ] 0 - SINK_WB_ACK Load [0 ] 0 SINK_WB_ACK Ifetch [0 ] 0 SINK_WB_ACK Store [0 ] 0 @@ -348,8 +342,8 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory --- L2Cache --- - Event Counts - L1_GET_INSTR [300 ] 300 -L1_GETS [206 ] 206 -L1_GETX [70 ] 70 +L1_GETS [205 ] 205 +L1_GETX [69 ] 69 L1_UPGRADE [0 ] 0 L1_PUTX [124 ] 124 L1_PUTX_old [0 ] 0 @@ -405,8 +399,8 @@ MT L2_Replacement_clean [141 ] 141 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [2 ] 2 -M_I L1_GETX [2 ] 2 +M_I L1_GETS [1 ] 1 +M_I L1_GETX [1 ] 1 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 M_I L1_PUTX_old [0 ] 0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index dc0ba2922..22e5bbd3f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:44:57 -gem5 started Jan 23 2012 04:21:56 -gem5 executing on zizzer -command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory +gem5 compiled Feb 12 2012 15:33:08 +gem5 started Feb 12 2012 15:33:21 +gem5 executing on Alis-MacBook-Pro.local +command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index ebac3fa83..bb0141a2a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000105 # Nu sim_ticks 104867 # Number of ticks simulated final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 1196 # Simulator instruction rate (inst/s) -host_tick_rate 48657 # Simulator tick rate (ticks/s) -host_mem_usage 217208 # Number of bytes of host memory used -host_seconds 2.16 # Real time elapsed on the host +host_inst_rate 10837 # Simulator instruction rate (inst/s) +host_op_rate 10836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 440871 # Simulator tick rate (ticks/s) +host_mem_usage 267756 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 104867 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index e5748fef4..1d5a893ff 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -132,6 +145,7 @@ number_of_TBEs=256 recycle_latency=10 request_latency=2 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 0529ad1d8..7ff042055 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:47:36 -gem5 started Jan 23 2012 04:22:12 +gem5 compiled Feb 11 2012 13:06:37 +gem5 started Feb 11 2012 13:53:34 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory +command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 8d97fa8c6..aeddd4cb4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000085 # Nu sim_ticks 85418 # Number of ticks simulated final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 13096 # Simulator instruction rate (inst/s) -host_tick_rate 434048 # Simulator tick rate (ticks/s) -host_mem_usage 217400 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 37008 # Simulator instruction rate (inst/s) +host_op_rate 36998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1226055 # Simulator tick rate (ticks/s) +host_mem_usage 219168 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 85418 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 4c0569af0..d5f1dd8ea 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -141,6 +154,7 @@ number_of_TBEs=256 recycle_latency=10 retry_threshold=1 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 476a0b599..f1a5aa8ce 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:50:16 -gem5 started Jan 23 2012 04:22:25 +gem5 compiled Feb 11 2012 13:07:02 +gem5 started Feb 11 2012 13:54:19 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token +command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index fd5600236..bd362a91b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000088 # Nu sim_ticks 87899 # Number of ticks simulated final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12702 # Simulator instruction rate (inst/s) -host_tick_rate 433208 # Simulator tick rate (ticks/s) -host_mem_usage 216416 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 58227 # Simulator instruction rate (inst/s) +host_op_rate 58203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1984496 # Simulator tick rate (ticks/s) +host_mem_usage 218264 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 87899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 209bb4d8d..82df55c27 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -147,6 +160,7 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 20c68eff3..f44aeab20 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:42:19 -gem5 started Jan 23 2012 04:21:49 +gem5 compiled Feb 11 2012 13:05:44 +gem5 started Feb 11 2012 13:52:40 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer +command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 5c579e1af..a79092ea7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000078 # Nu sim_ticks 78448 # Number of ticks simulated final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 29294 # Simulator instruction rate (inst/s) -host_tick_rate 891567 # Simulator tick rate (ticks/s) -host_mem_usage 215964 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 53931 # Simulator instruction rate (inst/s) +host_op_rate 53912 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1640583 # Simulator tick rate (ticks/s) +host_mem_usage 217556 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 78448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 2d5b16f7e..1b51d074e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -131,6 +144,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index af1c56980..acdbe4afb 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index bcff12bb9..22da3c1b5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000123 # Nu sim_ticks 123378 # Number of ticks simulated final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 44691 # Simulator instruction rate (inst/s) -host_tick_rate 2138947 # Simulator tick rate (ticks/s) -host_mem_usage 216404 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 35379 # Simulator instruction rate (inst/s) +host_op_rate 35370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1692995 # Simulator tick rate (ticks/s) +host_mem_usage 218176 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 123378 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 72df69882..bcf14766c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index 6a994fb76..ec60c2fa2 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index e3a7a00a0..4d24e98d0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000017 # Nu sim_ticks 16769000 # Number of ticks simulated final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297044 # Simulator instruction rate (inst/s) -host_tick_rate 1928782837 # Simulator tick rate (ticks/s) -host_mem_usage 206044 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 142484 # Simulator instruction rate (inst/s) +host_op_rate 142326 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 925222654 # Simulator tick rate (ticks/s) +host_mem_usage 208204 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 15680 # Number of bytes read from this memory system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 33538 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 2423 # To system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.039064 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.demand_misses 163 # number of demand (read+write) misses -system.cpu.icache.overall_misses 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits +system.cpu.icache.overall_hits::total 2423 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses +system.cpu.icache.overall_misses::total 163 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 627 # To system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 47.418751 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits +system.cpu.dcache.overall_hits::total 627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses +system.cpu.dcache.overall_misses::total 82 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1512000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1512000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 4592000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4592000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 4592000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4592000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use @@ -198,30 +229,58 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003268 # Average percentage of cache occupancy -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 80.120406 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.980800 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002445 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003268 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses +system.cpu.l2cache.overall_misses::total 245 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -230,30 +289,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 7fe95aa88..a46f1b25d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -534,7 +513,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 8159ae453..ab1ef55e9 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 07:27:01 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:35:50 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 691966ecb..010933949 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000010 # Nu sim_ticks 10000500 # Number of ticks simulated final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48981 # Simulator instruction rate (inst/s) -host_tick_rate 85336508 # Simulator tick rate (ticks/s) -host_mem_usage 252096 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -sim_insts 5739 # Number of instructions simulated +host_inst_rate 72927 # Simulator instruction rate (inst/s) +host_op_rate 90959 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158457261 # Simulator tick rate (ticks/s) +host_mem_usage 221260 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 4600 # Number of instructions simulated +sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 25856 # Number of bytes read from this memory system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -278,7 +280,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted @@ -299,7 +302,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 10622 # Number of insts commited each cycle -system.cpu.commit.count 5739 # Number of instructions committed +system.cpu.commit.committedInsts 4600 # Number of instructions committed +system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed system.cpu.commit.loads 1201 # Number of loads committed @@ -314,12 +318,13 @@ system.cpu.rob.rob_reads 21205 # Th system.cpu.rob.rob_writes 22566 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5739 # Number of Instructions Simulated -system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.485276 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.485276 # CPI: Total CPI of All Threads -system.cpu.ipc 0.286921 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.286921 # IPC: Total IPC of All Threads +system.cpu.committedInsts 4600 # Number of Instructions Simulated +system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4600 # Number of Instructions Simulated +system.cpu.cpi 4.348261 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.348261 # CPI: Total CPI of All Threads +system.cpu.ipc 0.229977 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.229977 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 37816 # number of integer regfile reads system.cpu.int_regfile_writes 7658 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads @@ -331,26 +336,39 @@ system.cpu.icache.total_refs 1559 # To system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.249158 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 148.855822 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.072684 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1559 # number of ReadReq hits -system.cpu.icache.demand_hits 1559 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1559 # number of overall hits -system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses -system.cpu.icache.demand_misses 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1919 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1919 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1919 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.187598 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.187598 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.187598 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 148.855822 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072684 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072684 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1559 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1559 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1559 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1559 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1559 # number of overall hits +system.cpu.icache.overall_hits::total 1559 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12552000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12552000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12552000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12552000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12552000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12552000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1919 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1919 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1919 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1919 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1919 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1919 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187598 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187598 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187598 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34866.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,27 +377,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.154768 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.154768 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.154768 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9945000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33484.848485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.085552 # Cycle average of tags in use @@ -387,40 +408,63 @@ system.cpu.dcache.total_refs 2331 # To system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.085552 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021749 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 2311 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2311 # number of overall hits -system.cpu.dcache.ReadReq_misses 169 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 473 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5350500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10725000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 16075500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16075500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2784 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2784 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.090326 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.169899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.169899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31659.763314 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35279.605263 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33986.257928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33986.257928 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 89.085552 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021749 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021749 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1702 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1702 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2311 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2311 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2311 # number of overall hits +system.cpu.dcache.overall_hits::total 2311 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 473 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 473 # number of overall misses +system.cpu.dcache.overall_misses::total 473 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5350500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5350500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10725000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10725000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16075500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16075500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16075500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16075500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2784 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2784 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2784 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2784 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090326 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.169899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.169899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31659.763314 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35279.605263 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -429,33 +473,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 112 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 154 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 154 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3230000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4735000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4735000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.055316 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.055316 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28839.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 154 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 154 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 154 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3230000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3230000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4735000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4735000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4735000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4735000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28839.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.110462 # Cycle average of tags in use @@ -463,31 +514,67 @@ system.cpu.l2cache.total_refs 42 # To system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 188.110462 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits -system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 42 # number of overall hits -system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12613500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1452000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14065500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14065500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.897311 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.906874 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.906874 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34369.209809 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34571.428571 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34389.975550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34389.975550 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 140.315748 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 47.794714 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004282 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001459 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 24 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 24 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 24 # number of overall hits +system.cpu.l2cache.overall_hits::total 42 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 88 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 130 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 409 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 130 # number of overall misses +system.cpu.l2cache.overall_misses::total 409 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9586000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3027500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12613500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1452000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1452000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9586000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4479500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14065500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9586000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4479500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14065500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 112 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 409 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 154 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 154 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.939394 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.785714 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.939394 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.844156 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.939394 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.844156 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.422939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.409091 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.428571 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,31 +583,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11304000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1319000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885086 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.895787 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.895787 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31226.519337 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31404.761905 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 362 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8692000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11304000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8692000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3931000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12623000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8692000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3931000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12623000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.741071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31154.121864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31404.761905 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 1ee45ad85..a2c85dbcd 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 13e73ddc3..ef47c4ce8 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 04:24:50 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:36:01 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 8e7751fe7..1e73e7e3d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25921 # Simulator instruction rate (inst/s) -host_tick_rate 12986430 # Simulator tick rate (ticks/s) -host_mem_usage 208728 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host -sim_insts 5739 # Number of instructions simulated +host_inst_rate 866385 # Simulator instruction rate (inst/s) +host_op_rate 1077395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 538148768 # Simulator tick rate (ticks/s) +host_mem_usage 211284 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 4600 # Number of instructions simulated +sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22944 # Number of bytes read from this memory system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory system.physmem.bytes_written 3648 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.numCycles 5752 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5739 # Number of instructions executed +system.cpu.committedInsts 4600 # Number of instructions committed +system.cpu.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index d881a3977..1d87891a2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 25474862b..378a682d4 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 04:24:50 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:36:11 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 9108e20ee..a93efeca8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000026 # Nu sim_ticks 26361000 # Number of ticks simulated final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20483 # Simulator instruction rate (inst/s) -host_tick_rate 95024596 # Simulator tick rate (ticks/s) -host_mem_usage 217432 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -sim_insts 5682 # Number of instructions simulated +host_inst_rate 456104 # Simulator instruction rate (inst/s) +host_op_rate 565540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2619225899 # Simulator tick rate (ticks/s) +host_mem_usage 220184 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 4574 # Number of instructions simulated +sim_ops 5682 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22400 # Number of bytes read from this memory system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.numCycles 52722 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5682 # Number of instructions executed +system.cpu.committedInsts 4574 # Number of instructions committed +system.cpu.committedOps 5682 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured @@ -88,26 +91,39 @@ system.cpu.icache.total_refs 4373 # To system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 114.525744 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.055921 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 4373 # number of ReadReq hits -system.cpu.icache.demand_hits 4373 # number of demand (read+write) hits -system.cpu.icache.overall_hits 4373 # number of overall hits -system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses -system.cpu.icache.demand_misses 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4614 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4614 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.052232 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.052232 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.052232 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4373 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4373 # number of overall hits +system.cpu.icache.overall_hits::total 4373 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses +system.cpu.icache.overall_misses::total 241 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4614 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4614 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.052232 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.052232 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use @@ -143,36 +157,57 @@ system.cpu.dcache.total_refs 1941 # To system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 82.937979 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020249 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 1919 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1919 # number of overall hits -system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses -system.cpu.dcache.demand_misses 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4816000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7224000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7224000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2060 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2060 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.085440 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.068447 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.068447 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 51234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 51234.042553 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 82.937979 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020249 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020249 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1919 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1919 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1919 # number of overall hits +system.cpu.dcache.overall_hits::total 1919 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses +system.cpu.dcache.overall_misses::total 141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4816000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4816000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2408000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2408000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7224000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2060 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,30 +216,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.068447 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use @@ -212,31 +247,67 @@ system.cpu.l2cache.total_refs 32 # To system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 32 # number of ReadReq hits -system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 32 # number of overall hits -system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.905605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 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of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,30 +316,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.916230 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index 1ccb30b9c..600677fb9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 677598e87..9f59be0ce 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:29 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:30 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 78172e7b6..6cd55fbff 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000020 # Nu sim_ticks 19785000 # Number of ticks simulated final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71616 # Simulator instruction rate (inst/s) -host_tick_rate 243111037 # Simulator tick rate (ticks/s) -host_mem_usage 208328 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 101976 # Simulator instruction rate (inst/s) +host_op_rate 101944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 346042004 # Simulator tick rate (ticks/s) +host_mem_usage 210372 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29120 # Number of bytes read from this memory system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,9 +56,10 @@ system.cpu.comNops 657 # Nu system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 5827 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads @@ -110,26 +113,39 @@ system.cpu.icache.total_refs 443 # To system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 148.138598 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.072333 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 443 # number of ReadReq hits -system.cpu.icache.demand_hits 443 # number of demand (read+write) hits -system.cpu.icache.overall_hits 443 # number of overall hits -system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses -system.cpu.icache.demand_misses 341 # number of demand (read+write) misses -system.cpu.icache.overall_misses 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19027500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19027500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 784 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 784 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.434949 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.434949 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.434949 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55799.120235 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55799.120235 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55799.120235 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 148.138598 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072333 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072333 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 443 # number of overall hits +system.cpu.icache.overall_hits::total 443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 341 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 341 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 341 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 341 # number of overall misses +system.cpu.icache.overall_misses::total 341 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19027500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19027500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19027500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19027500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19027500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19027500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 784 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 784 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 784 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 784 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 784 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 784 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.434949 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.434949 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.434949 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -138,27 +154,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16952500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.406888 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.406888 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.406888 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16952500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16952500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16952500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16952500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16952500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16952500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use @@ -166,32 +185,49 @@ system.cpu.dcache.total_refs 1838 # To system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.732679 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021907 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits -system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1838 # number of overall hits -system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 162 # number of WriteReq misses -system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 251 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 8912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13984500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.076460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.175135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55715.139442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55715.139442 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 89.732679 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 763 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1838 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1838 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1838 # number of overall hits +system.cpu.dcache.overall_hits::total 1838 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 162 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 162 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses +system.cpu.dcache.overall_misses::total 251 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8912000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8912000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13984500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13984500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076460 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,32 +236,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 111 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7448500 # 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number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 111 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 111 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use @@ -233,31 +275,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12717500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3529500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16247000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2058000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2058000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12717500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12717500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 508c3cad4..00305a8e7 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index eb1e6f70f..afa267678 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:41 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:39 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index e49d82dd9..9ff42644b 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000012 # Nu sim_ticks 12272500 # Number of ticks simulated final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65845 # Simulator instruction rate (inst/s) -host_tick_rate 156294886 # Simulator tick rate (ticks/s) -host_mem_usage 208908 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 97350 # Simulator instruction rate (inst/s) +host_op_rate 97317 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 230983195 # Simulator tick rate (ticks/s) +host_mem_usage 211060 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated +sim_ops 5169 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30400 # Number of bytes read from this memory system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -255,6 +257,7 @@ system.cpu.iew.wb_rate 0.289986 # in system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted @@ -275,7 +278,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle -system.cpu.commit.count 5826 # Number of instructions committed +system.cpu.commit.committedInsts 5826 # Number of instructions committed +system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2089 # Number of memory references committed system.cpu.commit.loads 1164 # Number of loads committed @@ -291,6 +295,7 @@ system.cpu.rob.rob_writes 20794 # Th system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated +system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads @@ -307,26 +312,39 @@ system.cpu.icache.total_refs 1363 # To system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 161.224498 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1363 # number of ReadReq hits -system.cpu.icache.demand_hits 1363 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1363 # number of overall hits -system.cpu.icache.ReadReq_misses 418 # number of ReadReq misses -system.cpu.icache.demand_misses 418 # number of demand (read+write) misses -system.cpu.icache.overall_misses 418 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15148000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15148000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1781 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1781 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.234700 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.234700 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.234700 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36239.234450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36239.234450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36239.234450 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits +system.cpu.icache.overall_hits::total 1363 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses +system.cpu.icache.overall_misses::total 418 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15148000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15148000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15148000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15148000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15148000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1781 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1781 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1781 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1781 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1781 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1781 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234700 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234700 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234700 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,27 +353,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 82 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.188658 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.188658 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.188658 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 336 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 336 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 336 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11784000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11784000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11784000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11784000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11784000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11784000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use @@ -363,32 +384,49 @@ system.cpu.dcache.total_refs 2380 # To system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.121984 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits -system.cpu.dcache.demand_hits 2380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2380 # number of overall hits -system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses -system.cpu.dcache.demand_misses 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11508000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16275500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.068734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.167832 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167832 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35845.864662 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33164.265130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33907.291667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33907.291667 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 92.121984 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022491 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022491 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1802 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2380 # number of overall hits +system.cpu.dcache.overall_hits::total 2380 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses +system.cpu.dcache.overall_misses::total 480 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4767500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4767500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11508000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11508000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16275500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16275500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16275500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16275500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068734 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.167832 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.167832 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -397,32 +435,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 338 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.047028 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.049650 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.049650 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 338 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 338 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 338 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 338 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1836000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1836000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5108000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5108000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5108000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5108000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047028 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use @@ -430,31 +474,64 @@ system.cpu.l2cache.total_refs 3 # To system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.521956 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 424 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # 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number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13198000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14796500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14796500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index 8bad8df13..9563d85bf 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=MipsTLB size=64 +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index 4b9270f18..7716b33a4 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:47 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:41 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 397c3f1f6..9ae16c4c6 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 2913500 # Number of ticks simulated final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231601 # Simulator instruction rate (inst/s) -host_tick_rate 115720913 # Simulator tick rate (ticks/s) -host_mem_usage 199128 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 1078442 # Simulator instruction rate (inst/s) +host_op_rate 1075012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 535874927 # Simulator tick rate (ticks/s) +host_mem_usage 200784 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27687 # Number of bytes read from this memory system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory system.physmem.bytes_written 3658 # Number of bytes written to this memory @@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 5828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.committedInsts 5827 # Number of instructions committed +system.cpu.committedOps 5827 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses system.cpu.num_func_calls 194 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index e5b4b16c8..da3c93787 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=MipsTLB size=64 +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -131,6 +144,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index f6eaf03f7..ac3ff100c 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:56 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:52 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 65d0aed82..8087912dc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000293 # Nu sim_ticks 292960 # Number of ticks simulated final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 55801 # Simulator instruction rate (inst/s) -host_tick_rate 2804966 # Simulator tick rate (ticks/s) -host_mem_usage 220172 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 71598 # Simulator instruction rate (inst/s) +host_op_rate 71583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3598224 # Simulator tick rate (ticks/s) +host_mem_usage 221836 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27687 # Number of bytes read from this memory system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory system.physmem.bytes_written 3658 # Number of bytes written to this memory @@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 292960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.committedInsts 5827 # Number of instructions committed +system.cpu.committedOps 5827 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses system.cpu.num_func_calls 194 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index 36444e22d..3cd70d03a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 7525d1ad5..29b03eaff 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:52 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:50 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 566ce19a4..5a0520753 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000032 # Nu sim_ticks 32088000 # Number of ticks simulated final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263412 # Simulator instruction rate (inst/s) -host_tick_rate 1449372115 # Simulator tick rate (ticks/s) -host_mem_usage 207940 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 603210 # Simulator instruction rate (inst/s) +host_op_rate 602100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3309896144 # Simulator tick rate (ticks/s) +host_mem_usage 209992 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28096 # Number of bytes read from this memory system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -40,7 +42,8 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 64176 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.committedInsts 5827 # Number of instructions committed +system.cpu.committedOps 5827 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses system.cpu.num_func_calls 194 # number of times a function call or return occured @@ -64,26 +67,39 @@ system.cpu.icache.total_refs 5526 # To system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits -system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits -system.cpu.icache.overall_hits 5526 # number of overall hits -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses -system.cpu.icache.overall_misses 303 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits +system.cpu.icache.overall_hits::total 5526 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses +system.cpu.icache.overall_misses::total 303 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -92,26 +108,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use @@ -119,32 +133,49 @@ system.cpu.dcache.total_refs 1951 # To system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1951 # number of overall hits -system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses -system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021352 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021352 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits +system.cpu.dcache.overall_hits::total 1951 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.dcache.overall_misses::total 138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -153,30 +184,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # 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number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 439 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 54.207742 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001654 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005739 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 301 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,30 +281,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index fb36c719f..eed88a81d 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -53,6 +60,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -70,6 +78,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -81,6 +90,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -89,6 +99,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -126,20 +137,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -425,20 +429,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -446,6 +443,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=PowerInterrupts + [system.cpu.itb] type=PowerTLB size=64 @@ -461,20 +461,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 8cb241542..8e7d01159 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:58:39 -gem5 started Jan 23 2012 04:24:00 +gem5 compiled Feb 11 2012 13:07:55 +gem5 started Feb 11 2012 13:55:01 gem5 executing on zizzer -command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing +command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 5a2ad1a0a..7c789f568 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000011 # Nu sim_ticks 10910500 # Number of ticks simulated final_tick 10910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80565 # Simulator instruction rate (inst/s) -host_tick_rate 151515044 # Simulator tick rate (ticks/s) -host_mem_usage 205800 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 114395 # Simulator instruction rate (inst/s) +host_op_rate 114354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215042277 # Simulator tick rate (ticks/s) +host_mem_usage 207892 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated +sim_ops 5800 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28608 # Number of bytes read from this memory system.physmem.bytes_inst_read 22016 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -255,6 +257,7 @@ system.cpu.iew.wb_rate 0.361058 # in system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted @@ -275,7 +278,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle -system.cpu.commit.count 5800 # Number of instructions committed +system.cpu.commit.committedInsts 5800 # Number of instructions committed +system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2008 # Number of memory references committed system.cpu.commit.loads 962 # Number of loads committed @@ -291,6 +295,7 @@ system.cpu.rob.rob_writes 20673 # Th system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated +system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads @@ -306,26 +311,39 @@ system.cpu.icache.total_refs 1291 # To system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 169.539680 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.082783 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1291 # number of ReadReq hits -system.cpu.icache.demand_hits 1291 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1291 # number of overall hits -system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses -system.cpu.icache.demand_misses 420 # number of demand (read+write) misses -system.cpu.icache.overall_misses 420 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15114500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15114500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15114500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.245470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.245470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.245470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35986.904762 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35986.904762 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35986.904762 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 169.539680 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.082783 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.082783 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1291 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1291 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1291 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1291 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1291 # number of overall hits +system.cpu.icache.overall_hits::total 1291 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 420 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 420 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 420 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 420 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 420 # number of overall misses +system.cpu.icache.overall_misses::total 420 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15114500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15114500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15114500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15114500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15114500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15114500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1711 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1711 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1711 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1711 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1711 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1711 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.245470 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.245470 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.245470 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35986.904762 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -334,27 +352,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 69 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12207500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12207500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12207500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.205143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.205143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.205143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12207500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12207500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12207500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12207500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12207500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12207500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34779.202279 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 66.296919 # Cycle average of tags in use @@ -362,32 +383,49 @@ system.cpu.dcache.total_refs 2156 # To system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 20.533333 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 66.296919 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.016186 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 728 # number of WriteReq hits -system.cpu.dcache.demand_hits 2156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2156 # number of overall hits -system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 318 # number of WriteReq misses -system.cpu.dcache.demand_misses 406 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2947000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10802500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13749500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13749500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2562 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.058047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.304015 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.158470 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.158470 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33488.636364 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33970.125786 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33865.763547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33865.763547 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 66.296919 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.016186 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.016186 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1428 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1428 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 728 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 728 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits +system.cpu.dcache.overall_hits::total 2156 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 88 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 88 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 406 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 406 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 406 # number of overall misses +system.cpu.dcache.overall_misses::total 406 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2947000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2947000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10802500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10802500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13749500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13749500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13749500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2562 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2562 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304015 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.158470 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158470 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33488.636364 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33970.125786 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,32 +434,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 57 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 105 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 105 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1751000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3714500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3714500 # 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number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 31 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 270 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 105 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3714500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3714500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.040984 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.040984 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34447.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36479.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35376.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35376.190476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 200.613051 # Cycle average of tags in use @@ -429,31 +473,67 @@ system.cpu.l2cache.total_refs 9 # To system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 200.613051 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006122 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 9 # number of ReadReq hits -system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 9 # number of overall hits -system.cpu.l2cache.ReadReq_misses 399 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 48 # 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miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.980263 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34968.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34435.123043 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34435.123043 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 168.132824 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.480228 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005131 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000991 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006122 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 2 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11818500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3574000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15392500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 57 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 105 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 105 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.980057 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964912 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980057 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980057 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.104651 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34463.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34968.750000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,30 +542,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 399 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 447 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12434000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977941 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.980263 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.980263 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31162.907268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 447 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10708500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1725500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12434000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10708500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10708500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31129.360465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31372.727273 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31791.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index f4325cdae..252e46831 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,17 +30,19 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload UnifiedTLB=true checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -41,6 +50,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -55,6 +65,9 @@ icache_port=system.membus.port[2] type=PowerTLB size=64 +[system.cpu.interrupts] +type=PowerInterrupts + [system.cpu.itb] type=PowerTLB size=64 diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index ef2f9ace6..2b3bb9fb6 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:58:39 -gem5 started Jan 23 2012 04:24:03 +gem5 compiled Feb 11 2012 13:07:55 +gem5 started Feb 11 2012 13:55:02 gem5 executing on zizzer -command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic +command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 5070ee2a1..5d83b2bac 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 2900000 # Number of ticks simulated final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 305071 # Simulator instruction rate (inst/s) -host_tick_rate 152367478 # Simulator tick rate (ticks/s) -host_mem_usage 196296 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 430782 # Simulator instruction rate (inst/s) +host_op_rate 430227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 214814147 # Simulator tick rate (ticks/s) +host_mem_usage 197864 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5801 # Number of instructions simulated +sim_ops 5801 # Number of ops (including micro ops) simulated system.physmem.bytes_read 26925 # Number of bytes read from this memory system.physmem.bytes_inst_read 23204 # Number of instructions bytes read from this memory system.physmem.bytes_written 4209 # Number of bytes written to this memory @@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls 9 # Nu system.cpu.numCycles 5801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5801 # Number of instructions executed +system.cpu.committedInsts 5801 # Number of instructions committed +system.cpu.committedOps 5801 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses system.cpu.num_func_calls 200 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 32a7f4ad9..eed996339 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 024efc4d5..13c85267e 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:09 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:12 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 18201500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 1ce5039d0..99d0ed042 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000018 # Nu sim_ticks 18201500 # Number of ticks simulated final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29731 # Simulator instruction rate (inst/s) -host_tick_rate 101330259 # Simulator tick rate (ticks/s) -host_mem_usage 213072 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 71915 # Simulator instruction rate (inst/s) +host_op_rate 71898 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 245008016 # Simulator tick rate (ticks/s) +host_mem_usage 211144 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated +sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27072 # Number of bytes read from this memory system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -36,9 +38,10 @@ system.cpu.comNops 173 # Nu system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed system.cpu.comInts 2537 # Number of Integer instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 5340 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads @@ -92,26 +95,39 @@ system.cpu.icache.total_refs 791 # To system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 136.669321 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.066733 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits -system.cpu.icache.demand_hits 791 # number of demand (read+write) hits -system.cpu.icache.overall_hits 791 # number of overall hits -system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses -system.cpu.icache.demand_misses 347 # number of demand (read+write) misses -system.cpu.icache.overall_misses 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19110500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19110500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19110500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55073.487032 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55073.487032 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55073.487032 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 136.669321 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066733 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066733 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 791 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 791 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 791 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 791 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 791 # number of overall hits +system.cpu.icache.overall_hits::total 791 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses +system.cpu.icache.overall_misses::total 347 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19110500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19110500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19110500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19110500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19110500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19110500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1138 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1138 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1138 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1138 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.304921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.304921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.304921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55073.487032 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -120,27 +136,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15470000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15470000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15470000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15470000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15470000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15470000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15470000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15470000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15470000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53161.512027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use @@ -148,32 +167,49 @@ system.cpu.dcache.total_refs 1049 # To system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 82.859932 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020229 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 392 # number of WriteReq hits -system.cpu.dcache.demand_hits 1049 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1049 # number of overall hits -system.cpu.dcache.ReadReq_misses 59 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 281 # number of WriteReq misses -system.cpu.dcache.demand_misses 340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3290500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 15457500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18748000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18748000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.082402 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.417533 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.244780 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.244780 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 55771.186441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55008.896797 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55141.176471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55141.176471 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 82.859932 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020229 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020229 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 392 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1049 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1049 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1049 # number of overall hits +system.cpu.dcache.overall_hits::total 1049 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 59 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 59 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 281 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 281 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 340 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses +system.cpu.dcache.overall_misses::total 340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3290500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3290500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15457500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15457500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18748000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18748000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18748000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18748000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55771.186441 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55008.896797 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,32 +218,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 200 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 205 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2865500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4327000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7192500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7192500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53064.814815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.753086 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 200 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 200 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 205 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 205 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 205 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 205 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2865500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2865500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7192500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7192500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7192500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7192500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53064.814815 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53419.753086 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use @@ -215,31 +257,67 @@ system.cpu.l2cache.total_refs 3 # To system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 162.297266 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004953 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 342 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 17918500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 22149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 22149000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 345 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 426 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 426 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.991304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.992958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52393.274854 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52361.702128 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52361.702128 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 136.185515 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.111751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 3 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.l2cache.overall_misses::total 423 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15132500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17918500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15132500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7016500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15132500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7016500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22149000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.591696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -248,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 342 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13747000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3255500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17002500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17002500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.991304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.992958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40195.906433 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40191.358025 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2143500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13747000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3255500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3255500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11603500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5399000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17002500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11603500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index 8aa4dc707..328fede16 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 9cbff76e8..51b7334cc 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:11 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:13 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 57eaeacb0..12998e98f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 2701000 # Number of ticks simulated final_tick 2701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117056 # Simulator instruction rate (inst/s) -host_tick_rate 59184907 # Simulator tick rate (ticks/s) -host_mem_usage 203964 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 963329 # Simulator instruction rate (inst/s) +host_op_rate 960313 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 484321069 # Simulator tick rate (ticks/s) +host_mem_usage 201636 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated +sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 26135 # Number of bytes read from this memory system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory system.physmem.bytes_written 5065 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 5403 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.committedInsts 5340 # Number of instructions committed +system.cpu.committedOps 5340 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 146 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index e13b78d74..bca11e4c0 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -131,6 +144,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index 8b55b99bf..f70d252d3 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:20 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:24 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 253364 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 5fbe4680b..a13bd4161 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000253 # Nu sim_ticks 253364 # Number of ticks simulated final_tick 253364 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 57666 # Simulator instruction rate (inst/s) -host_tick_rate 2735530 # Simulator tick rate (ticks/s) -host_mem_usage 224736 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 70723 # Simulator instruction rate (inst/s) +host_op_rate 70707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3354080 # Simulator tick rate (ticks/s) +host_mem_usage 222404 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated +sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 26135 # Number of bytes read from this memory system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory system.physmem.bytes_written 5065 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 253364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.committedInsts 5340 # Number of instructions committed +system.cpu.committedOps 5340 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 146 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 31f964ca0..a61827466 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index a3d57b80d..5f1c3c546 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:14 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:23 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 28206000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 0e1d1294b..e8bbbf4c9 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000028 # Nu sim_ticks 28206000 # Number of ticks simulated final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 103151 # Simulator instruction rate (inst/s) -host_tick_rate 544654705 # Simulator tick rate (ticks/s) -host_mem_usage 212680 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 534426 # Simulator instruction rate (inst/s) +host_op_rate 533460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2812998715 # Simulator tick rate (ticks/s) +host_mem_usage 210748 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated +sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 24896 # Number of bytes read from this memory system.physmem.bytes_inst_read 16320 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 56412 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.committedInsts 5340 # Number of instructions committed +system.cpu.committedOps 5340 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 146 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 5127 # To system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 116.975932 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.057117 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits -system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits -system.cpu.icache.overall_hits 5127 # number of overall hits -system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses -system.cpu.icache.demand_misses 257 # number of demand (read+write) misses -system.cpu.icache.overall_misses 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5127 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5127 # number of overall hits +system.cpu.icache.overall_hits::total 5127 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses +system.cpu.icache.overall_misses::total 257 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14308000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14308000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14308000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5384 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5384 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use @@ -101,32 +115,49 @@ system.cpu.dcache.total_refs 1254 # To system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 82.065697 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020036 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 592 # number of WriteReq hits -system.cpu.dcache.demand_hits 1254 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1254 # number of overall hits -system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses -system.cpu.dcache.demand_misses 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4536000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7518000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7518000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.097192 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.097192 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55688.888889 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020036 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020036 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1254 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1254 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1254 # number of overall hits +system.cpu.dcache.overall_hits::total 1254 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses +system.cpu.dcache.overall_misses::total 135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2982000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4536000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4536000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7518000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7518000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7518000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7518000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075419 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097192 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097192 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,30 +166,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use @@ -166,31 +197,67 @@ system.cpu.l2cache.total_refs 3 # To system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 142.102892 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004337 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 25.652557 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003554 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 3 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.l2cache.overall_misses::total 389 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,30 +266,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 8f8ece24e..7b5ea1d59 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -89,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -126,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -149,7 +152,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.fuPool] type=FUPool @@ -425,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -446,9 +449,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -461,25 +480,18 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -490,7 +502,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -503,7 +515,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -522,7 +534,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index b49f2b572..ac1cd3610 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 28 2012 12:11:40 -gem5 started Jan 28 2012 12:11:57 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:05 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 8477728c8..658a056fb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000012 # Nu sim_ticks 11989500 # Number of ticks simulated final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1330 # Simulator instruction rate (inst/s) -host_tick_rate 1625690 # Simulator tick rate (ticks/s) -host_mem_usage 239860 # Number of bytes of host memory used -host_seconds 7.38 # Real time elapsed on the host -sim_insts 9809 # Number of instructions simulated +host_inst_rate 61798 # Simulator instruction rate (inst/s) +host_op_rate 111900 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 136747555 # Simulator tick rate (ticks/s) +host_mem_usage 218292 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 5416 # Number of instructions simulated +sim_ops 9809 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28288 # Number of bytes read from this memory system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -235,7 +237,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions +system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted @@ -256,7 +259,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle -system.cpu.commit.count 9809 # Number of instructions committed +system.cpu.commit.committedInsts 5416 # Number of instructions committed +system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1990 # Number of memory references committed system.cpu.commit.loads 1056 # Number of loads committed @@ -271,12 +275,13 @@ system.cpu.rob.rob_reads 34653 # Th system.cpu.rob.rob_writes 42403 # The number of ROB writes system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 9809 # Number of Instructions Simulated -system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.444694 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.444694 # CPI: Total CPI of All Threads -system.cpu.ipc 0.409049 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.409049 # IPC: Total IPC of All Threads +system.cpu.committedInsts 5416 # Number of Instructions Simulated +system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 5416 # Number of Instructions Simulated +system.cpu.cpi 4.427622 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.427622 # CPI: Total CPI of All Threads +system.cpu.ipc 0.225855 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.225855 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 23430 # number of integer regfile reads system.cpu.int_regfile_writes 14518 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads @@ -287,26 +292,39 @@ system.cpu.icache.total_refs 1498 # To system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 140.870525 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.068784 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1498 # number of ReadReq hits -system.cpu.icache.demand_hits 1498 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1498 # number of overall hits -system.cpu.icache.ReadReq_misses 368 # number of ReadReq misses -system.cpu.icache.demand_misses 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13394000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13394000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1866 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.197213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.197213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.197213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36396.739130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36396.739130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36396.739130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 140.870525 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.068784 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.068784 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1498 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1498 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1498 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1498 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1498 # number of overall hits +system.cpu.icache.overall_hits::total 1498 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13394000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13394000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13394000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13394000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13394000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13394000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1866 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1866 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197213 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.197213 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.197213 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,27 +333,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10471500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.159700 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.159700 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.159700 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35139.261745 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35139.261745 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35139.261745 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10471500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10471500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 83.526549 # Cycle average of tags in use @@ -343,32 +364,49 @@ system.cpu.dcache.total_refs 2275 # To system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.689655 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 83.526549 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1417 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 858 # number of WriteReq hits -system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2275 # number of overall hits -system.cpu.dcache.ReadReq_misses 111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 76 # number of WriteReq misses -system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 187 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3859500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2916500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 6776000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2462 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2462 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.072644 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.075955 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.075955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 34770.270270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 38375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 36235.294118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 36235.294118 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 83.526549 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020392 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020392 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1417 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1417 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits +system.cpu.dcache.overall_hits::total 2275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 187 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 187 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 187 # number of overall misses +system.cpu.dcache.overall_misses::total 187 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3859500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3859500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2916500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2916500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6776000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6776000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6776000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6776000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2462 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2462 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2462 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2462 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072644 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075955 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075955 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34770.270270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38375 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,31 +415,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 41 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 70 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.045812 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.059301 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.059301 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35185.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35375 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35284.246575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35284.246575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 41 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 41 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2463000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2463000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2688500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2688500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5151500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5151500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045812 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35185.714286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35375 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 173.809724 # Cycle average of tags in use @@ -409,31 +452,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005479 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 173.809724 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005304 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 366 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 76 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 442 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12541000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2603000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 15144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 15144000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 368 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 76 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995495 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995495 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34265.027322 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34250 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34262.443439 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34262.443439 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 140.468506 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.341218 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004287 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001017 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005304 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 296 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 70 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4986000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15144000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10158000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4986000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15144000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 368 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 444 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 444 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993289 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993289 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993289 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.567568 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34042.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,30 +518,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 442 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11369000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2368500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13737500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995495 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995495 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31062.841530 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.473684 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 442 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9202000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2167000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11369000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2368500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2368500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9202000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4535500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9202000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4535500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13737500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index e5a1ce348..8e464f4fc 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index de652c174..51c6cbf48 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 04:24:38 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:16 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index e2f539833..d15c91451 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000006 # Nu sim_ticks 5651000 # Number of ticks simulated final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225004 # Simulator instruction rate (inst/s) -host_tick_rate 129531520 # Simulator tick rate (ticks/s) -host_mem_usage 202604 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 9810 # Number of instructions simulated +host_inst_rate 364793 # Simulator instruction rate (inst/s) +host_op_rate 659825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379660541 # Simulator tick rate (ticks/s) +host_mem_usage 207748 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +sim_insts 5417 # Number of instructions simulated +sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 62348 # Number of bytes read from this memory system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory system.physmem.bytes_written 7110 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 11303 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 9810 # Number of instructions executed +system.cpu.committedInsts 5417 # Number of instructions committed +system.cpu.committedOps 9810 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 3ef5774b9..95be41a11 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -49,11 +59,34 @@ icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.port[3] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_port=system.l1_cntrl0.sequencer.port[5] +pio=system.l1_cntrl0.sequencer.port[4] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.port[2] [system.cpu.tracer] type=ExeTracer @@ -131,6 +164,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 @@ -157,7 +191,7 @@ using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port +port=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 9c1cf6357..f8a22f9ca 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 04:24:43 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:37 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 49089d227..31a5db86e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000276 # Nu sim_ticks 276484 # Number of ticks simulated final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 88128 # Simulator instruction rate (inst/s) -host_tick_rate 2483404 # Simulator tick rate (ticks/s) -host_mem_usage 223444 # Number of bytes of host memory used +host_inst_rate 47191 # Simulator instruction rate (inst/s) +host_op_rate 85448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2407911 # Simulator tick rate (ticks/s) +host_mem_usage 228676 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host -sim_insts 9810 # Number of instructions simulated +sim_insts 5417 # Number of instructions simulated +sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 62348 # Number of bytes read from this memory system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory system.physmem.bytes_written 7110 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 276484 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 9810 # Number of instructions executed +system.cpu.committedInsts 5417 # Number of instructions committed +system.cpu.committedOps 9810 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 36b722b34..7bd202ff4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 074c5468c..89203c6bc 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 04:24:38 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:26 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index dcf7af574..c2e4355d3 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000029 # Nu sim_ticks 28768000 # Number of ticks simulated final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320748 # Simulator instruction rate (inst/s) -host_tick_rate 940055576 # Simulator tick rate (ticks/s) -host_mem_usage 211332 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 9810 # Number of instructions simulated +host_inst_rate 265683 # Simulator instruction rate (inst/s) +host_op_rate 480724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1408532008 # Simulator tick rate (ticks/s) +host_mem_usage 216996 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +sim_insts 5417 # Number of instructions simulated +sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 23104 # Number of bytes read from this memory system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 57536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 9810 # Number of instructions executed +system.cpu.committedInsts 5417 # Number of instructions committed +system.cpu.committedOps 9810 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 6683 # To system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits -system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits -system.cpu.icache.overall_hits 6683 # number of overall hits -system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses -system.cpu.icache.demand_misses 228 # number of demand (read+write) misses -system.cpu.icache.overall_misses 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 105.363985 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.051447 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.051447 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6683 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6683 # number of overall hits +system.cpu.icache.overall_hits::total 6683 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses +system.cpu.icache.overall_misses::total 228 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6911 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use @@ -101,32 +115,49 @@ system.cpu.dcache.total_refs 1856 # To system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits -system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1856 # number of overall hits -system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses -system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 80.668870 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1856 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1856 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1856 # number of overall hits +system.cpu.dcache.overall_hits::total 1856 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.dcache.overall_misses::total 134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1056 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1056 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1990 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,30 +166,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use @@ -166,31 +197,64 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 361 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 105.370729 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.438613 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003216 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000868 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.l2cache.overall_misses::total 361 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,30 +263,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5ef0030d0..14cc5821d 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1 +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload0 workload1 BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=2 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index ab4ed6a09..4edc89b33 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 6ec84dd27..292756fa3 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000013 # Nu sim_ticks 13202000 # Number of ticks simulated final_tick 13202000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76140 # Simulator instruction rate (inst/s) -host_tick_rate 78688554 # Simulator tick rate (ticks/s) -host_mem_usage 208616 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 91406 # Simulator instruction rate (inst/s) +host_op_rate 91394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94452628 # Simulator tick rate (ticks/s) +host_mem_usage 210624 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated +sim_ops 12773 # Number of ops (including micro ops) simulated system.physmem.bytes_read 62144 # Number of bytes read from this memory system.physmem.bytes_inst_read 39936 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -385,6 +387,7 @@ system.cpu.iew.wb_penalized_rate::0 0 # fr system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions +system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted @@ -405,9 +408,12 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle -system.cpu.commit.count::0 6403 # Number of instructions committed -system.cpu.commit.count::1 6404 # Number of instructions committed -system.cpu.commit.count::total 12807 # Number of instructions committed +system.cpu.commit.committedInsts::0 6403 # Number of instructions committed +system.cpu.commit.committedInsts::1 6404 # Number of instructions committed +system.cpu.commit.committedInsts::total 12807 # Number of instructions committed +system.cpu.commit.committedOps::0 6403 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::1 6404 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::total 12807 # Number of ops (including micro ops) committed system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed @@ -442,6 +448,8 @@ system.cpu.timesIdled 233 # Nu system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6386 # Number of Instructions Simulated system.cpu.committedInsts::1 6387 # Number of Instructions Simulated +system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction @@ -463,36 +471,39 @@ system.cpu.icache.total_refs 3236 # To system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 314.165301 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.153401 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 3236 # number of ReadReq hits -system.cpu.icache.demand_hits 3236 # number of demand (read+write) hits -system.cpu.icache.overall_hits 3236 # number of overall hits -system.cpu.icache.ReadReq_misses 855 # number of ReadReq misses -system.cpu.icache.demand_misses 855 # number of demand (read+write) misses -system.cpu.icache.overall_misses 855 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::0 30710500 # number of ReadReq miss cycles +system.cpu.icache.occ_blocks::cpu.inst 314.165301 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.153401 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.153401 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 3236 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3236 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3236 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3236 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3236 # number of overall hits +system.cpu.icache.overall_hits::total 3236 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855 # number of overall misses +system.cpu.icache.overall_misses::total 855 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30710500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::0 30710500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30710500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::0 30710500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30710500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4091 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.208995 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.208995 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.208995 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 35918.713450 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35918.713450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 35918.713450 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35918.713450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 35918.713450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35918.713450 # average overall miss latency +system.cpu.icache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.208995 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.208995 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.208995 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35918.713450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,63 +512,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::0 0 # number of writebacks -system.cpu.icache.writebacks::1 0 # number of writebacks -system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::0 229 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements @@ -567,44 +545,49 @@ system.cpu.dcache.total_refs 4323 # To system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 12.458213 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 216.133399 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.052767 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 3303 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 1020 # number of WriteReq hits -system.cpu.dcache.demand_hits 4323 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 4323 # 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average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34662.082515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 34662.082515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34662.082515 # average overall miss latency +system.cpu.dcache.ReadReq_accesses::cpu.data 3611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 5341 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5341 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5341 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5341 # 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number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12674000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.055663 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055663 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.064969 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064969 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.064969 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064969 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36696.517413 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36287.671233 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36524.495677 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36524.495677 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36696.517413 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36287.671233 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements @@ -688,43 +637,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 435.235373 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.013282 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 825 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 971 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 971 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::0 28470000 # number of ReadReq miss cycles +system.cpu.l2cache.occ_blocks::cpu.inst 314.499531 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 120.735842 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009598 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013282 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 201 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 825 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 347 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 971 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 347 # number of overall misses +system.cpu.l2cache.overall_misses::total 971 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21475000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6995000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 28470000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::0 5066000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5066000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5066000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::0 33536000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21475000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12061000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 33536000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::0 33536000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21475000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12061000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 33536000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 827 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997582 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997945 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997945 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34509.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34509.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34698.630137 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34698.630137 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::0 34537.590113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34537.590113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::0 34537.590113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34537.590113 # average overall miss latency +system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 827 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 973 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 973 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34415.064103 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34800.995025 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34698.630137 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -733,68 +703,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::0 0 # number of writebacks -system.cpu.l2cache.writebacks::1 0 # number of writebacks -system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::0 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::0 971 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::0 971 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25887000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19514500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6372500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4614000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4614000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::0 30501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10986500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::0 30501000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10986500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997582 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997582 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::0 0.997945 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997945 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::0 0.997945 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997945 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31378.181818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31602.739726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31273.237179 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31703.980100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31602.739726 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index 7db48bf0e..a2e6b7523 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index 38fdee473..71793d455 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:21 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:34 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 7b0904682..f7efdf641 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000025 # Nu sim_ticks 25058500 # Number of ticks simulated final_tick 25058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55020 # Simulator instruction rate (inst/s) -host_tick_rate 90849063 # Simulator tick rate (ticks/s) -host_mem_usage 212976 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 93467 # Simulator instruction rate (inst/s) +host_op_rate 93457 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154309649 # Simulator tick rate (ticks/s) +host_mem_usage 211048 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated +sim_ops 15175 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27904 # Number of bytes read from this memory system.physmem.bytes_inst_read 19072 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -36,9 +38,10 @@ system.cpu.comNops 726 # Nu system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed system.cpu.comInts 7177 # Number of Integer instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 15175 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 15175 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 15175 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total) system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads @@ -92,26 +95,39 @@ system.cpu.icache.total_refs 3085 # To system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 165.645515 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.080882 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 3085 # number of ReadReq hits -system.cpu.icache.demand_hits 3085 # number of demand (read+write) hits -system.cpu.icache.overall_hits 3085 # number of overall hits -system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses -system.cpu.icache.demand_misses 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 20100000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 20100000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 20100000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 3451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 3451 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 3451 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.106056 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.106056 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.106056 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54918.032787 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54918.032787 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54918.032787 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 165.645515 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080882 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080882 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 3085 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3085 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3085 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3085 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3085 # number of overall hits +system.cpu.icache.overall_hits::total 3085 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20100000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20100000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20100000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20100000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20100000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20100000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3451 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3451 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3451 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.106056 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.106056 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.106056 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54918.032787 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -120,27 +136,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 65 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 301 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 301 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 301 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15872000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15872000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15872000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.087221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.087221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.087221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52730.897010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52730.897010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52730.897010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15872000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15872000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15872000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15872000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 97.082868 # Cycle average of tags in use @@ -148,34 +167,53 @@ system.cpu.dcache.total_refs 3316 # To system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 97.082868 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.023702 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 2168 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 1142 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.demand_hits 3310 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 3310 # number of overall hits -system.cpu.dcache.ReadReq_misses 58 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 300 # number of WriteReq misses -system.cpu.dcache.demand_misses 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3282500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 16398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19680500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19680500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.026056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.208044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.097601 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.097601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56594.827586 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54973.463687 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54973.463687 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 97.082868 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023702 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023702 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2168 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2168 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1142 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3310 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3310 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3310 # number of overall hits +system.cpu.dcache.overall_hits::total 3310 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 300 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 300 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses +system.cpu.dcache.overall_misses::total 358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3282500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16398000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16398000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19680500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19680500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19680500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19680500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56594.827586 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54660 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -184,32 +222,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 50181.818182 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 215 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 220 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 220 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2838000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4545000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7383000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53547.169811 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53470.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 215 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 215 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 220 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 220 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 220 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4545000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4545000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53547.169811 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 196.307447 # Cycle average of tags in use @@ -217,31 +261,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 196.307447 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005991 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 352 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 18310500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4442500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 22753000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 22753000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 354 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994350 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52018.465909 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52066.361556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52066.361556 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 165.036640 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.270807 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005037 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005991 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 352 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 299 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.l2cache.overall_misses::total 437 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15533000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2777500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18310500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4442500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4442500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7220000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15533000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7220000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 301 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 301 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52405.660377 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,30 +327,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 352 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14048500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3416000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17464500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17464500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994350 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39910.511364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40188.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2132500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14048500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3416000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3416000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17464500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 6652fe60b..a7b62ffbf 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 14970f00a..2cf0bff32 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:22 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:35 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3a1cfc4e9..b63661760 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000018 # Nu sim_ticks 18114000 # Number of ticks simulated final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74785 # Simulator instruction rate (inst/s) -host_tick_rate 93746300 # Simulator tick rate (ticks/s) -host_mem_usage 213808 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 120891 # Simulator instruction rate (inst/s) +host_op_rate 120873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 151511225 # Simulator tick rate (ticks/s) +host_mem_usage 211580 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated +sim_ops 14449 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30464 # Number of bytes read from this memory system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -234,6 +236,7 @@ system.cpu.iew.wb_rate 0.481079 # in system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted @@ -254,7 +257,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle -system.cpu.commit.count 15175 # Number of instructions committed +system.cpu.commit.committedInsts 15175 # Number of instructions committed +system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 3674 # Number of memory references committed system.cpu.commit.loads 2226 # Number of loads committed @@ -270,6 +274,7 @@ system.cpu.rob.rob_writes 43308 # Th system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated +system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads @@ -285,26 +290,39 @@ system.cpu.icache.total_refs 4151 # To system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 193.216525 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.094344 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 4151 # number of ReadReq hits -system.cpu.icache.demand_hits 4151 # number of demand (read+write) hits -system.cpu.icache.overall_hits 4151 # number of overall hits -system.cpu.icache.ReadReq_misses 457 # number of ReadReq misses -system.cpu.icache.demand_misses 457 # number of demand (read+write) misses -system.cpu.icache.overall_misses 457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15956000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15956000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15956000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4608 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.099175 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.099175 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.099175 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34914.660832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34914.660832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34914.660832 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 193.216525 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.094344 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.094344 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4151 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4151 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4151 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4151 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4151 # number of overall hits +system.cpu.icache.overall_hits::total 4151 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses +system.cpu.icache.overall_misses::total 457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15956000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15956000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15956000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15956000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15956000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15956000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.099175 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.099175 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.099175 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34914.660832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -313,27 +331,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 125 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 125 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.072049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.072049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.072049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 125 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 125 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 125 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 125 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 125 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11653500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11653500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11653500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35100.903614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use @@ -341,34 +362,53 @@ system.cpu.dcache.total_refs 3712 # To system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.149831 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.024939 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 2672 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.demand_hits 3706 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 3706 # number of overall hits -system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses -system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3994500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 2786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 4228 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 4228 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.040919 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.123463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.123463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35716.475096 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 102.149831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024939 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2672 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2672 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3706 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3706 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3706 # number of overall hits +system.cpu.dcache.overall_hits::total 3706 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses +system.cpu.dcache.overall_misses::total 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3994500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3994500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14649500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14649500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18644000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18644000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18644000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18644000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 4228 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4228 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4228 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4228 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040919 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.123463 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.123463 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35039.473684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35905.637255 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,32 +417,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2241500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.034532 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.034532 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2241500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2241500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2985000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2985000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5226500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5226500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5226500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5226500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35579.365079 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35963.855422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use @@ -410,31 +456,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 228.374360 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006969 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 393 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 13475000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2872000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16347000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16347000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994937 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34342.436975 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34342.436975 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 192.484909 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 35.889452 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005874 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001095 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006969 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 330 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 393 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # 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number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11308000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5039000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16347000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11308000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5039000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16347000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 332 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993976 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993976 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993976 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34266.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34396.825397 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34602.409639 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,30 +522,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 393 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12215000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2608500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14823500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14823500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10246500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1968500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12215000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2608500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2608500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10246500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14823500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10246500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14823500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31427.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 421dd8a46..b6cf50e7b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index df7964c68..15efcd3a3 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:24 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:45 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 389636d62..de9d99a5d 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000008 # Nu sim_ticks 7618500 # Number of ticks simulated final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 296178 # Simulator instruction rate (inst/s) -host_tick_rate 148615294 # Simulator tick rate (ticks/s) -host_mem_usage 203776 # Number of bytes of host memory used +host_inst_rate 298140 # Simulator instruction rate (inst/s) +host_op_rate 298037 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149578582 # Simulator tick rate (ticks/s) +host_mem_usage 201436 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated +sim_ops 15175 # Number of ops (including micro ops) simulated system.physmem.bytes_read 72223 # Number of bytes read from this memory system.physmem.bytes_inst_read 60880 # Number of instructions bytes read from this memory system.physmem.bytes_written 9042 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 18 # Nu system.cpu.numCycles 15238 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.committedInsts 15175 # Number of instructions committed +system.cpu.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 385 # number of times a function call or return occured diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index fb5a1cb83..a5f3d5088 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index d982745c0..6f63071eb 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:28 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:45 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index f52890637..f7405d428 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000042 # Nu sim_ticks 41800000 # Number of ticks simulated final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146106 # Simulator instruction rate (inst/s) -host_tick_rate 402347608 # Simulator tick rate (ticks/s) -host_mem_usage 212484 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 399467 # Simulator instruction rate (inst/s) +host_op_rate 399277 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1099343547 # Simulator tick rate (ticks/s) +host_mem_usage 210560 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated +sim_ops 15175 # Number of ops (including micro ops) simulated system.physmem.bytes_read 26624 # Number of bytes read from this memory system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 18 # Nu system.cpu.numCycles 83600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.committedInsts 15175 # Number of instructions committed +system.cpu.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 385 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 14941 # To system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 153.436702 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.074920 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits -system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits -system.cpu.icache.overall_hits 14941 # number of overall hits -system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses -system.cpu.icache.demand_misses 280 # number of demand (read+write) misses -system.cpu.icache.overall_misses 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 153.436702 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074920 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074920 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14941 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14941 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14941 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14941 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14941 # number of overall hits +system.cpu.icache.overall_hits::total 14941 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses +system.cpu.icache.overall_misses::total 280 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15596000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15596000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15596000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15221 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15221 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use @@ -101,34 +115,53 @@ system.cpu.dcache.total_refs 3536 # To system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 97.842991 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.023887 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 1357 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.demand_hits 3530 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 3530 # number of overall hits -system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 85 # number of WriteReq misses -system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4760000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.037623 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.037623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 97.842991 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023887 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023887 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2173 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2173 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3530 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3530 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3530 # number of overall hits +system.cpu.dcache.overall_hits::total 3530 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses 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+system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -137,30 +170,30 @@ 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-system.cpu.dcache.WriteReq_mshr_miss_latency 4505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use @@ -168,31 +201,64 @@ system.cpu.l2cache.total_refs 2 # To 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21632000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 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was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index eb497bb90..bb8df191a 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[2] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache itb tracer workload +children=dcache dtb fuPool icache interrupts itb tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu0.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu0.interrupts] +type=SparcInterrupts + [system.cpu0.itb] type=SparcTLB size=64 @@ -473,7 +473,7 @@ uid=100 [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache itb tracer +children=dcache dtb fuPool icache interrupts itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -502,6 +502,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb fetchToDecodeDelay=1 @@ -519,6 +520,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu1.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -530,6 +532,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -538,6 +541,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -575,20 +579,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -874,20 +871,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -895,6 +885,9 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] +[system.cpu1.interrupts] +type=SparcInterrupts + [system.cpu1.itb] type=SparcTLB size=64 @@ -904,7 +897,7 @@ type=ExeTracer [system.cpu2] type=DerivO3CPU -children=dcache dtb fuPool icache itb tracer +children=dcache dtb fuPool icache interrupts itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -933,6 +926,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb fetchToDecodeDelay=1 @@ -950,6 +944,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu2.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu2.itb @@ -961,6 +956,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -969,6 +965,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -1006,20 +1003,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -1305,20 +1295,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -1326,6 +1309,9 @@ write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.port[5] +[system.cpu2.interrupts] +type=SparcInterrupts + [system.cpu2.itb] type=SparcTLB size=64 @@ -1335,7 +1321,7 @@ type=ExeTracer [system.cpu3] type=DerivO3CPU -children=dcache dtb fuPool icache itb tracer +children=dcache dtb fuPool icache interrupts itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -1364,6 +1350,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb fetchToDecodeDelay=1 @@ -1381,6 +1368,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu3.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu3.itb @@ -1392,6 +1380,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -1400,6 +1389,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -1437,20 +1427,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -1736,20 +1719,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -1757,6 +1733,9 @@ write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.port[7] +[system.cpu3.interrupts] +type=SparcInterrupts + [system.cpu3.itb] type=SparcTLB size=64 @@ -1775,20 +1754,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=4 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 0491d5141..2bb2951e2 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:31 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:55 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 191a42060..befe09ef8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000104 # Nu sim_ticks 104317500 # Number of ticks simulated final_tick 104317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132902 # Simulator instruction rate (inst/s) -host_tick_rate 13605540 # Simulator tick rate (ticks/s) -host_mem_usage 226920 # Number of bytes of host memory used -host_seconds 7.67 # Real time elapsed on the host +host_inst_rate 190796 # Simulator instruction rate (inst/s) +host_op_rate 190795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19532213 # Simulator tick rate (ticks/s) +host_mem_usage 225896 # Number of bytes of host memory used +host_seconds 5.34 # Real time elapsed on the host sim_insts 1018993 # Number of instructions simulated +sim_ops 1018993 # Number of ops (including micro ops) simulated system.physmem.bytes_read 41984 # Number of bytes read from this memory system.physmem.bytes_inst_read 28224 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -234,6 +236,7 @@ system.cpu0.iew.wb_rate 1.886424 # in system.cpu0.iew.wb_fanout 0.991039 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitCommittedInsts 462799 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 462799 # The number of committed instructions system.cpu0.commit.commitSquashedInsts 9535 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1043 # The number of times a branch was mispredicted @@ -254,7 +257,8 @@ system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 188840 # Number of insts commited each cycle -system.cpu0.commit.count 462799 # Number of instructions committed +system.cpu0.commit.committedInsts 462799 # Number of instructions committed +system.cpu0.commit.committedOps 462799 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 226109 # Number of memory references committed system.cpu0.commit.loads 150402 # Number of loads committed @@ -270,6 +274,7 @@ system.cpu0.rob.rob_writes 946703 # Th system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 17790 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.committedInsts 388389 # Number of Instructions Simulated +system.cpu0.committedOps 388389 # Number of Ops (including micro ops) Simulated system.cpu0.committedInsts_total 388389 # Number of Instructions Simulated system.cpu0.cpi 0.537183 # CPI: Cycles Per Instruction system.cpu0.cpi_total 0.537183 # CPI: Total CPI of All Threads @@ -286,26 +291,39 @@ system.cpu0.icache.total_refs 4810 # To system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 8.278830 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 244.353680 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.477253 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 4810 # number of ReadReq hits -system.cpu0.icache.demand_hits 4810 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 4810 # number of overall hits -system.cpu0.icache.ReadReq_misses 705 # number of ReadReq misses -system.cpu0.icache.demand_misses 705 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 705 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 27622000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 27622000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 27622000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 5515 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 5515 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 5515 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.127833 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.127833 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.127833 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency 39180.141844 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency 39180.141844 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 39180.141844 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 244.353680 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.477253 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.477253 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 4810 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 4810 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 4810 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 4810 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 4810 # number of overall hits +system.cpu0.icache.overall_hits::total 4810 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 705 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 705 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 705 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 705 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 705 # number of overall misses +system.cpu0.icache.overall_misses::total 705 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 27622000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 27622000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 27622000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 27622000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 27622000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 27622000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5515 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5515 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5515 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5515 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5515 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5515 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.127833 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.127833 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.127833 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39180.141844 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -314,68 +332,90 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 123 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 582 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 582 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 582 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 21369000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 21369000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 21369000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.105530 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate 0.105530 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0.105530 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36716.494845 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 123 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 123 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 123 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 123 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 582 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 582 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 582 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 582 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 582 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 582 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21369000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21369000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21369000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21369000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21369000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21369000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 138.901719 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 140.432794 # Cycle average of tags in use system.cpu0.dcache.total_refs 97328 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 559.356322 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 140.432794 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.531076 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.274283 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.002990 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 77005 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 75125 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits 23 # number of SwapReq hits -system.cpu0.dcache.demand_hits 152130 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 152130 # number of overall hits -system.cpu0.dcache.ReadReq_misses 517 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses 19 # number of SwapReq misses -system.cpu0.dcache.demand_misses 1057 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 1057 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 14734500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 24692984 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency 371000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency 39427484 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 39427484 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 77522 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 75665 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 153187 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 153187 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.006669 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.007137 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate 0.452381 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.006900 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.006900 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency 28500 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency 45727.748148 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency 19526.315789 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency 37301.309366 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 37301.309366 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 140.432794 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.274283 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.274283 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 77005 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77005 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75125 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75125 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 152130 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 152130 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 152130 # number of overall hits +system.cpu0.dcache.overall_hits::total 152130 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 517 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 517 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 540 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 540 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1057 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1057 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1057 # number of overall misses +system.cpu0.dcache.overall_misses::total 1057 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14734500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14734500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24692984 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24692984 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 371000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 371000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 39427484 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 39427484 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 39427484 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 39427484 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 77522 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 77522 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 75665 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 75665 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 153187 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 153187 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 153187 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 153187 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006669 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007137 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006900 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006900 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28500 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45727.748148 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19526.315789 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -384,36 +424,46 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 327 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 368 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 695 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 695 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 190 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 172 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses 19 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 5255000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6251500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency 314000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 11506500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 11506500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002273 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.452381 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate 0.002363 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0.002363 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27657.894737 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36345.930233 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16526.315789 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31785.911602 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31785.911602 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks +system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 327 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 327 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 695 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 695 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 695 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 695 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 190 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 190 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6251500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6251500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 314000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 314000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11506500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11506500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11506500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11506500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002273 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27657.894737 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36345.930233 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16526.315789 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 174305 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -631,6 +681,7 @@ system.cpu1.iew.wb_rate 1.379140 # in system.cpu1.iew.wb_fanout 0.968192 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitCommittedInsts 275667 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 275667 # The number of committed instructions system.cpu1.commit.commitSquashedInsts 9533 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 5427 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 1085 # The number of times a branch was mispredicted @@ -651,7 +702,8 @@ system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 163203 # Number of insts commited each cycle -system.cpu1.commit.count 275667 # Number of instructions committed +system.cpu1.commit.committedInsts 275667 # Number of instructions committed +system.cpu1.commit.committedOps 275667 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 118493 # Number of memory references committed system.cpu1.commit.loads 80399 # Number of loads committed @@ -668,6 +720,7 @@ system.cpu1.timesIdled 225 # Nu system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 34329 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 231385 # Number of Instructions Simulated +system.cpu1.committedOps 231385 # Number of Ops (including micro ops) Simulated system.cpu1.committedInsts_total 231385 # Number of Instructions Simulated system.cpu1.cpi 0.753312 # CPI: Cycles Per Instruction system.cpu1.cpi_total 0.753312 # CPI: Total CPI of All Threads @@ -684,26 +737,39 @@ system.cpu1.icache.total_refs 17870 # To system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 41.850117 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 84.541118 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.165119 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 17870 # number of ReadReq hits -system.cpu1.icache.demand_hits 17870 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 17870 # number of overall hits -system.cpu1.icache.ReadReq_misses 471 # number of ReadReq misses -system.cpu1.icache.demand_misses 471 # number of demand (read+write) misses -system.cpu1.icache.overall_misses 471 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7203000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7203000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7203000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 18341 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 18341 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 18341 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.025680 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.025680 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.025680 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency 15292.993631 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency 15292.993631 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 15292.993631 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 84.541118 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.165119 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.165119 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 17870 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 17870 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 17870 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 17870 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 17870 # number of overall hits +system.cpu1.icache.overall_hits::total 17870 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 471 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 471 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 471 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 471 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 471 # number of overall misses +system.cpu1.icache.overall_misses::total 471 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7203000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7203000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7203000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7203000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7203000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7203000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 18341 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 18341 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 18341 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 18341 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 18341 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 18341 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025680 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025680 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025680 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15292.993631 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -712,68 +778,90 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 44 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 44 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 427 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5374000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5374000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5374000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.023281 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate 0.023281 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0.023281 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12585.480094 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12585.480094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12585.480094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 427 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 427 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 427 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 427 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5374000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5374000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5374000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5374000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5374000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5374000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 18.588243 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 24.401572 # Cycle average of tags in use system.cpu1.dcache.total_refs 44082 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 1469.400000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 24.401572 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -5.813330 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.047659 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::1 -0.011354 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 46660 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 37905 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits 84565 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 84565 # number of overall hits -system.cpu1.dcache.ReadReq_misses 478 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 124 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 52 # number of SwapReq misses -system.cpu1.dcache.demand_misses 602 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 602 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 10261500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 2943000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency 1149500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency 13204500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 13204500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 47138 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 38029 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 85167 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 85167 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.010140 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.003261 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.007068 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.007068 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency 21467.573222 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency 23733.870968 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency 22105.769231 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency 21934.385382 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 21934.385382 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 24.401572 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.047659 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.047659 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 46660 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 46660 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 37905 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 37905 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 84565 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 84565 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 84565 # number of overall hits +system.cpu1.dcache.overall_hits::total 84565 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 478 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 124 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 124 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 602 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 602 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 602 # number of overall misses +system.cpu1.dcache.overall_misses::total 602 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10261500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 10261500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2943000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2943000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1149500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1149500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13204500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13204500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13204500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13204500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 47138 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 47138 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 38029 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 38029 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 85167 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 85167 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 85167 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 85167 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010140 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003261 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007068 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007068 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21467.573222 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23733.870968 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 22105.769231 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21934.385382 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21934.385382 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -782,36 +870,46 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 323 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 341 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 341 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 261 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 261 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2079000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1617000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency 993500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 3696000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 3696000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003288 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002787 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate 0.003065 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0.003065 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13412.903226 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15254.716981 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19105.769231 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14160.919540 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14160.919540 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu1.dcache.writebacks::total 1 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 18 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 18 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 341 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 341 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 261 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 261 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2079000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2079000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1617000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1617000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 993500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 993500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3696000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3696000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3696000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3696000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003288 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002787 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13412.903226 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15254.716981 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 19105.769231 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 174018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -1029,6 +1127,7 @@ system.cpu2.iew.wb_rate 1.290855 # in system.cpu2.iew.wb_fanout 0.966435 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitCommittedInsts 256708 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 256708 # The number of committed instructions system.cpu2.commit.commitSquashedInsts 10074 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 5686 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 1149 # The number of times a branch was mispredicted @@ -1049,7 +1148,8 @@ system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::total 160519 # Number of insts commited each cycle -system.cpu2.commit.count 256708 # Number of instructions committed +system.cpu2.commit.committedInsts 256708 # Number of instructions committed +system.cpu2.commit.committedOps 256708 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed system.cpu2.commit.refs 108759 # Number of memory references committed system.cpu2.commit.loads 73984 # Number of loads committed @@ -1066,6 +1166,7 @@ system.cpu2.timesIdled 232 # Nu system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 34616 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu2.committedInsts 215254 # Number of Instructions Simulated +system.cpu2.committedOps 215254 # Number of Ops (including micro ops) Simulated system.cpu2.committedInsts_total 215254 # Number of Instructions Simulated system.cpu2.cpi 0.808431 # CPI: Cycles Per Instruction system.cpu2.cpi_total 0.808431 # CPI: Total CPI of All Threads @@ -1082,26 +1183,39 @@ system.cpu2.icache.total_refs 18578 # To system.cpu2.icache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 43.508197 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 85.227474 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.166460 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 18578 # number of ReadReq hits -system.cpu2.icache.demand_hits 18578 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 18578 # number of overall hits -system.cpu2.icache.ReadReq_misses 481 # number of ReadReq misses -system.cpu2.icache.demand_misses 481 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 481 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency 10446500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency 10446500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 10446500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 19059 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 19059 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 19059 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.025237 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.025237 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.025237 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency 21718.295218 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency 21718.295218 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 21718.295218 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 85.227474 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.166460 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.166460 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 18578 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 18578 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 18578 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 18578 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 18578 # number of overall hits +system.cpu2.icache.overall_hits::total 18578 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 481 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 481 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 481 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 481 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 481 # number of overall misses +system.cpu2.icache.overall_misses::total 481 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 10446500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 10446500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 10446500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 10446500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 10446500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 10446500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19059 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19059 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19059 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19059 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19059 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19059 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.025237 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.025237 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.025237 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21718.295218 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1110,68 +1224,90 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 427 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.ReadReq_mshr_miss_latency 8026500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency 8026500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 8026500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.022404 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate 0.022404 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0.022404 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18797.423888 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 54 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 54 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 54 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 54 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 54 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 427 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 427 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 427 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 427 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8026500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 8026500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8026500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 8026500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8026500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 8026500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 19.370911 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 26.582846 # Cycle average of tags in use system.cpu2.dcache.total_refs 40686 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 1356.200000 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 26.582846 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -7.211935 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.051920 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::1 -0.014086 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 43569 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 34581 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits 78150 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 78150 # number of overall hits -system.cpu2.dcache.ReadReq_misses 459 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 120 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses 61 # number of SwapReq misses -system.cpu2.dcache.demand_misses 579 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses 579 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency 10999500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency 2980500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency 1343500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency 13980000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 13980000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 44028 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 34701 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 78729 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 78729 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.010425 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.003458 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.824324 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.007354 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.007354 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency 23964.052288 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency 24837.500000 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency 22024.590164 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency 24145.077720 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 24145.077720 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.582846 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.051920 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.051920 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 43569 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 43569 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 34581 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 34581 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 78150 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 78150 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 78150 # number of overall hits +system.cpu2.dcache.overall_hits::total 78150 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 459 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 459 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 120 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 120 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 61 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 61 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 579 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 579 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 579 # number of overall misses +system.cpu2.dcache.overall_misses::total 579 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10999500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 10999500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2980500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2980500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1343500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 1343500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 13980000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 13980000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 13980000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 13980000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 44028 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 44028 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 34701 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 34701 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 78729 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 78729 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 78729 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 78729 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010425 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003458 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.824324 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007354 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007354 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23964.052288 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24837.500000 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 22024.590164 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1180,36 +1316,46 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits 315 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 315 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses 61 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2380000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency 1660000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency 1160500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency 4040000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 4040000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003679 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002939 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.824324 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate 0.003353 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0.003353 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14691.358025 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19024.590164 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu2.dcache.writebacks::total 1 # number of writebacks +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 297 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 297 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 18 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 18 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 315 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 315 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 61 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 264 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 264 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2380000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2380000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1660000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1660000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1160500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1160500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4040000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4040000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4040000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4040000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002939 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.824324 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14691.358025 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16274.509804 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 19024.590164 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173752 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -1427,6 +1573,7 @@ system.cpu3.iew.wb_rate 1.121909 # in system.cpu3.iew.wb_fanout 0.961453 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu3.commit.commitCommittedInsts 222296 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 222296 # The number of committed instructions system.cpu3.commit.commitSquashedInsts 9409 # The number of squashed insts skipped by commit system.cpu3.commit.commitNonSpecStalls 7641 # The number of times commit has been forced to stall to communicate backwards system.cpu3.commit.branchMispredicts 1065 # The number of times a branch was mispredicted @@ -1447,7 +1594,8 @@ system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::total 162652 # Number of insts commited each cycle -system.cpu3.commit.count 222296 # Number of instructions committed +system.cpu3.commit.committedInsts 222296 # Number of instructions committed +system.cpu3.commit.committedOps 222296 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed system.cpu3.commit.refs 89597 # Number of memory references committed system.cpu3.commit.loads 61865 # Number of loads committed @@ -1464,6 +1612,7 @@ system.cpu3.timesIdled 234 # Nu system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 34882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu3.committedInsts 183965 # Number of Instructions Simulated +system.cpu3.committedOps 183965 # Number of Ops (including micro ops) Simulated system.cpu3.committedInsts_total 183965 # Number of Instructions Simulated system.cpu3.cpi 0.944484 # CPI: Cycles Per Instruction system.cpu3.cpi_total 0.944484 # CPI: Total CPI of All Threads @@ -1480,26 +1629,39 @@ system.cpu3.icache.total_refs 22493 # To system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 52.800469 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 80.006059 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.156262 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 22493 # number of ReadReq hits -system.cpu3.icache.demand_hits 22493 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 22493 # number of overall hits -system.cpu3.icache.ReadReq_misses 466 # number of ReadReq misses -system.cpu3.icache.demand_misses 466 # number of demand (read+write) misses -system.cpu3.icache.overall_misses 466 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency 6527000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency 6527000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 6527000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 22959 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 22959 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 22959 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.020297 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.020297 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.020297 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency 14006.437768 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency 14006.437768 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 14006.437768 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 80.006059 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.156262 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.156262 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 22493 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 22493 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 22493 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 22493 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 22493 # number of overall hits +system.cpu3.icache.overall_hits::total 22493 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 466 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 466 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 466 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 466 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 466 # number of overall misses +system.cpu3.icache.overall_misses::total 466 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6527000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6527000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6527000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6527000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6527000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6527000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 22959 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 22959 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 22959 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 22959 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 22959 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 22959 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020297 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020297 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020297 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14006.437768 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1508,68 +1670,90 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits 40 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses 426 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.ReadReq_mshr_miss_latency 4833500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency 4833500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 4833500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.018555 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate 0.018555 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0.018555 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11346.244131 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11346.244131 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11346.244131 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 40 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 40 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 40 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 40 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 40 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 426 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 426 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 426 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 426 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 426 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4833500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4833500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4833500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4833500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4833500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4833500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 13.455705 # Cycle average of tags in use +system.cpu3.dcache.tagsinuse 23.407477 # Cycle average of tags in use system.cpu3.dcache.total_refs 33584 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.avg_refs 1158.068966 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 23.407477 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -9.951772 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.045718 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::1 -0.019437 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 38412 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 27537 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits 65949 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 65949 # number of overall hits -system.cpu3.dcache.ReadReq_misses 448 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 125 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 56 # number of SwapReq misses -system.cpu3.dcache.demand_misses 573 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 573 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency 9358000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency 2911000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency 1350500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency 12269000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 12269000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 38860 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 27662 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 66522 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 66522 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.011529 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.004519 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.008614 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.008614 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency 20888.392857 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency 23288 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency 24116.071429 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency 21411.867365 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 21411.867365 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 23.407477 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.045718 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.045718 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 38412 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 38412 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 27537 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 27537 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 65949 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 65949 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 65949 # number of overall hits +system.cpu3.dcache.overall_hits::total 65949 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 448 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 448 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 125 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 125 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 573 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 573 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 573 # number of overall misses +system.cpu3.dcache.overall_misses::total 573 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9358000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 9358000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2911000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2911000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1350500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 1350500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 12269000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 12269000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 12269000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 12269000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 38860 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 38860 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 27662 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 27662 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 66522 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 66522 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 66522 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 66522 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011529 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004519 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.800000 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008614 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008614 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20888.392857 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23288 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 24116.071429 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 21411.867365 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 21411.867365 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1578,36 +1762,46 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits 279 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 296 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses 169 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 277 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 2218000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency 1624500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency 1182500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency 3842500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 3842500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004349 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003904 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.800000 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate 0.004164 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0.004164 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13124.260355 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15041.666667 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 21116.071429 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 13871.841155 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 13871.841155 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu3.dcache.writebacks::total 1 # number of writebacks +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 279 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 17 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 17 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 296 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 296 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 169 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 277 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 277 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2218000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2218000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1624500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1624500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1182500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1182500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3842500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3842500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3842500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3842500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004349 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003904 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004164 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004164 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13124.260355 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15041.666667 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 21116.071429 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13871.841155 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13871.841155 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 428.231635 # Cycle average of tags in use @@ -1615,142 +1809,231 @@ system.l2c.total_refs 1446 # To system.l2c.sampled_refs 527 # Sample count of references to valid blocks. system.l2c.avg_refs 2.743833 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 347.174574 # Average occupied blocks per context -system.l2c.occ_blocks::1 11.269547 # Average occupied blocks per context -system.l2c.occ_blocks::2 63.254631 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.567259 # Average occupied blocks per context -system.l2c.occ_blocks::4 4.965624 # Average occupied blocks per context -system.l2c.occ_percent::0 0.005297 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.000172 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000965 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.000024 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000076 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 233 # number of ReadReq hits -system.l2c.ReadReq_hits::1 424 # number of ReadReq hits -system.l2c.ReadReq_hits::2 356 # number of ReadReq hits -system.l2c.ReadReq_hits::3 436 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 4.965624 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 287.776309 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.398265 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 10.494682 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 0.774865 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 57.571117 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 5.683514 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 0.828706 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.738553 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000076 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004391 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000906 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000160 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000878 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000087 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006534 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 228 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits 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# number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 228 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 7 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 12 # number of demand (read+write) hits system.l2c.demand_hits::total 1449 # number of demand (read+write) hits -system.l2c.overall_hits::0 233 # number of overall hits -system.l2c.overall_hits::1 424 # number of overall hits -system.l2c.overall_hits::2 356 # number of overall hits -system.l2c.overall_hits::3 436 # number of overall hits +system.l2c.overall_hits::cpu0.inst 228 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 412 # number of overall hits +system.l2c.overall_hits::cpu1.data 12 # number of overall hits +system.l2c.overall_hits::cpu2.inst 349 # number of overall hits +system.l2c.overall_hits::cpu2.data 7 # number of overall hits +system.l2c.overall_hits::cpu3.inst 424 # number of overall hits +system.l2c.overall_hits::cpu3.data 12 # number of overall hits system.l2c.overall_hits::total 1449 # number of overall hits -system.l2c.ReadReq_misses::0 429 # number of ReadReq misses -system.l2c.ReadReq_misses::1 16 # number of ReadReq misses -system.l2c.ReadReq_misses::2 85 # number of ReadReq misses -system.l2c.ReadReq_misses::3 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 354 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 78 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses 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352846.938776 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 2305266.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3959194.525956 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.inst 0.608247 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.035129 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.076923 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.182670 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.004695 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.076923 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses 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miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52094.632768 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52494.082840 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 49666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 51493.589744 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52425 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 48000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1759,55 +2042,159 @@ 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3.625000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 3.954545 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 3.954545 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 3.954545 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 15.488636 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.867725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.451327 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.444934 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.454545 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.218532 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.867725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.451327 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.444934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.454545 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.218532 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40049.542683 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40049.542683 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 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3480000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3792000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 524500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5279000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 14091500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6811000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 561000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 521000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 2922000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 804500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 26272500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 14091500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6811000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 561000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 521000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2922000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 804500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 26272500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40253.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40340.425532 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40083.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40346.153846 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 65fcae2f7..90b4c4184 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[2] [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer workload +children=dcache dtb icache interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu0.interrupts itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -61,20 +71,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -97,20 +100,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -118,6 +114,9 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu0.interrupts] +type=SparcInterrupts + [system.cpu0.itb] type=SparcTLB size=64 @@ -146,16 +145,18 @@ uid=100 [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu1.interrupts itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -163,6 +164,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -184,20 +186,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -220,20 +215,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -241,6 +229,9 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] +[system.cpu1.interrupts] +type=SparcInterrupts + [system.cpu1.itb] type=SparcTLB size=64 @@ -250,16 +241,18 @@ type=ExeTracer [system.cpu2] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=2 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu2.interrupts itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -267,6 +260,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -288,20 +282,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -324,20 +311,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -345,6 +325,9 @@ write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.port[5] +[system.cpu2.interrupts] +type=SparcInterrupts + [system.cpu2.itb] type=SparcTLB size=64 @@ -354,16 +337,18 @@ type=ExeTracer [system.cpu3] type=AtomicSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=3 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu3.interrupts itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -371,6 +356,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -392,20 +378,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -428,20 +407,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -449,6 +421,9 @@ write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.port[7] +[system.cpu3.interrupts] +type=SparcInterrupts + [system.cpu3.itb] type=SparcTLB size=64 @@ -467,20 +442,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=4 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 8daa6c894..4d44fa6f6 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:32 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:56 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 0cc0a830c..71dd904a3 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000088 # Nu sim_ticks 87713500 # Number of ticks simulated final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1650324 # Simulator instruction rate (inst/s) -host_tick_rate 213702670 # Simulator tick rate (ticks/s) -host_mem_usage 1140448 # Number of bytes of host memory used +host_inst_rate 1664146 # Simulator instruction rate (inst/s) +host_op_rate 1664073 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215483439 # Simulator tick rate (ticks/s) +host_mem_usage 1139232 # Number of bytes of host memory used host_seconds 0.41 # Real time elapsed on the host sim_insts 677340 # Number of instructions simulated +sim_ops 677340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 35776 # Number of bytes read from this memory system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu0.workload.num_syscalls 89 # Nu system.cpu0.numCycles 175428 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 175339 # Number of instructions executed +system.cpu0.committedInsts 175339 # Number of instructions committed +system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured @@ -46,24 +49,30 @@ system.cpu0.icache.total_refs 174934 # To system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 222.757301 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.435073 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 174934 # number of ReadReq hits -system.cpu0.icache.demand_hits 174934 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 174934 # number of overall hits -system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses -system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 467 # number of overall misses -system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 175401 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 175401 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.002662 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.002662 # miss rate for overall accesses -system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 222.757301 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.435073 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.435073 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 174934 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 174934 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 174934 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 174934 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 174934 # number of overall hits +system.cpu0.icache.overall_hits::total 174934 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -72,22 +81,6 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use @@ -95,32 +88,44 @@ system.cpu0.dcache.total_refs 61599 # To system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.284595 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 54431 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 27578 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits 15 # number of SwapReq hits -system.cpu0.dcache.demand_hits 82009 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 82009 # number of overall hits -system.cpu0.dcache.ReadReq_misses 151 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses 177 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses 27 # number of SwapReq misses -system.cpu0.dcache.demand_misses 328 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 328 # number of overall misses -system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 54582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 82337 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 82337 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.002766 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.003984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.003984 # miss rate for overall accesses -system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 82009 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 82009 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 82009 # number of overall hits +system.cpu0.dcache.overall_hits::total 82009 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses +system.cpu0.dcache.overall_misses::total 328 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 54582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 54582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 82337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 82337 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,27 +134,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks +system.cpu0.dcache.writebacks::total 6 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173308 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 167398 # Number of instructions executed +system.cpu1.committedInsts 167398 # Number of instructions committed +system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 633 # number of times a function call or return occured @@ -173,24 +165,30 @@ system.cpu1.icache.total_refs 167072 # To system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 76.746014 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.149895 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 167072 # number of ReadReq hits -system.cpu1.icache.demand_hits 167072 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 167072 # number of overall hits -system.cpu1.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu1.icache.demand_misses 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses 358 # number of overall misses -system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 167430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 167430 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 167430 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.002138 # miss rate for overall accesses -system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 76.746014 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.149895 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.149895 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits +system.cpu1.icache.overall_hits::total 167072 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses +system.cpu1.icache.overall_misses::total 358 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,22 +197,6 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use @@ -222,32 +204,44 @@ system.cpu1.dcache.total_refs 26889 # To system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 29.073016 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.056783 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 40468 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 12563 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits 53031 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 53031 # number of overall hits -system.cpu1.dcache.ReadReq_misses 176 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses 282 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 282 # number of overall misses -system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 40644 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 12669 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 53313 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 53313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.004330 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses -system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 29.073016 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.056783 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.056783 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 40468 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40468 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 53031 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 53031 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 53031 # number of overall hits +system.cpu1.dcache.overall_hits::total 53031 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 176 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 176 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses +system.cpu1.dcache.overall_misses::total 282 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,27 +250,14 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu1.dcache.writebacks::total 1 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173308 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.num_insts 167334 # Number of instructions executed +system.cpu2.committedInsts 167334 # Number of instructions committed +system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 633 # number of times a function call or return occured @@ -300,24 +281,30 @@ system.cpu2.icache.total_refs 167008 # To system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 74.775474 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.146046 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 167008 # number of ReadReq hits -system.cpu2.icache.demand_hits 167008 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 167008 # number of overall hits -system.cpu2.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu2.icache.demand_misses 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 358 # number of overall misses -system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 167366 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 167366 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 167366 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.002139 # miss rate for overall accesses -system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 74.775474 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.146046 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.146046 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits +system.cpu2.icache.overall_hits::total 167008 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses +system.cpu2.icache.overall_misses::total 358 # number of overall misses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,22 +313,6 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use @@ -349,32 +320,44 @@ system.cpu2.dcache.total_refs 33771 # To system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 28.420699 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.055509 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 42192 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 15998 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits 58190 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 58190 # number of overall hits -system.cpu2.dcache.ReadReq_misses 162 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses 271 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses 271 # number of overall misses -system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 42354 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 16107 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 58461 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 58461 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.003825 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses -system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 28.420699 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.055509 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.055509 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42192 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42192 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 58190 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58190 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58190 # number of overall hits +system.cpu2.dcache.overall_hits::total 58190 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses +system.cpu2.dcache.overall_misses::total 271 # number of overall misses +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,27 +366,14 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu2.dcache.writebacks::total 1 # number of writebacks system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173307 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.num_insts 167269 # Number of instructions executed +system.cpu3.committedInsts 167269 # Number of instructions committed +system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 633 # number of times a function call or return occured @@ -427,24 +397,30 @@ system.cpu3.icache.total_refs 166942 # To system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 72.869097 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.142322 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 166942 # number of ReadReq hits -system.cpu3.icache.demand_hits 166942 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 166942 # number of overall hits -system.cpu3.icache.ReadReq_misses 359 # number of ReadReq misses -system.cpu3.icache.demand_misses 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses 359 # number of overall misses -system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 167301 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 167301 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 167301 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.002146 # miss rate for overall accesses -system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 72.869097 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.142322 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.142322 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits +system.cpu3.icache.overall_hits::total 166942 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses +system.cpu3.icache.overall_misses::total 359 # number of overall misses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,22 +429,6 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use @@ -476,32 +436,44 @@ system.cpu3.dcache.total_refs 30309 # To system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 27.588376 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.053884 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 41299 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 14260 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits 55559 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 55559 # number of overall hits -system.cpu3.dcache.ReadReq_misses 159 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 102 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu3.dcache.demand_misses 261 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 261 # number of overall misses -system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 41458 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 14362 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 55820 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 55820 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.003835 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses -system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 27.588376 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.053884 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.053884 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41299 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41299 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 55559 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 55559 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 55559 # number of overall hits +system.cpu3.dcache.overall_hits::total 55559 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 261 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 261 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 261 # number of overall misses +system.cpu3.dcache.overall_misses::total 261 # number of overall misses +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,22 +482,8 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu3.dcache.writebacks::total 1 # number of writebacks system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 371.980910 # Cycle average of tags in use @@ -533,124 +491,164 @@ system.l2c.total_refs 1223 # To system.l2c.sampled_refs 426 # Sample count of references to valid blocks. system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 294.613840 # Average occupied blocks per context -system.l2c.occ_blocks::1 66.228089 # Average occupied blocks per context -system.l2c.occ_blocks::2 2.865859 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.883074 # Average occupied blocks per context -system.l2c.occ_blocks::4 6.390048 # Average occupied blocks per context -system.l2c.occ_percent::0 0.004495 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.001011 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000044 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.000029 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000098 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 190 # number of ReadReq hits -system.l2c.ReadReq_hits::1 301 # number of ReadReq hits -system.l2c.ReadReq_hits::2 367 # number of ReadReq hits -system.l2c.ReadReq_hits::3 368 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 6.390048 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 6.720647 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.930518 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000098 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005676 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits -system.l2c.Writeback_hits::0 9 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::0 190 # number of demand (read+write) hits -system.l2c.demand_hits::1 301 # number of demand (read+write) hits -system.l2c.demand_hits::2 367 # number of demand (read+write) hits -system.l2c.demand_hits::3 368 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits system.l2c.demand_hits::total 1226 # number of demand (read+write) hits -system.l2c.overall_hits::0 190 # number of overall hits -system.l2c.overall_hits::1 301 # number of overall hits -system.l2c.overall_hits::2 367 # number of overall hits -system.l2c.overall_hits::3 368 # number of overall hits +system.l2c.overall_hits::cpu0.inst 185 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 296 # number of overall hits +system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu2.inst 356 # number of overall hits +system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu3.inst 357 # number of overall hits +system.l2c.overall_hits::cpu3.data 11 # number of overall hits system.l2c.overall_hits::total 1226 # number of overall hits -system.l2c.ReadReq_misses::0 348 # number of ReadReq misses -system.l2c.ReadReq_misses::1 69 # number of ReadReq misses -system.l2c.ReadReq_misses::2 3 # number of ReadReq misses -system.l2c.ReadReq_misses::3 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.demand_misses::0 447 # number of demand (read+write) misses -system.l2c.demand_misses::1 82 # number of demand (read+write) misses -system.l2c.demand_misses::2 15 # number of demand (read+write) misses -system.l2c.demand_misses::3 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::0 447 # number of overall misses -system.l2c.overall_misses::1 82 # number of overall misses -system.l2c.overall_misses::2 15 # number of overall misses -system.l2c.overall_misses::3 15 # number of overall misses +system.l2c.overall_misses::cpu0.inst 282 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 62 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 2 # number of overall misses +system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 371 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 382 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.646840 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.186486 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.008108 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.008086 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.849521 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.935484 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 3.935484 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.701727 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.214099 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.039267 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.039164 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.994258 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.701727 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.214099 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.039267 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.039164 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.994258 # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -659,30 +657,6 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 0 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index ae7e021b5..c00589f53 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[1] [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache itb tracer workload +children=dcache dtb icache interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu0.interrupts itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu0.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu0.interrupts] +type=SparcInterrupts + [system.cpu0.itb] type=SparcTLB size=64 @@ -143,16 +142,18 @@ uid=100 [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu1.interrupts itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -160,6 +161,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu1.tracer @@ -178,20 +180,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -214,20 +209,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -235,6 +223,9 @@ write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] +[system.cpu1.interrupts] +type=SparcInterrupts + [system.cpu1.itb] type=SparcTLB size=64 @@ -244,16 +235,18 @@ type=ExeTracer [system.cpu2] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=2 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu2.interrupts itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -261,6 +254,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu2.tracer @@ -279,20 +273,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -315,20 +302,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -336,6 +316,9 @@ write_buffers=8 cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.port[5] +[system.cpu2.interrupts] +type=SparcInterrupts + [system.cpu2.itb] type=SparcTLB size=64 @@ -345,16 +328,18 @@ type=ExeTracer [system.cpu3] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer checker=Null clock=500 cpu_id=3 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu3.interrupts itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -362,6 +347,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu3.tracer @@ -380,20 +366,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -416,20 +395,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -437,6 +409,9 @@ write_buffers=8 cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.port[7] +[system.cpu3.interrupts] +type=SparcInterrupts + [system.cpu3.itb] type=SparcTLB size=64 @@ -455,20 +430,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=4 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 6f90c0dd1..bd048d482 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:33 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:56:07 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 0ce3fe3af..fcff65a90 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000262 # Nu sim_ticks 262298000 # Number of ticks simulated final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1158712 # Simulator instruction rate (inst/s) -host_tick_rate 458877844 # Simulator tick rate (ticks/s) -host_mem_usage 222944 # Number of bytes of host memory used -host_seconds 0.57 # Real time elapsed on the host +host_inst_rate 1330969 # Simulator instruction rate (inst/s) +host_op_rate 1330920 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 527074583 # Simulator tick rate (ticks/s) +host_mem_usage 221728 # Number of bytes of host memory used +host_seconds 0.50 # Real time elapsed on the host sim_insts 662307 # Number of instructions simulated +sim_ops 662307 # Number of ops (including micro ops) simulated system.physmem.bytes_read 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu0.workload.num_syscalls 89 # Nu system.cpu0.numCycles 524596 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 158353 # Number of instructions executed +system.cpu0.committedInsts 158353 # Number of instructions committed +system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu0.icache.total_refs 157949 # To system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 212.479188 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.414998 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 157949 # number of ReadReq hits -system.cpu0.icache.demand_hits 157949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 157949 # number of overall hits -system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses -system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 18524000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 18524000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 18524000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 158416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 158416 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 158416 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.002948 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.002948 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.002948 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency 39665.952891 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency 39665.952891 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits +system.cpu0.icache.overall_hits::total 157949 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 17123000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 17123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 17123000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.002948 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate 0.002948 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0.002948 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36665.952891 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use @@ -101,38 +115,59 @@ system.cpu0.dcache.total_refs 56009 # To system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 141.233342 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.275846 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 48758 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 24741 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits 73499 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 73499 # number of overall hits -system.cpu0.dcache.ReadReq_misses 162 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses 183 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency 387000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 11924000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 73844 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 73844 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.003312 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.007342 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.004672 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.004672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 34562.318841 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits +system.cpu0.dcache.overall_hits::total 73499 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses +system.cpu0.dcache.overall_misses::total 345 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,39 +176,44 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 183 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 345 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.003312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.007342 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate 0.004672 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks +system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 524596 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 172325 # Number of instructions executed +system.cpu1.committedInsts 172325 # Number of instructions committed +system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured @@ -197,26 +237,39 @@ system.cpu1.icache.total_refs 171992 # To system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 70.076133 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 171992 # number of ReadReq hits -system.cpu1.icache.demand_hits 171992 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 171992 # number of overall hits -system.cpu1.icache.ReadReq_misses 366 # number of ReadReq misses -system.cpu1.icache.demand_misses 366 # number of demand (read+write) misses -system.cpu1.icache.overall_misses 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7920500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7920500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7920500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 172358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 172358 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 172358 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.002123 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.002123 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.002123 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency 21640.710383 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency 21640.710383 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 21640.710383 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits +system.cpu1.icache.overall_hits::total 171992 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses +system.cpu1.icache.overall_misses::total 366 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7920500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7920500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7920500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7920500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -225,67 +278,84 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 366 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 6822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 6822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 6822000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.002123 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate 0.002123 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 18639.344262 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 22.703917 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 26.693562 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -3.989645 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.052136 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::1 -0.007792 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 39428 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 8099 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 18 # number of SwapReq hits -system.cpu1.dcache.demand_hits 47527 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 47527 # number of overall hits -system.cpu1.dcache.ReadReq_misses 181 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 98 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 65 # number of SwapReq misses -system.cpu1.dcache.demand_misses 279 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 279 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 3713000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 1889000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency 415000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency 5602000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 5602000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 39609 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 8197 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 47806 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 47806 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.004570 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.011956 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.005836 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.005836 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency 20513.812155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency 19275.510204 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency 20078.853047 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 20078.853047 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.052136 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.052136 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 39428 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39428 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 47527 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 47527 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 47527 # number of overall hits +system.cpu1.dcache.overall_hits::total 47527 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 181 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 181 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 279 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 279 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 279 # number of overall misses +system.cpu1.dcache.overall_misses::total 279 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3713000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3713000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1889000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1889000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5602000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5602000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5602000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5602000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -294,39 +364,44 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 279 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 3170000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1595000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004570 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.011956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16275.510204 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu1.dcache.writebacks::total 1 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 524596 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.num_insts 165499 # Number of instructions executed +system.cpu2.committedInsts 165499 # Number of instructions committed +system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured @@ -350,26 +425,39 @@ system.cpu2.icache.total_refs 165166 # To system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 65.601019 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 165166 # number of ReadReq hits -system.cpu2.icache.demand_hits 165166 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 165166 # number of overall hits -system.cpu2.icache.ReadReq_misses 366 # number of ReadReq misses -system.cpu2.icache.demand_misses 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency 5648500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency 5648500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 5648500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 165532 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 165532 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.002211 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.002211 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency 15433.060109 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency 15433.060109 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 15433.060109 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits +system.cpu2.icache.overall_hits::total 165166 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses +system.cpu2.icache.overall_misses::total 366 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5648500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5648500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,67 +466,84 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.ReadReq_mshr_miss_latency 4550500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency 4550500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 4550500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0.002211 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 12433.060109 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 12433.060109 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 23.305393 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 24.943438 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -1.638045 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::1 -0.003199 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 41688 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 15916 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits 57604 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 57604 # number of overall hits -system.cpu2.dcache.ReadReq_misses 156 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses 265 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses 265 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency 2084000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency 305000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 4611000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 41844 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 16025 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 62 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 57869 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 57869 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.003728 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.006802 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.004579 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.004579 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency 19119.266055 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency 5980.392157 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 17400 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits +system.cpu2.dcache.overall_hits::total 57604 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses +system.cpu2.dcache.overall_misses::total 265 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,39 +552,44 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency 1757000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003728 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.006802 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16119.266055 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu2.dcache.writebacks::total 1 # number of writebacks +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 524596 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.num_insts 166130 # Number of instructions executed +system.cpu3.committedInsts 166130 # Number of instructions committed +system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured @@ -503,26 +613,39 @@ system.cpu3.icache.total_refs 165796 # To system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 67.737646 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 165796 # number of ReadReq hits -system.cpu3.icache.demand_hits 165796 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 165796 # number of overall hits -system.cpu3.icache.ReadReq_misses 367 # number of ReadReq misses -system.cpu3.icache.demand_misses 367 # number of demand (read+write) misses -system.cpu3.icache.overall_misses 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency 5531500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 5531500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 166163 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 166163 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.002209 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.002209 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency 15072.207084 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 15072.207084 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits +system.cpu3.icache.overall_hits::total 165796 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses +system.cpu3.icache.overall_misses::total 367 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,67 +654,84 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses 367 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses 367 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.ReadReq_mshr_miss_latency 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 4430500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.002209 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate 0.002209 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0.002209 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 12072.207084 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency 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-system.cpu3.dcache.occ_percent::1 -0.007034 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 41555 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 15348 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits 56903 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 56903 # number of overall hits -system.cpu3.dcache.ReadReq_misses 157 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 108 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses 265 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 265 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency 2569000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency 2080000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency 326000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency 4649000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 4649000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 41712 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 15456 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 57168 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 57168 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.003764 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.006988 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.830769 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.004635 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.004635 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency 16363.057325 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency 19259.259259 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 17543.396226 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.050166 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.050166 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41555 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41555 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 56903 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 56903 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 56903 # number of overall hits +system.cpu3.dcache.overall_hits::total 56903 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 265 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 265 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 265 # number of overall misses +system.cpu3.dcache.overall_misses::total 265 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2569000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2569000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2080000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2080000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4649000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4649000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4649000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4649000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41712 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41712 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -600,34 +740,38 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses 157 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 265 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 2098000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency 1756000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency 164000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003764 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.006988 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.830769 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate 0.004635 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0.004635 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13363.057325 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16259.259259 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 3037.037037 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu3.dcache.writebacks::total 1 # number of writebacks +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 265 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 265 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2098000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1756000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1756000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 353.886259 # Cycle average of tags in use @@ -635,142 +779,231 @@ system.l2c.total_refs 1223 # To system.l2c.sampled_refs 434 # Sample count of references to valid blocks. system.l2c.avg_refs 2.817972 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 286.079543 # Average occupied blocks per context -system.l2c.occ_blocks::1 57.730360 # Average occupied blocks per context -system.l2c.occ_blocks::2 2.746586 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.731874 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.597896 # Average occupied blocks per context -system.l2c.occ_percent::0 0.004365 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.000881 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.000026 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000085 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 187 # number of ReadReq hits -system.l2c.ReadReq_hits::1 305 # number of ReadReq hits -system.l2c.ReadReq_hits::2 365 # number of ReadReq hits -system.l2c.ReadReq_hits::3 369 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 5.597896 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 231.859183 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 54.220360 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 51.601293 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 6.129067 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.914986 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.831600 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 0.887228 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.844646 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000085 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005400 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits -system.l2c.Writeback_hits::0 9 # number of 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# number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses -system.l2c.demand_misses::0 450 # number of demand (read+write) misses -system.l2c.demand_misses::1 89 # number of demand (read+write) misses -system.l2c.demand_misses::2 28 # number of demand (read+write) misses -system.l2c.demand_misses::3 25 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses system.l2c.demand_misses::total 592 # number of demand (read+write) misses -system.l2c.overall_misses::0 450 # number of overall misses -system.l2c.overall_misses::1 89 # number of overall misses -system.l2c.overall_misses::2 28 # number of overall misses -system.l2c.overall_misses::3 25 # number of overall misses +system.l2c.overall_misses::cpu0.inst 285 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 66 # number of overall misses +system.l2c.overall_misses::cpu1.data 23 # number of overall misses +system.l2c.overall_misses::cpu2.inst 12 # number of overall misses +system.l2c.overall_misses::cpu2.data 16 # number of overall misses +system.l2c.overall_misses::cpu3.inst 9 # number of overall misses +system.l2c.overall_misses::cpu3.data 16 # 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ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 781000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7385000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14822000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8580000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3416000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1194000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 615000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 832000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 429000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 827000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30715000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14822000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3416000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1194000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 615000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 832000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 429000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 827000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30715000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 12 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 12 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 15 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 394 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 393 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 394 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 27 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 394 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 393 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 394 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 28 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 27 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1818 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.652416 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.195251 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.036939 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.028947 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.913554 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 3.933333 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.706436 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.225888 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.071247 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.063452 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 1.067023 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.706436 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.225888 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.071247 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.063452 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 1.067023 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 66467.236467 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 315270.270270 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 1666428.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 2120909.090909 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 4169075.169075 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 5571.428571 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 13000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 9750 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 9750 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 38071.428571 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 74595.959596 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 492333.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 527500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 527500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1621929.292929 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 68255.555556 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 345112.359551 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 1096964.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 1228600 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 2738932.200820 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 68255.555556 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 345112.359551 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 1096964.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 1228600 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 2738932.200820 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq 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rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini index f1d5fb57f..dacf2f87f 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini @@ -41,6 +41,7 @@ percent_source_unaligned=50 percent_uncacheable=0 progress_interval=10000 suppress_func_warnings=true +sys=system trace_addr=0 functional=system.funcmem.port[0] test=system.l1_cntrl0.sequencer.port[0] @@ -58,6 +59,7 @@ percent_source_unaligned=50 percent_uncacheable=0 progress_interval=10000 suppress_func_warnings=true +sys=system trace_addr=0 functional=system.funcmem.port[1] test=system.l1_cntrl1.sequencer.port[0] @@ -75,6 +77,7 @@ percent_source_unaligned=50 percent_uncacheable=0 progress_interval=10000 suppress_func_warnings=true +sys=system trace_addr=0 functional=system.funcmem.port[2] test=system.l1_cntrl2.sequencer.port[0] @@ -92,6 +95,7 @@ percent_source_unaligned=50 percent_uncacheable=0 progress_interval=10000 suppress_func_warnings=true +sys=system trace_addr=0 functional=system.funcmem.port[3] test=system.l1_cntrl3.sequencer.port[0] @@ -109,6 +113,7 @@ percent_source_unaligned=50 percent_uncacheable=0 progress_interval=10000 suppress_func_warnings=true +sys=system trace_addr=0 functional=system.funcmem.port[4] test=system.l1_cntrl4.sequencer.port[0] @@ -126,6 +131,7 @@ percent_source_unaligned=50 percent_uncacheable=0 progress_interval=10000 suppress_func_warnings=true +sys=system trace_addr=0 functional=system.funcmem.port[5] test=system.l1_cntrl5.sequencer.port[0] @@ -143,6 +149,7 @@ percent_source_unaligned=50 percent_uncacheable=0 progress_interval=10000 suppress_func_warnings=true +sys=system trace_addr=0 functional=system.funcmem.port[6] test=system.l1_cntrl6.sequencer.port[0] @@ -160,6 +167,7 @@ percent_source_unaligned=50 percent_uncacheable=0 progress_interval=10000 suppress_func_warnings=true +sys=system trace_addr=0 functional=system.funcmem.port[7] test=system.l1_cntrl7.sequencer.port[0] diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index 64437a4e3..e8a51599b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,26 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/12/2012 12:58:05 +Real time: Feb/12/2012 15:36:31 Profiler Stats -------------- -Elapsed_time_in_seconds: 110 -Elapsed_time_in_minutes: 1.83333 -Elapsed_time_in_hours: 0.0305556 -Elapsed_time_in_days: 0.00127315 +Elapsed_time_in_seconds: 190 +Elapsed_time_in_minutes: 3.16667 +Elapsed_time_in_hours: 0.0527778 +Elapsed_time_in_days: 0.00219907 -Virtual_time_in_seconds: 110.38 -Virtual_time_in_minutes: 1.83967 -Virtual_time_in_hours: 0.0306611 -Virtual_time_in_days: 0.00127755 +Virtual_time_in_seconds: 189.25 +Virtual_time_in_minutes: 3.15417 +Virtual_time_in_hours: 0.0525694 +Virtual_time_in_days: 0.00219039 Ruby_current_time: 22495354 Ruby_start_time: 0 Ruby_cycles: 22495354 -mbytes_resident: 41.8164 -mbytes_total: 371.512 -resident_ratio: 0.112578 +mbytes_resident: 0 +mbytes_total: 0 ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ] @@ -116,13 +115,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 3280807 average: 0.508064 | Resource Usage -------------- page_size: 4096 -user_time: 110 +user_time: 188 system_time: 0 -page_reclaims: 11719 -page_faults: 18 +page_reclaims: 12571 +page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 1 +block_outputs: 44 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index 1577dfd47..f74c8ffd6 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 12:56:01 -gem5 started Feb 12 2012 12:56:15 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Feb 12 2012 15:33:08 +gem5 started Feb 12 2012 15:33:21 +gem5 executing on Alis-MacBook-Pro.local command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index 04704faf4..1bc6a2ebb 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.022495 # Nu sim_ticks 22495354 # Number of ticks simulated final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 204320 # Simulator tick rate (ticks/s) -host_mem_usage 380432 # Number of bytes of host memory used -host_seconds 110.10 # Real time elapsed on the host +host_tick_rate 118487 # Simulator tick rate (ticks/s) +host_mem_usage 398520 # Number of bytes of host memory used +host_seconds 189.86 # Real time elapsed on the host system.physmem.bytes_read 0 # Number of bytes read from this memory system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini index ac8d82ede..1dd8fc1b6 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem system.funcmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -35,6 +42,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 suppress_func_warnings=false +sys=system trace_addr=0 functional=system.funcmem.port[0] test=system.cpu0.l1c.cpu_side @@ -50,20 +58,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=12 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -85,6 +86,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 suppress_func_warnings=false +sys=system trace_addr=0 functional=system.funcmem.port[1] test=system.cpu1.l1c.cpu_side @@ -100,20 +102,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=12 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -135,6 +130,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 suppress_func_warnings=false +sys=system trace_addr=0 functional=system.funcmem.port[2] test=system.cpu2.l1c.cpu_side @@ -150,20 +146,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=12 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -185,6 +174,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 suppress_func_warnings=false +sys=system trace_addr=0 functional=system.funcmem.port[3] test=system.cpu3.l1c.cpu_side @@ -200,20 +190,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=12 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -235,6 +218,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 suppress_func_warnings=false +sys=system trace_addr=0 functional=system.funcmem.port[4] test=system.cpu4.l1c.cpu_side @@ -250,20 +234,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=12 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -285,6 +262,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 suppress_func_warnings=false +sys=system trace_addr=0 functional=system.funcmem.port[5] test=system.cpu5.l1c.cpu_side @@ -300,20 +278,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=12 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -335,6 +306,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 suppress_func_warnings=false +sys=system trace_addr=0 functional=system.funcmem.port[6] test=system.cpu6.l1c.cpu_side @@ -350,20 +322,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=12 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -385,6 +350,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 suppress_func_warnings=false +sys=system trace_addr=0 functional=system.funcmem.port[7] test=system.cpu7.l1c.cpu_side @@ -400,20 +366,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=12 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -442,20 +401,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=8 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=65536 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index c76c33576..c89b62243 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:28 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:36 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 263488655 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 82bd7a1b0..8183eaaf7 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000263 # Nu sim_ticks 263488655 # Number of ticks simulated final_tick 263488655 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1768401 # Simulator tick rate (ticks/s) -host_mem_usage 335780 # Number of bytes of host memory used -host_seconds 149.00 # Real time elapsed on the host +host_tick_rate 1938715 # Simulator tick rate (ticks/s) +host_mem_usage 338552 # Number of bytes of host memory used +host_seconds 135.91 # Real time elapsed on the host system.physmem.bytes_read 4057580 # Number of bytes read from this memory system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory system.physmem.bytes_written 2644316 # Number of bytes written to this memory @@ -28,258 +28,289 @@ system.l2c.total_refs 139150 # To system.l2c.sampled_refs 77525 # Sample count of references to valid blocks. system.l2c.avg_refs 1.794905 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 24.077198 # Average occupied blocks per context -system.l2c.occ_blocks::1 23.899612 # Average occupied blocks per context -system.l2c.occ_blocks::2 23.566419 # Average occupied blocks per context -system.l2c.occ_blocks::3 24.461210 # Average occupied blocks per context -system.l2c.occ_blocks::4 24.025606 # Average occupied blocks per context -system.l2c.occ_blocks::5 23.167376 # Average occupied blocks per context -system.l2c.occ_blocks::6 23.494200 # Average occupied blocks per context -system.l2c.occ_blocks::7 23.002994 # Average occupied blocks per context -system.l2c.occ_blocks::8 468.019905 # Average occupied blocks per context -system.l2c.occ_percent::0 0.023513 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.023339 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.023014 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.023888 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.023463 # Average percentage of cache occupancy -system.l2c.occ_percent::5 0.022624 # Average percentage of cache occupancy -system.l2c.occ_percent::6 0.022944 # Average percentage of cache occupancy -system.l2c.occ_percent::7 0.022464 # Average percentage of cache occupancy -system.l2c.occ_percent::8 0.457051 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 10466 # number of ReadReq hits -system.l2c.ReadReq_hits::1 10370 # number of ReadReq hits -system.l2c.ReadReq_hits::2 10579 # number of ReadReq hits -system.l2c.ReadReq_hits::3 10469 # number of ReadReq hits -system.l2c.ReadReq_hits::4 10390 # number of ReadReq hits -system.l2c.ReadReq_hits::5 10384 # number of ReadReq hits -system.l2c.ReadReq_hits::6 10590 # number of ReadReq hits -system.l2c.ReadReq_hits::7 10463 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 468.019905 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 24.077198 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 23.899612 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 23.566419 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 24.461210 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 24.025606 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 23.167376 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 23.494200 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 23.002994 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.457051 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.023513 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.023339 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.023014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.023888 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.023463 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.022624 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.022944 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.022464 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.642299 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10466 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10370 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10579 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10469 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10390 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10384 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10590 # 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number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 463 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 430 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 463 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 415 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 411 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3504 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 2829 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 2819 # number of ReadExReq hits -system.l2c.ReadExReq_hits::2 2901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::3 2765 # number of ReadExReq hits -system.l2c.ReadExReq_hits::4 2827 # number of ReadExReq hits -system.l2c.ReadExReq_hits::5 2929 # number of ReadExReq hits -system.l2c.ReadExReq_hits::6 2882 # number of ReadExReq hits -system.l2c.ReadExReq_hits::7 2913 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0 2829 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 2819 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 2901 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2765 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 2827 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 2929 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 2882 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2913 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 22865 # number of ReadExReq hits -system.l2c.demand_hits::0 13295 # number of demand (read+write) hits -system.l2c.demand_hits::1 13189 # number of demand (read+write) hits -system.l2c.demand_hits::2 13480 # number of demand (read+write) hits -system.l2c.demand_hits::3 13234 # number of demand (read+write) hits -system.l2c.demand_hits::4 13217 # number of demand (read+write) hits -system.l2c.demand_hits::5 13313 # number of demand (read+write) hits -system.l2c.demand_hits::6 13472 # number of demand (read+write) hits -system.l2c.demand_hits::7 13376 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0 13295 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 13189 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 13480 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 13234 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 13217 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 13313 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 13472 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 13376 # number of demand (read+write) hits system.l2c.demand_hits::total 106576 # number of demand (read+write) hits -system.l2c.overall_hits::0 13295 # number of overall hits -system.l2c.overall_hits::1 13189 # number of overall hits -system.l2c.overall_hits::2 13480 # number of overall hits -system.l2c.overall_hits::3 13234 # number of overall hits -system.l2c.overall_hits::4 13217 # number of overall hits -system.l2c.overall_hits::5 13313 # number of overall hits -system.l2c.overall_hits::6 13472 # number of overall hits -system.l2c.overall_hits::7 13376 # number of overall hits +system.l2c.overall_hits::cpu0 13295 # number of overall hits +system.l2c.overall_hits::cpu1 13189 # number of overall hits +system.l2c.overall_hits::cpu2 13480 # number of overall hits +system.l2c.overall_hits::cpu3 13234 # number of overall hits +system.l2c.overall_hits::cpu4 13217 # number of overall hits +system.l2c.overall_hits::cpu5 13313 # number of overall hits +system.l2c.overall_hits::cpu6 13472 # number of overall hits +system.l2c.overall_hits::cpu7 13376 # number of overall hits system.l2c.overall_hits::total 106576 # number of overall hits -system.l2c.ReadReq_misses::0 5163 # number of ReadReq misses -system.l2c.ReadReq_misses::1 5186 # number of ReadReq misses -system.l2c.ReadReq_misses::2 5173 # number of ReadReq misses -system.l2c.ReadReq_misses::3 5223 # number of ReadReq misses -system.l2c.ReadReq_misses::4 5193 # number of ReadReq misses -system.l2c.ReadReq_misses::5 5114 # number of ReadReq misses -system.l2c.ReadReq_misses::6 5145 # number of ReadReq misses -system.l2c.ReadReq_misses::7 4996 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0 5163 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 5186 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 5173 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 5223 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 5193 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 5114 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 5145 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 4996 # number of ReadReq misses system.l2c.ReadReq_misses::total 41193 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1644 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 1598 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 1617 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 1610 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::4 1586 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::5 1626 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::6 1624 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::7 1582 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0 1644 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1598 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1617 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1610 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1586 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1626 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1624 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1582 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12887 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 5539 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 5808 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 5466 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 5538 # number of ReadExReq misses -system.l2c.ReadExReq_misses::4 5599 # number of ReadExReq misses -system.l2c.ReadExReq_misses::5 5507 # number of ReadExReq misses -system.l2c.ReadExReq_misses::6 5800 # number of ReadExReq misses -system.l2c.ReadExReq_misses::7 5643 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0 5539 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 5808 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 5466 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 5538 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 5599 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 5507 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 5800 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 5643 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 44900 # number of ReadExReq misses -system.l2c.demand_misses::0 10702 # number of demand (read+write) misses -system.l2c.demand_misses::1 10994 # number of demand (read+write) misses -system.l2c.demand_misses::2 10639 # number of demand (read+write) misses -system.l2c.demand_misses::3 10761 # number of demand (read+write) misses -system.l2c.demand_misses::4 10792 # number of demand (read+write) misses -system.l2c.demand_misses::5 10621 # number of demand (read+write) misses -system.l2c.demand_misses::6 10945 # number of demand (read+write) misses -system.l2c.demand_misses::7 10639 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0 10702 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 10994 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 10639 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 10761 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 10792 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 10621 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 10945 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 10639 # number of demand (read+write) misses system.l2c.demand_misses::total 86093 # number of demand (read+write) misses -system.l2c.overall_misses::0 10702 # number of overall misses -system.l2c.overall_misses::1 10994 # number of overall misses -system.l2c.overall_misses::2 10639 # number of overall misses -system.l2c.overall_misses::3 10761 # number of overall misses -system.l2c.overall_misses::4 10792 # number of overall misses -system.l2c.overall_misses::5 10621 # number of overall misses -system.l2c.overall_misses::6 10945 # number of overall misses -system.l2c.overall_misses::7 10639 # number of overall misses +system.l2c.overall_misses::cpu0 10702 # number of overall misses +system.l2c.overall_misses::cpu1 10994 # number of overall misses +system.l2c.overall_misses::cpu2 10639 # number of overall misses +system.l2c.overall_misses::cpu3 10761 # number of overall misses +system.l2c.overall_misses::cpu4 10792 # number of overall misses +system.l2c.overall_misses::cpu5 10621 # number of overall misses +system.l2c.overall_misses::cpu6 10945 # number of overall misses +system.l2c.overall_misses::cpu7 10639 # number of overall misses system.l2c.overall_misses::total 86093 # number of overall misses -system.l2c.ReadReq_miss_latency 2043791615 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 261408598 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 2236788368 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 4280579983 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 4280579983 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 15629 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 15556 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 15752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 15692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::4 15583 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::5 15498 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::6 15735 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::7 15459 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu0 256196985 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 257287128 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 256567876 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 259144977 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 257572428 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 253877351 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 255352806 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 247792064 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2043791615 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 32636387 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 33737386 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 32855972 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 32255171 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 31405634 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 33663875 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 32311068 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 32543105 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 261408598 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 275716926 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 289198618 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 271873258 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 276122659 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 279168031 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 274243794 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 289241297 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 281223785 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2236788368 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 531913911 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 546485746 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 528441134 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 535267636 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 536740459 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 528121145 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 544594103 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 529015849 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 4280579983 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 531913911 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 546485746 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 528441134 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 535267636 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 536740459 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 528121145 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 544594103 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 529015849 # number of overall miss cycles +system.l2c.overall_miss_latency::total 4280579983 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 15629 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 15556 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 15752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 15692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 15583 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 15498 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 15735 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 15459 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 124904 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 94038 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 94038 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 94038 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2101 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 2017 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 2063 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 2073 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::4 2016 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::5 2089 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::6 2039 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::7 1993 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2101 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2017 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2063 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2073 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2016 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2089 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2039 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 1993 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 16391 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 8368 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 8627 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 8367 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 8303 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::4 8426 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::5 8436 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::6 8682 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::7 8556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 8368 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 8627 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 8367 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 8303 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 8426 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 8436 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 8682 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 8556 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 67765 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 23997 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 24183 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 24119 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 23995 # number of demand (read+write) accesses -system.l2c.demand_accesses::4 24009 # number of demand (read+write) accesses -system.l2c.demand_accesses::5 23934 # number of demand (read+write) accesses -system.l2c.demand_accesses::6 24417 # number of demand (read+write) accesses -system.l2c.demand_accesses::7 24015 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0 23997 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 24183 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 24119 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 23995 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 24009 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 23934 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 24417 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 24015 # number of demand (read+write) accesses system.l2c.demand_accesses::total 192669 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 23997 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 24183 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 24119 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 23995 # number of overall (read+write) accesses -system.l2c.overall_accesses::4 24009 # number of overall (read+write) accesses -system.l2c.overall_accesses::5 23934 # number of overall (read+write) accesses -system.l2c.overall_accesses::6 24417 # number of overall (read+write) accesses -system.l2c.overall_accesses::7 24015 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0 23997 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 24183 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 24119 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 23995 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 24009 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 23934 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 24417 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 24015 # number of overall (read+write) accesses system.l2c.overall_accesses::total 192669 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.330347 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.333376 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.328403 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.332845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::4 0.333248 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::5 0.329978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::6 0.326978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::7 0.323177 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 2.638352 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.782485 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.792266 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::2 0.783810 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::3 0.776652 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::4 0.786706 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::5 0.778363 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::6 0.796469 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::7 0.793778 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 6.290529 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.661926 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.673235 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 0.653281 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 0.666988 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::4 0.664491 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::5 0.652798 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::6 0.668049 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::7 0.659537 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 5.300305 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.445972 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.454617 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.441105 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.448468 # miss rate for demand accesses -system.l2c.demand_miss_rate::4 0.449498 # miss rate for demand accesses -system.l2c.demand_miss_rate::5 0.443762 # miss rate for demand accesses -system.l2c.demand_miss_rate::6 0.448253 # miss rate for demand accesses -system.l2c.demand_miss_rate::7 0.443015 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 3.574690 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.445972 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.454617 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.441105 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.448468 # miss rate for overall accesses -system.l2c.overall_miss_rate::4 0.449498 # miss rate for overall accesses -system.l2c.overall_miss_rate::5 0.443762 # miss rate for overall accesses -system.l2c.overall_miss_rate::6 0.448253 # miss rate for overall accesses -system.l2c.overall_miss_rate::7 0.443015 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 3.574690 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 395853.498935 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 394097.881797 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 395088.268896 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 391306.072181 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::4 393566.650298 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::5 399646.385413 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::6 397238.409135 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::7 409085.591473 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 3175882.758128 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 159007.663017 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 163584.854819 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 161662.707483 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 162365.588820 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::4 164822.571248 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::5 160767.895449 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::6 160965.885468 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::7 165239.316056 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1298416.482359 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 403825.305651 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 385121.964187 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 409218.508599 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 403898.224630 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::4 399497.833184 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::5 406171.848193 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::6 385653.166897 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::7 396382.840333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 3189769.691674 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 399979.441506 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 389356.010824 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 402347.963436 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 397786.449494 # average overall miss latency -system.l2c.demand_avg_miss_latency::4 396643.808655 # average overall miss latency -system.l2c.demand_avg_miss_latency::5 403029.844930 # average overall miss latency -system.l2c.demand_avg_miss_latency::6 391099.130471 # average overall miss latency -system.l2c.demand_avg_miss_latency::7 402347.963436 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3182590.612752 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 399979.441506 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 389356.010824 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 402347.963436 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 397786.449494 # average overall miss latency -system.l2c.overall_avg_miss_latency::4 396643.808655 # average overall miss latency -system.l2c.overall_avg_miss_latency::5 403029.844930 # average overall miss latency -system.l2c.overall_avg_miss_latency::6 391099.130471 # average overall miss latency -system.l2c.overall_avg_miss_latency::7 402347.963436 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3182590.612752 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0 0.330347 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.333376 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.328403 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.332845 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.333248 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.329978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.326978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.323177 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.782485 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.792266 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.783810 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.776652 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.786706 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.778363 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.796469 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.793778 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.661926 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.673235 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.653281 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.666988 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.664491 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.652798 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.668049 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.659537 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.445972 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.454617 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.441105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.448468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.449498 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.443762 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.448253 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.443015 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.445972 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.454617 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.441105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.448468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.449498 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.443762 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.448253 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.443015 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 49611.864250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 49597.501643 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 49616.116600 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 49599.928365 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 49643.596206 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 49631.254810 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 49598.091273 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 20319.092146 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 20034.267702 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 19801.786885 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 20703.490160 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 19895.977833 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 20570.862832 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 49777.383282 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 49793.150482 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 49738.978778 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 49859.635067 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 49860.337739 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 49799.127293 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 49869.189138 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 49835.864788 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 49702.290320 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 49707.635619 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 49670.188364 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 49741.440015 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 49735.031412 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 49724.239243 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 49757.341526 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 49724.208008 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 49702.290320 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 49707.635619 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 49670.188364 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 49741.440015 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 49735.031412 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 49724.239243 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 49757.341526 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 49724.208008 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked @@ -288,119 +319,327 @@ system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 40644 # number of writebacks -system.l2c.ReadReq_mshr_hits 961 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits 49 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits 507 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits 1468 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 1468 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 40232 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 12838 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 44393 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 84625 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 84625 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1609227416 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 513507057 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 1775748338 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 3384975754 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 3384975754 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 3189139994 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1723903484 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 4913043478 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 2.574189 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.586269 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 2.554088 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 2.563854 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::4 2.581788 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::5 2.595948 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::6 2.556848 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::7 2.602497 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 20.615481 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 6.110424 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 6.364898 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 6.222976 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 6.192957 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::4 6.368056 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::5 6.145524 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::6 6.296224 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::7 6.441545 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 50.142604 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 5.305091 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 5.145821 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 5.305725 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 5.346622 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::4 5.268573 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::5 5.262328 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::6 5.113223 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::7 5.188523 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 41.935906 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 3.526482 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 3.499359 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 3.508645 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 3.526776 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::4 3.524720 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::5 3.535765 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::6 3.465823 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::7 3.523839 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 28.111410 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 3.526482 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 3.499359 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 3.508645 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 3.526776 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::4 3.524720 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::5 3.535765 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::6 3.465823 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::7 3.523839 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 28.111410 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 39998.692981 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 39998.991821 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40000.638344 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 39999.713489 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 39999.713489 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 40644 # number of writebacks +system.l2c.writebacks::total 40644 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 118 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 121 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 142 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 119 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 123 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 404102628 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 391101960 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 403583386 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3189139994 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 215688086 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 217048117 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 213007261 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 216128145 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 218848364 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 214487951 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 216767566 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 211927994 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1723903484 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 616110431 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 608109604 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 614510151 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 612749972 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 619591835 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 618590579 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 607869526 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 615511380 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4913043478 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.322797 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.325598 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.319388 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.325261 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.325355 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.322622 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.319987 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.315803 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.779153 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.788299 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.781386 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.773275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.783730 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.775969 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.794017 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.790768 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.653800 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.664889 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.644556 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.661327 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.657963 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.644263 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.661368 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.652291 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.441550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.442084 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.441550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.442084 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40002.870565 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40002.812241 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40002.878951 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40002.595611 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 39994.796252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.304600 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 39986.772989 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39994.349857 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40002.238852 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39976.872327 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40002.032258 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40001.814722 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40002.012025 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40002.360888 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40002.153799 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40002.212563 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40002.446171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39995.372559 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39994.920452 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40002.626298 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40002.443543 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40002.523827 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40002.451411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 40002.352804 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.611515 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 39998.790654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.611515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 39998.790654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.num_reads 99815 # number of read accesses completed system.cpu0.num_writes 53929 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed system.cpu0.l1c.replacements 27826 # number of replacements -system.cpu0.l1c.tagsinuse 102.742005 # Cycle average of tags in use +system.cpu0.l1c.tagsinuse 347.331950 # Cycle average of tags in use system.cpu0.l1c.total_refs 11604 # Total number of references to valid blocks. system.cpu0.l1c.sampled_refs 28187 # Sample count of references to valid blocks. system.cpu0.l1c.avg_refs 0.411679 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::0 347.331950 # Average occupied blocks per context -system.cpu0.l1c.occ_blocks::1 -244.589945 # Average occupied blocks per context -system.cpu0.l1c.occ_percent::0 0.678383 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::1 -0.477715 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits 7530 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits 1059 # number of WriteReq hits -system.cpu0.l1c.demand_hits 8589 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits 8589 # number of overall hits -system.cpu0.l1c.ReadReq_misses 37279 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses 23202 # number of WriteReq misses -system.cpu0.l1c.demand_misses 60481 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses 60481 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency 1299667421 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency 1001508092 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency 2301175513 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency 2301175513 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses 44809 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses 24261 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses 69070 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses 69070 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate 0.831953 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate 0.956350 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate 0.875648 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate 0.875648 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency 34863.258698 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency 43164.731144 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency 38047.907822 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency 38047.907822 # average overall miss latency +system.cpu0.l1c.occ_blocks::cpu0 347.331950 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.678383 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.678383 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 7530 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 7530 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1059 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1059 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 8589 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 8589 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 8589 # number of overall hits +system.cpu0.l1c.overall_hits::total 8589 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 37279 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 37279 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23202 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23202 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60481 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60481 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60481 # number of overall misses +system.cpu0.l1c.overall_misses::total 60481 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1299667421 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1299667421 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1001508092 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1001508092 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2301175513 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2301175513 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2301175513 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2301175513 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44809 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44809 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24261 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 69070 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 69070 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 69070 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 69070 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.831953 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956350 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.875648 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.875648 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 34863.258698 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 43164.731144 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 38047.907822 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822 # average overall miss latency system.cpu0.l1c.blocked_cycles::no_mshrs 253845135 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.blocked::no_mshrs 69110 # number of cycles access was blocked @@ -409,72 +648,94 @@ system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3673.059398 system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks 11972 # number of writebacks -system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.ReadReq_mshr_misses 37279 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses 23202 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses 60481 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses 60481 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 1262244251 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency 978215253 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency 2240459504 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency 2240459504 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 894578632 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 569723237 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency 1464301869 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.831953 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.956350 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate 0.875648 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate 0.875648 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33859.391373 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 42160.816007 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 37044.022156 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 37044.022156 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.l1c.writebacks::writebacks 11972 # number of writebacks +system.cpu0.l1c.writebacks::total 11972 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 37279 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 37279 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23202 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23202 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60481 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60481 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60481 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60481 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1262244251 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1262244251 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 978215253 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 978215253 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2240459504 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2240459504 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2240459504 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2240459504 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 894578632 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 894578632 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 569723237 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 569723237 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1464301869 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1464301869 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.831953 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956350 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 33859.391373 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 42160.816007 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.num_reads 98493 # number of read accesses completed system.cpu1.num_writes 53671 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed system.cpu1.l1c.replacements 27684 # number of replacements -system.cpu1.l1c.tagsinuse 93.018974 # Cycle average of tags in use +system.cpu1.l1c.tagsinuse 345.656340 # Cycle average of tags in use system.cpu1.l1c.total_refs 11419 # Total number of references to valid blocks. system.cpu1.l1c.sampled_refs 28039 # Sample count of references to valid blocks. system.cpu1.l1c.avg_refs 0.407254 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::0 345.656340 # Average occupied blocks per context -system.cpu1.l1c.occ_blocks::1 -252.637366 # Average occupied blocks per context -system.cpu1.l1c.occ_percent::0 0.675110 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::1 -0.493432 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits 7429 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits 1066 # number of WriteReq hits -system.cpu1.l1c.demand_hits 8495 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits 8495 # number of overall hits -system.cpu1.l1c.ReadReq_misses 37110 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses 23275 # number of WriteReq misses -system.cpu1.l1c.demand_misses 60385 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses 60385 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency 1301760811 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency 1014297005 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency 2316057816 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency 2316057816 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses 44539 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses 24341 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses 68880 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses 68880 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate 0.833202 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate 0.956206 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate 0.876670 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate 0.876670 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency 35078.437375 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency 43578.818690 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency 38354.853291 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency 38354.853291 # average overall miss latency +system.cpu1.l1c.occ_blocks::cpu1 345.656340 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.675110 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.675110 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 7429 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 7429 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1066 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1066 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 8495 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 8495 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 8495 # number of overall hits +system.cpu1.l1c.overall_hits::total 8495 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 37110 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 37110 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23275 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23275 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60385 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60385 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60385 # number of overall misses +system.cpu1.l1c.overall_misses::total 60385 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1301760811 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1301760811 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1014297005 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1014297005 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2316057816 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2316057816 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2316057816 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2316057816 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44539 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44539 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24341 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24341 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68880 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68880 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68880 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68880 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.833202 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956206 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.876670 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.876670 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291 # average overall miss latency system.cpu1.l1c.blocked_cycles::no_mshrs 253325402 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.blocked::no_mshrs 68822 # number of cycles access was blocked @@ -483,72 +744,94 @@ system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3680.878237 system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks 11809 # number of writebacks -system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.ReadReq_mshr_misses 37110 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses 23275 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses 60385 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses 60385 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 1264508347 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency 990933889 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency 2255442236 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency 2255442236 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 877119159 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 578327433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency 1455446592 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833202 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.956206 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate 0.876670 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate 0.876670 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34074.598410 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 42575.032825 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 37351.034793 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.l1c.writebacks::writebacks 11809 # number of writebacks +system.cpu1.l1c.writebacks::total 11809 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 37110 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 37110 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23275 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23275 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60385 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60385 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60385 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60385 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1264508347 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1264508347 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 990933889 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 990933889 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2255442236 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2255442236 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2255442236 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2255442236 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 877119159 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 877119159 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 578327433 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 578327433 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1455446592 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1455446592 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.833202 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956206 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.num_reads 99149 # number of read accesses completed system.cpu2.num_writes 53185 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed system.cpu2.l1c.replacements 27627 # number of replacements -system.cpu2.l1c.tagsinuse 84.373112 # Cycle average of tags in use +system.cpu2.l1c.tagsinuse 345.430231 # Cycle average of tags in use system.cpu2.l1c.total_refs 11519 # Total number of references to valid blocks. system.cpu2.l1c.sampled_refs 27982 # Sample count of references to valid blocks. system.cpu2.l1c.avg_refs 0.411657 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::0 345.430231 # Average occupied blocks per context -system.cpu2.l1c.occ_blocks::1 -261.057119 # Average occupied blocks per context -system.cpu2.l1c.occ_percent::0 0.674668 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::1 -0.509877 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits 7576 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits 1069 # number of WriteReq hits -system.cpu2.l1c.demand_hits 8645 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits 8645 # number of overall hits -system.cpu2.l1c.ReadReq_misses 37144 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses 22885 # number of WriteReq misses -system.cpu2.l1c.demand_misses 60029 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses 60029 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency 1302790562 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency 991654869 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency 2294445431 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency 2294445431 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses 44720 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses 23954 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses 68674 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses 68674 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate 0.830590 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate 0.955373 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate 0.874115 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate 0.874115 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency 35074.051314 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency 43332.089535 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency 38222.283080 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency 38222.283080 # average overall miss latency +system.cpu2.l1c.occ_blocks::cpu2 345.430231 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.674668 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.674668 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 7576 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 7576 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1069 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1069 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 8645 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 8645 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 8645 # number of overall hits +system.cpu2.l1c.overall_hits::total 8645 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 37144 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 37144 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22885 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22885 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60029 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60029 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60029 # number of overall misses +system.cpu2.l1c.overall_misses::total 60029 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1302790562 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1302790562 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 991654869 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 991654869 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2294445431 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2294445431 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2294445431 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2294445431 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44720 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44720 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23954 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23954 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68674 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68674 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68674 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68674 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.830590 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955373 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.874115 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.874115 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 38222.283080 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080 # average overall miss latency system.cpu2.l1c.blocked_cycles::no_mshrs 254303447 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.blocked::no_mshrs 68698 # number of cycles access was blocked @@ -557,72 +840,94 @@ system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3701.759105 system.cpu2.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks 11784 # number of writebacks -system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.ReadReq_mshr_misses 37144 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses 22885 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses 60029 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses 60029 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 1265501937 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency 968684322 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency 2234186259 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency 2234186259 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 900513056 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 566349170 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency 1466862226 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.830590 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.955373 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate 0.874115 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate 0.874115 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34070.157684 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 42328.351409 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 37218.448733 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 37218.448733 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.l1c.writebacks::writebacks 11784 # number of writebacks +system.cpu2.l1c.writebacks::total 11784 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 37144 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 37144 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22885 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22885 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60029 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60029 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60029 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60029 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1265501937 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1265501937 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 968684322 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 968684322 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2234186259 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2234186259 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2234186259 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2234186259 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 900513056 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 900513056 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 566349170 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 566349170 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1466862226 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1466862226 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.830590 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955373 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.num_reads 99588 # number of read accesses completed system.cpu3.num_writes 53645 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed system.cpu3.l1c.replacements 27837 # number of replacements -system.cpu3.l1c.tagsinuse 104.177298 # Cycle average of tags in use +system.cpu3.l1c.tagsinuse 347.574885 # Cycle average of tags in use system.cpu3.l1c.total_refs 11563 # Total number of references to valid blocks. system.cpu3.l1c.sampled_refs 28190 # Sample count of references to valid blocks. system.cpu3.l1c.avg_refs 0.410181 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::0 347.574885 # Average occupied blocks per context -system.cpu3.l1c.occ_blocks::1 -243.397586 # Average occupied blocks per context -system.cpu3.l1c.occ_percent::0 0.678857 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::1 -0.475386 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits 7552 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits 1078 # number of WriteReq hits -system.cpu3.l1c.demand_hits 8630 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits 8630 # number of overall hits -system.cpu3.l1c.ReadReq_misses 37191 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses 23219 # number of WriteReq misses -system.cpu3.l1c.demand_misses 60410 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses 60410 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency 1312024933 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency 995527685 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency 2307552618 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency 2307552618 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses 44743 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses 24297 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses 69040 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses 69040 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate 0.831214 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate 0.955632 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate 0.875000 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate 0.875000 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency 35278.022452 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency 42875.562470 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency 38198.189340 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency 38198.189340 # average overall miss latency +system.cpu3.l1c.occ_blocks::cpu3 347.574885 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.678857 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.678857 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 7552 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 7552 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1078 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1078 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 8630 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 8630 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 8630 # number of overall hits +system.cpu3.l1c.overall_hits::total 8630 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 37191 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 37191 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23219 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23219 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60410 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60410 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60410 # number of overall misses +system.cpu3.l1c.overall_misses::total 60410 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1312024933 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1312024933 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 995527685 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 995527685 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2307552618 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2307552618 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2307552618 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2307552618 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44743 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44743 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24297 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24297 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 69040 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 69040 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 69040 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 69040 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.831214 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955632 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.875000 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.875000 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 35278.022452 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 42875.562470 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 38198.189340 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 38198.189340 # average overall miss latency system.cpu3.l1c.blocked_cycles::no_mshrs 254462667 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.blocked::no_mshrs 68939 # number of cycles access was blocked @@ -631,72 +936,94 @@ system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3691.127910 system.cpu3.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks 11956 # number of writebacks -system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses 23219 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses 60410 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses 60410 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 1274692143 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency 972218785 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency 2246910928 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency 2246910928 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 889431937 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 569772276 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency 1459204213 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.831214 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.955632 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate 0.875000 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate 0.875000 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34274.209970 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 41871.690641 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 37194.354047 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 37194.354047 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.l1c.writebacks::writebacks 11956 # number of writebacks +system.cpu3.l1c.writebacks::total 11956 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 37191 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 37191 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23219 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23219 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60410 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60410 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60410 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60410 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1274692143 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1274692143 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 972218785 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 972218785 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2246910928 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2246910928 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2246910928 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2246910928 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 889431937 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 889431937 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 569772276 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 569772276 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1459204213 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1459204213 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.831214 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955632 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34274.209970 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 41871.690641 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu4.num_reads 99725 # number of read accesses completed system.cpu4.num_writes 53533 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed system.cpu4.l1c.replacements 27683 # number of replacements -system.cpu4.l1c.tagsinuse 94.681644 # Cycle average of tags in use +system.cpu4.l1c.tagsinuse 347.631602 # Cycle average of tags in use system.cpu4.l1c.total_refs 11724 # Total number of references to valid blocks. system.cpu4.l1c.sampled_refs 28041 # Sample count of references to valid blocks. system.cpu4.l1c.avg_refs 0.418102 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::0 347.631602 # Average occupied blocks per context -system.cpu4.l1c.occ_blocks::1 -252.949959 # Average occupied blocks per context -system.cpu4.l1c.occ_percent::0 0.678968 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::1 -0.494043 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits 7686 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits 1123 # number of WriteReq hits -system.cpu4.l1c.demand_hits 8809 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits 8809 # number of overall hits -system.cpu4.l1c.ReadReq_misses 37251 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses 22937 # number of WriteReq misses -system.cpu4.l1c.demand_misses 60188 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses 60188 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency 1303112178 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency 994450363 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency 2297562541 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency 2297562541 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses 44937 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses 24060 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses 68997 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses 68997 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate 0.828961 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate 0.953325 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate 0.872328 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate 0.872328 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency 34981.938149 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency 43355.729302 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency 38173.099970 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency 38173.099970 # average overall miss latency +system.cpu4.l1c.occ_blocks::cpu4 347.631602 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.678968 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.678968 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 7686 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 7686 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1123 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1123 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 8809 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 8809 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 8809 # number of overall hits +system.cpu4.l1c.overall_hits::total 8809 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 37251 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 37251 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22937 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22937 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60188 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60188 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60188 # number of overall misses +system.cpu4.l1c.overall_misses::total 60188 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1303112178 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1303112178 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 994450363 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 994450363 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2297562541 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2297562541 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2297562541 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2297562541 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44937 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44937 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24060 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24060 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68997 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68997 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68997 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68997 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.828961 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953325 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.872328 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.872328 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 34981.938149 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 43355.729302 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 38173.099970 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 38173.099970 # average overall miss latency system.cpu4.l1c.blocked_cycles::no_mshrs 254136532 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.blocked::no_mshrs 68868 # number of cycles access was blocked @@ -705,72 +1032,94 @@ system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3690.197653 system.cpu4.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks 11763 # number of writebacks -system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.ReadReq_mshr_misses 37251 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses 22937 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses 60188 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses 60188 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 1265717116 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency 971425596 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency 2237142712 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency 2237142712 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 898461911 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 576408625 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency 1474870536 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.828961 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.953325 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate 0.872328 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate 0.872328 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 33978.070817 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 42351.902864 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 37169.248222 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 37169.248222 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu4.l1c.writebacks::writebacks 11763 # number of writebacks +system.cpu4.l1c.writebacks::total 11763 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 37251 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 37251 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22937 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22937 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60188 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60188 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60188 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60188 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1265717116 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1265717116 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 971425596 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 971425596 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2237142712 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2237142712 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2237142712 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2237142712 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 898461911 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 898461911 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 576408625 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 576408625 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1474870536 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1474870536 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.828961 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953325 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 33978.070817 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 42351.902864 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu5.num_reads 100000 # number of read accesses completed system.cpu5.num_writes 53710 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed system.cpu5.l1c.replacements 27832 # number of replacements -system.cpu5.l1c.tagsinuse 93.507234 # Cycle average of tags in use +system.cpu5.l1c.tagsinuse 346.806811 # Cycle average of tags in use system.cpu5.l1c.total_refs 11748 # Total number of references to valid blocks. system.cpu5.l1c.sampled_refs 28191 # Sample count of references to valid blocks. system.cpu5.l1c.avg_refs 0.416729 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::0 346.806811 # Average occupied blocks per context -system.cpu5.l1c.occ_blocks::1 -253.299577 # Average occupied blocks per context -system.cpu5.l1c.occ_percent::0 0.677357 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::1 -0.494726 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits 7592 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits 1126 # number of WriteReq hits -system.cpu5.l1c.demand_hits 8718 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits 8718 # number of overall hits -system.cpu5.l1c.ReadReq_misses 37349 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses 23013 # number of WriteReq misses -system.cpu5.l1c.demand_misses 60362 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses 60362 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency 1291933371 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency 998304045 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency 2290237416 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency 2290237416 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses 44941 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses 24139 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses 69080 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses 69080 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate 0.831067 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate 0.953353 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate 0.873798 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate 0.873798 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency 34590.842352 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency 43380.004563 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency 37941.708625 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency 37941.708625 # average overall miss latency +system.cpu5.l1c.occ_blocks::cpu5 346.806811 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.677357 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.677357 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 7592 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 7592 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1126 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1126 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 8718 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 8718 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 8718 # number of overall hits +system.cpu5.l1c.overall_hits::total 8718 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 37349 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 37349 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23013 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23013 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60362 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60362 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60362 # number of overall misses +system.cpu5.l1c.overall_misses::total 60362 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1291933371 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1291933371 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 998304045 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 998304045 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2290237416 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2290237416 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2290237416 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2290237416 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44941 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44941 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24139 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24139 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69080 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69080 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69080 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69080 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.831067 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953353 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.873798 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.873798 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 37941.708625 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625 # average overall miss latency system.cpu5.l1c.blocked_cycles::no_mshrs 253381114 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.blocked::no_mshrs 68969 # number of cycles access was blocked @@ -779,72 +1128,94 @@ system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3673.840624 system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks 11908 # number of writebacks -system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.ReadReq_mshr_misses 37349 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses 23013 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses 60362 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses 60362 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 1254436910 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency 975203983 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency 2229640893 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency 2229640893 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 902856034 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 567587171 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency 1470443205 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831067 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.953353 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate 0.873798 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate 0.873798 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33586.894160 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 42376.221397 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 36937.823349 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 36937.823349 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu5.l1c.writebacks::writebacks 11908 # number of writebacks +system.cpu5.l1c.writebacks::total 11908 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 37349 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 37349 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23013 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23013 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60362 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60362 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60362 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60362 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1254436910 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1254436910 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 975203983 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 975203983 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2229640893 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2229640893 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2229640893 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2229640893 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 902856034 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 902856034 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 567587171 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567587171 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1470443205 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1470443205 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.831067 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953353 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 33586.894160 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 42376.221397 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu6.num_reads 99389 # number of read accesses completed system.cpu6.num_writes 53686 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed system.cpu6.l1c.replacements 27861 # number of replacements -system.cpu6.l1c.tagsinuse 89.788098 # Cycle average of tags in use +system.cpu6.l1c.tagsinuse 347.289326 # Cycle average of tags in use system.cpu6.l1c.total_refs 11520 # Total number of references to valid blocks. system.cpu6.l1c.sampled_refs 28198 # Sample count of references to valid blocks. system.cpu6.l1c.avg_refs 0.408540 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::0 347.289326 # Average occupied blocks per context -system.cpu6.l1c.occ_blocks::1 -257.501227 # Average occupied blocks per context -system.cpu6.l1c.occ_percent::0 0.678299 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::1 -0.502932 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits 7543 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits 1119 # number of WriteReq hits -system.cpu6.l1c.demand_hits 8662 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits 8662 # number of overall hits -system.cpu6.l1c.ReadReq_misses 37109 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses 23142 # number of WriteReq misses -system.cpu6.l1c.demand_misses 60251 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses 60251 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency 1299799162 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency 1015775810 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency 2315574972 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency 2315574972 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses 44652 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses 24261 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses 68913 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses 68913 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate 0.831071 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate 0.953877 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate 0.874305 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate 0.874305 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency 35026.520844 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency 43893.173019 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency 38432.141740 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency 38432.141740 # average overall miss latency +system.cpu6.l1c.occ_blocks::cpu6 347.289326 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.678299 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.678299 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 7543 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 7543 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1119 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1119 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 8662 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 8662 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 8662 # number of overall hits +system.cpu6.l1c.overall_hits::total 8662 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 37109 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 37109 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23142 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23142 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60251 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60251 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60251 # number of overall misses +system.cpu6.l1c.overall_misses::total 60251 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1299799162 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1299799162 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1015775810 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1015775810 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2315574972 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2315574972 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2315574972 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2315574972 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44652 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44652 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24261 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68913 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68913 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68913 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68913 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.831071 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953877 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.874305 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.874305 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740 # average overall miss latency system.cpu6.l1c.blocked_cycles::no_mshrs 253794713 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.blocked::no_mshrs 68612 # number of cycles access was blocked @@ -853,72 +1224,94 @@ system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3698.984332 system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks 11849 # number of writebacks -system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.ReadReq_mshr_misses 37109 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses 23142 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses 60251 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses 60251 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 1262548698 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency 992541214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency 2255089912 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency 2255089912 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 877981455 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 574689009 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency 1452670464 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.831071 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.953877 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate 0.874305 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate 0.874305 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34022.708723 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 42889.171809 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 37428.256992 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu6.l1c.writebacks::writebacks 11849 # number of writebacks +system.cpu6.l1c.writebacks::total 11849 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 37109 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 37109 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23142 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23142 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60251 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60251 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60251 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60251 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1262548698 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262548698 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 992541214 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 992541214 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2255089912 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2255089912 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2255089912 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2255089912 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 877981455 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 877981455 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 574689009 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 574689009 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1452670464 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1452670464 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.831071 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953877 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu7.num_reads 99694 # number of read accesses completed system.cpu7.num_writes 53501 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed system.cpu7.l1c.replacements 27727 # number of replacements -system.cpu7.l1c.tagsinuse 84.250612 # Cycle average of tags in use +system.cpu7.l1c.tagsinuse 346.094259 # Cycle average of tags in use system.cpu7.l1c.total_refs 11534 # Total number of references to valid blocks. system.cpu7.l1c.sampled_refs 28062 # Sample count of references to valid blocks. system.cpu7.l1c.avg_refs 0.411018 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::0 346.094259 # Average occupied blocks per context -system.cpu7.l1c.occ_blocks::1 -261.843648 # Average occupied blocks per context -system.cpu7.l1c.occ_percent::0 0.675965 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::1 -0.511413 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits 7593 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits 1111 # number of WriteReq hits -system.cpu7.l1c.demand_hits 8704 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits 8704 # number of overall hits -system.cpu7.l1c.ReadReq_misses 37155 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses 23121 # number of WriteReq misses -system.cpu7.l1c.demand_misses 60276 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses 60276 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency 1287127315 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency 1006139538 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency 2293266853 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency 2293266853 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses 44748 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses 24232 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses 68980 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses 68980 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate 0.830316 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate 0.954152 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate 0.873818 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate 0.873818 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency 34642.102409 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency 43516.263916 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency 38046.102147 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency 38046.102147 # average overall miss latency +system.cpu7.l1c.occ_blocks::cpu7 346.094259 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.675965 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.675965 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 7593 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 7593 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1111 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1111 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 8704 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 8704 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 8704 # number of overall hits +system.cpu7.l1c.overall_hits::total 8704 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 37155 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 37155 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23121 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23121 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60276 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60276 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60276 # number of overall misses +system.cpu7.l1c.overall_misses::total 60276 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1287127315 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1287127315 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1006139538 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1006139538 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2293266853 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2293266853 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2293266853 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2293266853 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44748 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44748 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24232 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24232 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68980 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68980 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68980 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68980 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.830316 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954152 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.873818 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.873818 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147 # average overall miss latency system.cpu7.l1c.blocked_cycles::no_mshrs 254008986 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.blocked::no_mshrs 69036 # number of cycles access was blocked @@ -927,34 +1320,41 @@ system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3679.369981 system.cpu7.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks 11797 # number of writebacks -system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.ReadReq_mshr_misses 37155 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses 23121 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses 60276 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses 60276 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 1249829653 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency 982928032 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency 2232757685 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency 2232757685 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 901961636 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 558194703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency 1460156339 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830316 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.954152 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate 0.873818 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate 0.873818 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33638.262764 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 42512.349466 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 37042.233808 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu7.l1c.writebacks::writebacks 11797 # number of writebacks +system.cpu7.l1c.writebacks::total 11797 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 37155 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 37155 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23121 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23121 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60276 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60276 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60276 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60276 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1249829653 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1249829653 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 982928032 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 982928032 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2232757685 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2232757685 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2232757685 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2232757685 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 901961636 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 901961636 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 558194703 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 558194703 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1460156339 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1460156339 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.830316 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954152 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini index bb6d59ead..b16ace9ba 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini @@ -282,6 +282,7 @@ type=RubyTester check_flush=false checks_to_complete=100 deadlock_threshold=50000 +system=system wakeup_frequency=10 cpuPort=system.l1_cntrl0.sequencer.port[0] diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats index df1c9f71b..31ca83263 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,26 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/12/2012 12:56:15 +Real time: Feb/12/2012 15:33:22 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.46 -Virtual_time_in_minutes: 0.00766667 -Virtual_time_in_hours: 0.000127778 -Virtual_time_in_days: 5.32407e-06 +Virtual_time_in_seconds: 0.95 +Virtual_time_in_minutes: 0.0158333 +Virtual_time_in_hours: 0.000263889 +Virtual_time_in_days: 1.09954e-05 Ruby_current_time: 366301 Ruby_start_time: 0 Ruby_cycles: 366301 -mbytes_resident: 39.4219 -mbytes_total: 241.242 -resident_ratio: 0.163461 +mbytes_resident: 0 +mbytes_total: 0 ruby_cycles_executed: [ 366302 ] @@ -119,11 +118,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11076 -page_faults: 18 +page_reclaims: 11904 +page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 4 +block_outputs: 5 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout index f8914feae..865d6a91e 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 12:56:01 -gem5 started Feb 12 2012 12:56:15 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Feb 12 2012 15:33:08 +gem5 started Feb 12 2012 15:33:21 +gem5 executing on Alis-MacBook-Pro.local command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index 134ffa963..3c5f9984c 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000366 # Nu sim_ticks 366301 # Number of ticks simulated final_tick 366301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1737283 # Simulator tick rate (ticks/s) -host_mem_usage 247036 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 728650 # Simulator tick rate (ticks/s) +host_mem_usage 266424 # Number of bytes of host memory used +host_seconds 0.50 # Real time elapsed on the host system.physmem.bytes_read 0 # Number of bytes read from this memory system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory |