diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:39 -0400 |
| commit | 80cd107e51ceb5aac262ec7dd82870e48d345b43 (patch) | |
| tree | 4bb545ae29522161963a8028f34ca850c98a3403 /tests/quick/se | |
| parent | 2847d5f5177304236dcdbab112a0369f0bd96aea (diff) | |
| download | gem5-80cd107e51ceb5aac262ec7dd82870e48d345b43.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/quick/se')
20 files changed, 3610 insertions, 3499 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 0b52af291..6403398b5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -744,17 +744,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 94ce3d081..725976bdf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17398000 # Number of ticks simulated final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32773 # Simulator instruction rate (inst/s) -host_op_rate 38377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 124135140 # Simulator tick rate (ticks/s) -host_mem_usage 303432 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 57922 # Simulator instruction rate (inst/s) +host_op_rate 67825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219380871 # Simulator tick rate (ticks/s) +host_mem_usage 310080 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1162,19 +1162,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index a58641eea..835d1798d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1074,17 +1074,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 64 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.127237 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 439 87.28% 87.28% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 64 12.72% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 5334b6829..e88fbd103 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88081 # Simulator instruction rate (inst/s) -host_op_rate 103121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51657705 # Simulator tick rate (ticks/s) -host_mem_usage 292672 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 803078 # Simulator instruction rate (inst/s) +host_op_rate 938405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 469266934 # Simulator tick rate (ticks/s) +host_mem_usage 299548 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -347,16 +347,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram +system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram +system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index cc40f6f8e..d7a1f965a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99386 # Simulator instruction rate (inst/s) -host_op_rate 116351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58281162 # Simulator tick rate (ticks/s) -host_mem_usage 291652 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 829930 # Simulator instruction rate (inst/s) +host_op_rate 969708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 484799424 # Simulator tick rate (ticks/s) +host_mem_usage 298800 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -228,16 +228,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram +system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram +system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 578791a49..eccfa92c7 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -549,17 +549,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index ab4491575..66fb99cb1 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -896,17 +896,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 3bcc97a18..decb816ca 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 365210 # Simulator instruction rate (inst/s) -host_op_rate 661016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 380445830 # Simulator tick rate (ticks/s) -host_mem_usage 292780 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 96804 # Simulator instruction rate (inst/s) +host_op_rate 175298 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 100934348 # Simulator tick rate (ticks/s) +host_mem_usage 242164 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 1266607302 # Wr system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 7917 # Transaction distribution -system.membus.trans_dist::ReadResp 7917 # Transaction distribution -system.membus.trans_dist::WriteReq 935 # Transaction distribution -system.membus.trans_dist::WriteResp 935 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 8852 # Request fanout histogram -system.membus.snoop_fanout::mean 2.775418 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1988 22.46% 22.46% # Request fanout histogram -system.membus.snoop_fanout::3 6864 77.54% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 8852 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.membus.trans_dist::ReadReq 7917 # Transaction distribution +system.membus.trans_dist::ReadResp 7917 # Transaction distribution +system.membus.trans_dist::WriteReq 935 # Transaction distribution +system.membus.trans_dist::WriteResp 935 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 8852 # Request fanout histogram +system.membus.snoop_fanout::mean 0.775418 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1988 22.46% 22.46% # Request fanout histogram +system.membus.snoop_fanout::1 6864 77.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 8852 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 2ef89d07d..5185b356a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358500 # Number of ticks simulated final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 312703 # Simulator instruction rate (inst/s) -host_op_rate 566020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1645401799 # Simulator tick rate (ticks/s) -host_mem_usage 307640 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 97635 # Simulator instruction rate (inst/s) +host_op_rate 176805 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 514168344 # Simulator tick rate (ticks/s) +host_mem_usage 251928 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -423,17 +423,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index cffe156e4..5787f53df 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000500 # Number of ticks simulated final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1362402 # Simulator instruction rate (inst/s) -host_op_rate 1369187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 814125846 # Simulator tick rate (ticks/s) -host_mem_usage 428768 # Number of bytes of host memory used -host_seconds 66.50 # Real time elapsed on the host +host_inst_rate 1892320 # Simulator instruction rate (inst/s) +host_op_rate 1901744 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1130787212 # Simulator tick rate (ticks/s) +host_mem_usage 435148 # Number of bytes of host memory used +host_seconds 47.88 # Real time elapsed on the host sim_insts 90602408 # Number of instructions simulated sim_ops 91053639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 135031171 # Request fanout histogram -system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram +system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::3 107830771 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 135031171 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index c88ed3ac4..fd1fa8729 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -589,17 +589,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 844bb352a..c6a32009b 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1180838 # Simulator instruction rate (inst/s) -host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1262766288 # Simulator tick rate (ticks/s) -host_mem_usage 436624 # Number of bytes of host memory used -host_seconds 133.79 # Real time elapsed on the host +host_inst_rate 1204419 # Simulator instruction rate (inst/s) +host_op_rate 2120788 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1287982979 # Simulator tick rate (ticks/s) +host_mem_usage 383444 # Number of bytes of host memory used +host_seconds 131.17 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 1439319677 # Wr system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 308475611 # Transaction distribution -system.membus.trans_dist::ReadResp 308475611 # Transaction distribution -system.membus.trans_dist::WriteReq 31439752 # Transaction distribution -system.membus.trans_dist::WriteResp 31439752 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 339915363 # Request fanout histogram -system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram -system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 339915363 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.membus.trans_dist::ReadReq 308475611 # Transaction distribution +system.membus.trans_dist::ReadResp 308475611 # Transaction distribution +system.membus.trans_dist::WriteReq 31439752 # Transaction distribution +system.membus.trans_dist::WriteResp 31439752 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 339915363 # Request fanout histogram +system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram +system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 339915363 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 1b6566181..c01cc2902 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1735 +1,1809 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000730 # Number of seconds simulated -sim_ticks 729906500 # Number of ticks simulated -final_tick 729906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000790 # Number of seconds simulated +sim_ticks 789792500 # Number of ticks simulated +final_tick 789792500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 158517498 # Simulator tick rate (ticks/s) -host_mem_usage 277860 # Number of bytes of host memory used -host_seconds 4.60 # Real time elapsed on the host +host_tick_rate 129975147 # Simulator tick rate (ticks/s) +host_mem_usage 221936 # Number of bytes of host memory used +host_seconds 6.08 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 76606 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 79713 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 76745 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 78087 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 75189 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77277 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 77630 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 79795 # Number of bytes read from this memory -system.physmem.bytes_read::total 621042 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 386688 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5335 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5543 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5476 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5451 # Number of bytes written to this memory -system.physmem.bytes_written::total 430089 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10810 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6042 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5335 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5543 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5476 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49443 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 104953169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 109209878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 105143604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 106982196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 103011824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 105872464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 106356088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 109322221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 850851445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 529777444 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7329706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 7309155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7313265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7594123 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 7485890 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7502331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7458490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7468080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 589238485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 529777444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 112282875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 116519034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 112456869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 114576319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 110497714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 113374795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 113814578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 116790301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1440089929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 78179 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78681 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79146 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 76465 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 76157 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 75918 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79229 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 81414 # Number of bytes read from this memory +system.physmem.bytes_read::total 625189 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 393152 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5414 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5436 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5494 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5519 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5358 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5447 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5462 # Number of bytes written to this memory +system.physmem.bytes_written::total 436740 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10874 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87862 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6143 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5414 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5436 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5494 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5519 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5358 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5447 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5462 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49731 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 98986759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 99622369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 100211131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 96816569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 96426593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 96123982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 100316222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 103082772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 791586398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 497791509 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 6854965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6882820 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 6956257 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6987911 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6784060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 6910676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 6896748 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 6915741 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 552980688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 497791509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 105841724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 106505190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 107167389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 103804480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 103210653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 103034658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 107212970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 109998512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1344567086 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99153 # number of read accesses completed -system.cpu0.num_writes 54942 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22508 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.884164 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13343 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22908 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.582460 # Average number of references to valid blocks. +system.cpu0.num_reads 99211 # number of read accesses completed +system.cpu0.num_writes 54990 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22470 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.865816 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13332 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22858 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.583253 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.884164 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.769305 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.769305 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337372 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337372 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8651 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8651 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1083 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9734 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9734 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9734 # number of overall hits -system.cpu0.l1c.overall_hits::total 9734 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36335 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36335 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24086 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24086 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60421 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60421 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60421 # number of overall misses -system.cpu0.l1c.overall_misses::total 60421 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1008804376 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1008804376 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 935467464 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 935467464 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1944271840 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1944271840 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1944271840 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1944271840 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44986 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44986 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25169 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70155 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70155 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807696 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807696 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956971 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956971 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861250 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861250 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861250 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861250 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27763.984478 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 27763.984478 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38838.639209 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 38838.639209 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 32178.743152 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 32178.743152 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 32178.743152 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 32178.743152 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1068204 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 393.865816 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.769269 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.769269 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337265 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337265 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8594 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8594 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9737 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9737 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9737 # number of overall hits +system.cpu0.l1c.overall_hits::total 9737 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36367 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36367 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 24030 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 24030 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60397 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60397 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60397 # number of overall misses +system.cpu0.l1c.overall_misses::total 60397 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1097985534 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1097985534 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1003527320 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1003527320 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2101512854 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2101512854 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2101512854 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2101512854 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44961 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44961 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25173 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25173 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70134 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70134 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70134 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70134 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808857 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808857 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954594 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954594 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861166 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861166 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861166 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861166 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 30191.809443 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 30191.809443 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 41761.436538 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 41761.436538 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 34794.987400 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 34794.987400 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 34794.987400 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 34794.987400 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1144726 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61717 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61078 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.308100 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 18.742035 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9915 # number of writebacks -system.cpu0.l1c.writebacks::total 9915 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36335 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36335 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24086 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24086 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60421 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60421 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60421 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60421 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 953224016 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 953224016 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 898871386 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 898871386 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1852095402 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1852095402 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1852095402 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1852095402 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 743740324 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 743740324 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1921383275 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1921383275 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2665123599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2665123599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807696 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807696 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956971 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956971 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861250 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861250 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26234.319967 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26234.319967 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37319.247115 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37319.247115 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9946 # number of writebacks +system.cpu0.l1c.writebacks::total 9946 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36367 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36367 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24030 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 24030 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60397 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60397 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60397 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60397 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9956 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5416 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5416 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15372 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15372 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1042449014 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1042449014 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 966947420 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 966947420 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2009396434 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2009396434 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2009396434 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2009396434 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 778948863 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 778948863 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 2127994240 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 2127994240 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2906943103 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2906943103 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808857 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808857 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954594 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954594 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861166 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861166 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861166 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 28664.696401 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 28664.696401 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 40239.176862 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 40239.176862 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 33269.805355 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78239.138509 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78239.138509 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 392908.833087 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392908.833087 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 189106.368918 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 189106.368918 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 54938 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22377 # number of replacements -system.cpu1.l1c.tags.tagsinuse 394.468790 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13456 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.590564 # Average number of references to valid blocks. +system.cpu1.num_writes 55318 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22177 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.980771 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13598 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22566 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.602588 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 394.468790 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.770447 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.770447 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338150 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338150 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8709 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8709 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1179 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1179 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9888 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9888 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9888 # number of overall hits -system.cpu1.l1c.overall_hits::total 9888 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36587 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36587 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23856 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23856 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60443 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60443 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60443 # number of overall misses -system.cpu1.l1c.overall_misses::total 60443 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1017715976 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1017715976 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 924313604 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 924313604 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1942029580 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1942029580 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1942029580 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1942029580 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45296 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45296 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25035 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70331 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70331 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70331 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70331 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807731 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807731 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.952906 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.952906 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859408 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859408 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859408 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859408 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27816.327548 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 27816.327548 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38745.540074 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 38745.540074 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 32129.933657 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 32129.933657 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 32129.933657 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 32129.933657 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1075887 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.980771 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.769494 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.769494 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338430 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338430 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8884 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8884 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1068 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1068 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9952 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9952 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9952 # number of overall hits +system.cpu1.l1c.overall_hits::total 9952 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36538 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36538 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23930 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23930 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60468 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60468 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60468 # number of overall misses +system.cpu1.l1c.overall_misses::total 60468 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1108002821 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1108002821 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 993849096 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 993849096 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2101851917 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2101851917 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2101851917 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2101851917 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45422 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45422 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24998 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24998 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70420 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70420 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70420 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70420 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804412 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.804412 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.957277 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.957277 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858677 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858677 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858677 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858677 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 30324.670781 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 30324.670781 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 41531.512578 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 41531.512578 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 34759.739317 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 34759.739317 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 34759.739317 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 34759.739317 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1147241 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62059 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61428 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.336518 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 18.676190 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9753 # number of writebacks -system.cpu1.l1c.writebacks::total 9753 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36587 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36587 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23856 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23856 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60443 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60443 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 961736168 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 961736168 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 888050076 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 888050076 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1849786244 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1849786244 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1849786244 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1849786244 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 753708733 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 753708733 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1923800282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1923800282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2677509015 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2677509015 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807731 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807731 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952906 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952906 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859408 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859408 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26286.281138 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26286.281138 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37225.439135 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37225.439135 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9780 # number of writebacks +system.cpu1.l1c.writebacks::total 9780 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36538 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36538 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23930 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23930 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60468 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60468 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60468 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 10010 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 10010 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5438 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15448 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15448 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1052180887 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1052180887 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 957433148 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 957433148 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2009614035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2009614035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2009614035 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2009614035 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 780874824 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 780874824 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 2141613646 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 2141613646 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2922488470 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2922488470 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804412 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804412 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.957277 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.957277 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858677 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858677 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858677 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 28796.893289 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 28796.893289 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 40009.742917 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 40009.742917 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 33234.339403 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78009.472927 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78009.472927 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 393823.767194 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 393823.767194 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 189182.319394 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 189182.319394 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99515 # number of read accesses completed -system.cpu2.num_writes 55356 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22413 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.491739 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22815 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.589437 # Average number of references to valid blocks. +system.cpu2.num_reads 99906 # number of read accesses completed +system.cpu2.num_writes 55186 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22429 # number of replacements +system.cpu2.l1c.tags.tagsinuse 394.168243 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13360 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.585605 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.491739 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.770492 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.770492 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338294 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338294 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8726 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8726 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1175 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1175 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9901 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9901 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9901 # number of overall hits -system.cpu2.l1c.overall_hits::total 9901 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36442 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36442 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24017 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24017 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses -system.cpu2.l1c.overall_misses::total 60459 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1013968188 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1013968188 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 926155084 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 926155084 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1940123272 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1940123272 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1940123272 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1940123272 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45168 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25192 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25192 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70360 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70360 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806810 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806810 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953358 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953358 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859281 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859281 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859281 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859281 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27824.164096 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 27824.164096 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38562.480077 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 38562.480077 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 32089.900131 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 32089.900131 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 32089.900131 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 32089.900131 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1067763 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 394.168243 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.769860 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.769860 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338029 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338029 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8660 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8660 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1124 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1124 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9784 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9784 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9784 # number of overall hits +system.cpu2.l1c.overall_hits::total 9784 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36507 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36507 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24000 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24000 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60507 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60507 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60507 # number of overall misses +system.cpu2.l1c.overall_misses::total 60507 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1106428919 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1106428919 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1000960978 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1000960978 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2107389897 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2107389897 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2107389897 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2107389897 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45167 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45167 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70291 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70291 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70291 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70291 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808267 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.808267 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955262 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955262 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860807 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860807 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860807 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860807 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 30307.308708 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 30307.308708 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 41706.707417 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 41706.707417 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 34828.861074 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 34828.861074 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 34828.861074 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 34828.861074 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1143492 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 61601 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.333534 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 18.666514 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9861 # number of writebacks -system.cpu2.l1c.writebacks::total 9861 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36442 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36442 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24017 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24017 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958233322 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958233322 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 889641050 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 889641050 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847874372 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1847874372 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847874372 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1847874372 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 744958366 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 744958366 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1919549279 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1919549279 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2664507645 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2664507645 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806810 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806810 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953358 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953358 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859281 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859281 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26294.751166 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26294.751166 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37042.138902 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37042.138902 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9834 # number of writebacks +system.cpu2.l1c.writebacks::total 9834 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36507 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36507 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24000 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60507 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60507 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60507 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60507 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9899 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9899 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5496 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5496 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15395 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1050702877 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1050702877 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 964435030 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 964435030 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2015137907 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2015137907 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2015137907 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2015137907 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 774345338 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 774345338 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 2129438676 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 2129438676 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2903784014 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2903784014 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808267 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808267 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955262 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955262 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860807 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860807 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860807 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 28780.860575 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 28780.860575 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 40184.792917 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 40184.792917 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 33304.211199 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78224.602283 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78224.602283 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 387452.451965 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 387452.451965 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 188618.643326 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 188618.643326 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99509 # number of read accesses completed -system.cpu3.num_writes 55322 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22357 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.352238 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13564 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22743 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.596403 # Average number of references to valid blocks. +system.cpu3.num_reads 99687 # number of read accesses completed +system.cpu3.num_writes 54914 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22514 # number of replacements +system.cpu3.l1c.tags.tagsinuse 394.486423 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13398 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22905 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.584938 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.352238 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770219 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770219 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338647 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338647 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8763 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8763 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1221 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1221 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9984 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9984 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9984 # number of overall hits -system.cpu3.l1c.overall_hits::total 9984 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36641 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36641 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23832 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23832 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60473 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60473 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60473 # number of overall misses -system.cpu3.l1c.overall_misses::total 60473 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1024295614 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1024295614 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 922064777 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 922064777 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1946360391 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1946360391 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1946360391 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1946360391 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45404 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45404 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25053 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25053 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70457 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70457 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70457 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70457 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806999 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806999 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.951263 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.951263 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858297 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858297 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858297 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858297 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27954.903360 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 27954.903360 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38690.197088 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 38690.197088 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 32185.609958 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 32185.609958 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 32185.609958 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 32185.609958 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1061792 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 394.486423 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.770481 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.770481 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 351 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337490 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337490 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8775 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8775 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1091 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1091 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9866 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9866 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9866 # number of overall hits +system.cpu3.l1c.overall_hits::total 9866 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36393 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36393 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23929 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23929 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60322 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60322 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60322 # number of overall misses +system.cpu3.l1c.overall_misses::total 60322 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1101223942 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1101223942 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 999641040 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 999641040 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2100864982 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2100864982 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2100864982 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2100864982 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45168 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25020 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25020 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70188 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70188 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70188 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70188 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805725 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805725 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956395 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956395 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859435 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859435 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859435 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859435 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 30259.224082 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 30259.224082 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 41775.295248 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 41775.295248 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 34827.508736 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 34827.508736 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 34827.508736 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 34827.508736 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1140042 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61430 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 60968 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.284584 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 18.699022 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9814 # number of writebacks -system.cpu3.l1c.writebacks::total 9814 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36641 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23832 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60473 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60473 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 968238306 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 968238306 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 885855695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 885855695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1854094001 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1854094001 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1854094001 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1854094001 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 733819505 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 733819505 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1976786114 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1976786114 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2710605619 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2710605619 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806999 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.951263 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.951263 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858297 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858297 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26424.996752 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26424.996752 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37170.849908 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37170.849908 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9981 # number of writebacks +system.cpu3.l1c.writebacks::total 9981 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36393 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36393 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23929 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60322 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60322 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60322 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60322 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9906 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5522 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15428 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1045674368 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1045674368 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 963227618 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 963227618 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2008901986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2008901986 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2008901986 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2008901986 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 776644993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 776644993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 2134037166 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 2134037166 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2910682159 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2910682159 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805725 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805725 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956395 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956395 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859435 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859435 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859435 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 28732.843349 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 28732.843349 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 40253.567554 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 40253.567554 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 33302.973807 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78401.473148 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78401.473148 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 386460.913799 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 386460.913799 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 188662.312613 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 188662.312613 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99688 # number of read accesses completed -system.cpu4.num_writes 55538 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22215 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.788113 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13621 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22618 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.602219 # Average number of references to valid blocks. +system.cpu4.num_reads 99646 # number of read accesses completed +system.cpu4.num_writes 55076 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22475 # number of replacements +system.cpu4.l1c.tags.tagsinuse 394.666578 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13432 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587243 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.788113 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.765211 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.765211 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 365 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338206 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338206 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8861 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8861 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1198 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1198 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits -system.cpu4.l1c.overall_hits::total 10059 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36318 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36318 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24000 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24000 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60318 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60318 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60318 # number of overall misses -system.cpu4.l1c.overall_misses::total 60318 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1007698293 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1007698293 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 930213172 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 930213172 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1937911465 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1937911465 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1937911465 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1937911465 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45179 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45179 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25198 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25198 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70377 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70377 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70377 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70377 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803869 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.803869 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952457 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952457 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857070 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857070 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857070 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857070 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27746.524946 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 27746.524946 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38758.882167 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 38758.882167 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 32128.244720 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 32128.244720 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 32128.244720 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 32128.244720 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1066740 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 394.666578 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.770833 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.770833 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 352 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338590 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338590 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8683 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8683 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1163 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1163 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9846 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9846 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9846 # number of overall hits +system.cpu4.l1c.overall_hits::total 9846 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36657 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36657 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23918 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23918 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60575 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60575 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60575 # number of overall misses +system.cpu4.l1c.overall_misses::total 60575 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1108449638 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1108449638 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 999797609 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 999797609 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2108247247 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2108247247 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2108247247 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2108247247 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45340 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45340 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25081 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25081 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70421 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70421 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70421 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70421 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808491 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.808491 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953630 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953630 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.860184 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.860184 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.860184 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.860184 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 30238.416619 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 30238.416619 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 41801.053976 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 41801.053976 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 34803.916583 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 34803.916583 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 34803.916583 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 34803.916583 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1151337 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61639 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61602 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.306251 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 18.689929 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9826 # number of writebacks -system.cpu4.l1c.writebacks::total 9826 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36318 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36318 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24000 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60318 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60318 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60318 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60318 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 952156937 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 952156937 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 893690718 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 893690718 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1845847655 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1845847655 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1845847655 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1845847655 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748268844 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748268844 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1945456088 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1945456088 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2693724932 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2693724932 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803869 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803869 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952457 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952457 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857070 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857070 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26217.218377 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26217.218377 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37237.113250 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37237.113250 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9802 # number of writebacks +system.cpu4.l1c.writebacks::total 9802 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36657 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36657 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23918 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60575 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60575 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60575 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60575 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9982 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5360 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5360 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15342 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15342 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1052462662 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1052462662 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 963409159 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 963409159 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2015871821 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2015871821 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2015871821 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2015871821 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 780487806 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 780487806 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 2113182760 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 2113182760 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2893670566 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2893670566 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808491 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808491 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953630 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953630 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.860184 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860184 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.860184 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 28711.096435 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 28711.096435 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 40279.670499 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 40279.670499 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 33278.940504 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78189.521739 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78189.521739 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 394250.514925 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 394250.514925 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 188611.039369 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 188611.039369 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98777 # number of read accesses completed -system.cpu5.num_writes 55102 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22389 # number of replacements -system.cpu5.l1c.tags.tagsinuse 394.368473 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13612 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.597411 # Average number of references to valid blocks. +system.cpu5.num_reads 99659 # number of read accesses completed +system.cpu5.num_writes 54989 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22353 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.762821 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13360 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22726 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.587873 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 394.368473 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.770251 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.770251 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338353 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338353 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8788 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8788 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1200 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1200 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9988 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9988 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9988 # number of overall hits -system.cpu5.l1c.overall_hits::total 9988 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36608 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36608 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23815 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23815 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60423 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60423 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60423 # number of overall misses -system.cpu5.l1c.overall_misses::total 60423 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1017800983 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1017800983 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 926597102 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 926597102 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1944398085 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1944398085 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1944398085 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1944398085 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45396 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45396 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25015 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25015 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70411 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70411 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70411 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70411 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806415 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806415 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952029 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952029 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858147 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858147 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858147 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858147 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27802.692936 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 27802.692936 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38908.129414 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 38908.129414 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 32179.767390 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 32179.767390 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 32179.767390 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 32179.767390 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1064852 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.762821 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.767115 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.767115 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 325 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.728516 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337942 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337942 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8666 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8666 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1136 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1136 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9802 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9802 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9802 # number of overall hits +system.cpu5.l1c.overall_hits::total 9802 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36641 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36641 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23834 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23834 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60475 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60475 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60475 # number of overall misses +system.cpu5.l1c.overall_misses::total 60475 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1106472248 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1106472248 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 994607245 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 994607245 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2101079493 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2101079493 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2101079493 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2101079493 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45307 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45307 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24970 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24970 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70277 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70277 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70277 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70277 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808727 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808727 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954505 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954505 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860523 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860523 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860523 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860523 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 30197.654212 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 30197.654212 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 41730.605228 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 41730.605228 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 34742.943249 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 34742.943249 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 34742.943249 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 34742.943249 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1144155 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61539 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61191 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.303694 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 18.698093 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9851 # number of writebacks -system.cpu5.l1c.writebacks::total 9851 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36608 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23815 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60423 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60423 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 961777191 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 961777191 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890427492 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890427492 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1852204683 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1852204683 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1852204683 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1852204683 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 736504009 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 736504009 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1948720715 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1948720715 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2685224724 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2685224724 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806415 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806415 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952029 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952029 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858147 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858147 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26272.322744 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26272.322744 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37389.355112 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37389.355112 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9829 # number of writebacks +system.cpu5.l1c.writebacks::total 9829 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36641 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23834 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23834 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60475 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60475 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5460 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5460 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15394 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15394 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1050521774 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1050521774 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 958365245 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 958365245 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2008887019 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2008887019 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2008887019 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2008887019 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 778256892 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 778256892 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 2141596587 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 2141596587 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2919853479 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2919853479 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808727 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808727 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954505 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954505 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860523 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860523 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860523 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 28670.663301 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 28670.663301 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 40210.004405 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 40210.004405 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 33218.470757 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78342.751359 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78342.751359 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 392233.807143 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392233.807143 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 189674.774523 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 189674.774523 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99339 # number of read accesses completed -system.cpu6.num_writes 55520 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22403 # number of replacements -system.cpu6.l1c.tags.tagsinuse 393.263413 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13582 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22789 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.595989 # Average number of references to valid blocks. +system.cpu6.num_reads 99691 # number of read accesses completed +system.cpu6.num_writes 55108 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22433 # number of replacements +system.cpu6.l1c.tags.tagsinuse 394.732703 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13465 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.590234 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 393.263413 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.768093 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.768093 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338803 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338803 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8815 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8815 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1164 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1164 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9979 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9979 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9979 # number of overall hits -system.cpu6.l1c.overall_hits::total 9979 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36385 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36385 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24126 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24126 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60511 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60511 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60511 # number of overall misses -system.cpu6.l1c.overall_misses::total 60511 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1008730718 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1008730718 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 936995994 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 936995994 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1945726712 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1945726712 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1945726712 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1945726712 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45200 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45200 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25290 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25290 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70490 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70490 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70490 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70490 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804978 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.804978 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953974 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858434 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858434 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858434 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858434 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27723.807008 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 27723.807008 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38837.602338 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 38837.602338 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 32154.925749 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 32154.925749 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 32154.925749 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 32154.925749 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1063684 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 394.732703 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.770962 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.770962 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.742188 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 339043 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 339043 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8806 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8806 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9950 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9950 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9950 # number of overall hits +system.cpu6.l1c.overall_hits::total 9950 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36628 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36628 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23944 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23944 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60572 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60572 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60572 # number of overall misses +system.cpu6.l1c.overall_misses::total 60572 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1115774950 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1115774950 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 994580574 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 994580574 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2110355524 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2110355524 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2110355524 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2110355524 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45434 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45434 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25088 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25088 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70522 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70522 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70522 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70522 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806180 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806180 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954401 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954401 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858909 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858909 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858909 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858909 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 30462.349842 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 30462.349842 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 41537.778734 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 41537.778734 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 34840.446477 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 34840.446477 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 34840.446477 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 34840.446477 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1141787 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61545 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61213 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.283029 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 18.652688 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9842 # number of writebacks -system.cpu6.l1c.writebacks::total 9842 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36385 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36385 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24126 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24126 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60511 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60511 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60511 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60511 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 953086366 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 953086366 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 900293024 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 900293024 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1853379390 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1853379390 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1853379390 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1853379390 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 738599910 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 738599910 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1965255677 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1965255677 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2703855587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2703855587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804978 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804978 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953974 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858434 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858434 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26194.485805 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26194.485805 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37316.298765 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37316.298765 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9839 # number of writebacks +system.cpu6.l1c.writebacks::total 9839 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36628 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36628 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23944 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60572 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60572 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60572 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60572 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5449 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1059827480 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1059827480 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 958175570 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 958175570 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2018003050 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2018003050 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2018003050 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2018003050 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767222409 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767222409 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 2138123651 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 2138123651 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2905346060 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2905346060 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806180 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806180 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954401 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954401 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858909 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858909 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858909 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 28934.898984 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 28934.898984 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 40017.355914 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 40017.355914 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 33315.773790 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78367.968233 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78367.968233 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 392388.264085 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 392388.264085 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 190652.015224 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 190652.015224 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99565 # number of read accesses completed -system.cpu7.num_writes 55051 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22600 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.642544 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13380 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22986 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.582093 # Average number of references to valid blocks. +system.cpu7.num_reads 99881 # number of read accesses completed +system.cpu7.num_writes 55258 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22490 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.773487 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13394 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22887 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.585223 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.642544 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.770786 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.770786 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338392 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338392 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8664 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8664 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1142 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1142 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9806 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9806 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9806 # number of overall hits -system.cpu7.l1c.overall_hits::total 9806 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36635 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36635 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23923 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23923 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60558 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60558 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60558 # number of overall misses -system.cpu7.l1c.overall_misses::total 60558 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1023029462 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1023029462 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 929610099 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 929610099 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1952639561 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1952639561 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1952639561 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1952639561 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25065 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70364 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70364 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70364 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70364 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808737 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.808737 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954438 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954438 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860639 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860639 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860639 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860639 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27924.920486 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 27924.920486 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38858.424905 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 38858.424905 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 32244.122346 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 32244.122346 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 32244.122346 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 32244.122346 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1066072 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 394.773487 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.771042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.771042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 361 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338728 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338728 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8705 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8705 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1114 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1114 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9819 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9819 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9819 # number of overall hits +system.cpu7.l1c.overall_hits::total 9819 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36637 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36637 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23983 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23983 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60620 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60620 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60620 # number of overall misses +system.cpu7.l1c.overall_misses::total 60620 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1106293724 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1106293724 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1002572296 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1002572296 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2108866020 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2108866020 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2108866020 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2108866020 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45342 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45342 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25097 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25097 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70439 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70439 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70439 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70439 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808015 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.808015 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955612 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955612 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860603 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860603 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860603 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860603 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 30196.078391 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 30196.078391 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 41803.456448 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 41803.456448 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 34788.288024 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 34788.288024 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 34788.288024 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 34788.288024 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1141532 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 61535 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61288 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.324645 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 18.625702 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9831 # number of writebacks -system.cpu7.l1c.writebacks::total 9831 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36635 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36635 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23923 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23923 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60558 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60558 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60558 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60558 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 966974672 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 966974672 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 893289987 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 893289987 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1860264659 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1860264659 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1860264659 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1860264659 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 731988929 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 731988929 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1960595657 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1960595657 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2692584586 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2692584586 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808737 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808737 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954438 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954438 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860639 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860639 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26394.832046 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26394.832046 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37340.215985 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37340.215985 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9784 # number of writebacks +system.cpu7.l1c.writebacks::total 9784 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36637 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23983 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60620 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60620 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60620 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60620 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9862 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5465 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5465 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15327 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15327 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1050368666 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1050368666 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 966121280 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 966121280 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2016489946 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2016489946 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2016489946 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2016489946 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 770060879 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 770060879 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 2135523645 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 2135523645 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2905584524 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2905584524 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808015 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808015 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955612 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955612 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860603 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860603 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860603 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 28669.614488 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 28669.614488 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 40283.587541 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 40283.587541 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78083.642162 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78083.642162 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 390763.704483 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 390763.704483 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 189572.944738 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 189572.944738 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12974 # number of replacements -system.l2c.tags.tagsinuse 782.339791 # Cycle average of tags in use -system.l2c.tags.total_refs 149980 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13746 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.910810 # Average number of references to valid blocks. +system.l2c.tags.replacements 12865 # number of replacements +system.l2c.tags.tagsinuse 778.482244 # Cycle average of tags in use +system.l2c.tags.total_refs 150454 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13664 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.010978 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 728.962494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.892190 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.186949 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.375204 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.806314 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.399875 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.389081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.432209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.895475 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.711877 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007019 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006226 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006647 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006250 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006281 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764004 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 772 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 551 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1963370 # Number of tag accesses -system.l2c.tags.data_accesses 1963370 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10704 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10790 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10626 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10729 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10684 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10653 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10669 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85605 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 75955 # number of Writeback hits -system.l2c.Writeback_hits::total 75955 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 339 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 357 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 325 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2692 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1953 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1945 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1922 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1952 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1880 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1895 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15383 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12548 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12609 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12579 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 91101 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 75955 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 75955 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2280 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2211 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2259 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2295 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2293 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18292 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6404 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6350 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6303 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6320 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6284 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6361 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6307 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50641 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17778 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17849 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17615 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17765 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17711 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17652 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17684 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17688 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 141742 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17778 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17849 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17615 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17765 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17711 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17652 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17684 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17688 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 141742 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.058906 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.061658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.060644 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.060725 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.058777 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.060169 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.059172 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.062560 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.060329 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.855666 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.851316 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.848485 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851262 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.851852 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.845855 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.859732 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.858264 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.852832 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.695034 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.693701 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.695066 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.691139 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.702155 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.698440 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.698475 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.695893 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.696234 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.288053 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.286515 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.287653 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.284999 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288070 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.287390 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.289131 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.288388 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.287522 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.288053 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.286515 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.287653 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.284999 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288070 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.287390 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.289131 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288388 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.287522 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60808.873134 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 62076.071932 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 61198.879009 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61331.572662 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 60844.688060 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 61500.640351 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 62161.076119 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61902.279494 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61484.075146 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28751.761833 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28801.132921 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28650.052772 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29156.526261 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29231.968798 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29527.054620 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29232.680723 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28763.719004 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29016.025321 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54649.507751 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54681.148922 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54684.195389 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54775.745879 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54646.875903 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54716.441786 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54656.417736 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54569.028708 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54672.264054 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55455.361062 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55706.373876 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55566.191237 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55675.666798 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55460.779106 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55631.165188 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55639.817133 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55592.607332 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55590.890784 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55455.361062 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55706.373876 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55566.191237 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55675.666798 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55460.779106 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55631.165188 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55639.817133 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55592.607332 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55590.890784 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 10498 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 726.215945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 5.941011 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.607450 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.516565 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.767835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.065793 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.555833 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.650782 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.161030 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.709195 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.005802 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006453 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006609 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.005924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006402 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006495 # 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number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 75954 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 75954 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2310 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2295 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2298 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2265 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2248 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2278 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18274 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6311 # 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miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.885033 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.874238 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.875055 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.875890 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.878841 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880048 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.727460 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.722090 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.730548 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.724988 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717829 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.726705 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.715905 # 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average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61174.914706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 60878.852436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61108.128143 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30275.160635 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 30610.754810 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 30825.884086 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30288.479902 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28343.454455 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 30092.078708 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29379.632301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29716.782717 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29945.839634 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54781.955130 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54618.652404 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54659.601702 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54677.013734 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54851.685137 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54590.629296 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54679.671648 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54794.138511 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54706.996788 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55460.636416 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55510.229841 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55549.921676 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55489.007443 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55550.636951 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55507.683756 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55535.136549 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55580.935532 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55523.253539 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55460.636416 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55510.229841 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55549.921676 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55489.007443 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55550.636951 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55507.683756 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55535.136549 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55580.935532 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55523.253539 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 8422 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1439 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1138 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.295344 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.400703 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6042 # number of writebacks -system.l2c.writebacks::total 6042 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6144 # number of writebacks +system.l2c.writebacks::total 6144 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::total 23 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 662 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 705 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 678 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 691 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 663 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 677 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 662 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 707 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5445 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1985 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1941 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1876 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1922 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1955 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1959 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1992 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1967 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15597 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4445 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4400 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4378 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4367 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4441 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35235 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5107 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5105 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5058 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5093 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5064 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5103 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5094 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40680 # 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number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 32539439 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 33571932 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 33370421 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 35357421 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 270275455 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 83067491 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81344988 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78653997 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 80593493 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81980984 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 82268488 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 83402478 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 82404992 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 653716911 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 189131446 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 187405945 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 186408946 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 186284944 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 188429940 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 186911948 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 188992946 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 186252939 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1499819054 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 221587387 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 222698881 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 219929872 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 220451383 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 220969379 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 220483880 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 222363367 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 221610360 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1770094509 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 221587387 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 222698881 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 219929872 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 220451383 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 220969379 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 220483880 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 222363367 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 221610360 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1770094509 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 412646911 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 419015931 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 413234441 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 407408946 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 415648431 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 408376439 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 410035928 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406831940 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3293198967 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 229215970 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 228786954 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 227259971 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 236423452 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 233573451 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 234334469 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233635458 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 232899980 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1856129705 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 641862881 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 647802885 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 640494412 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 643832398 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 649221882 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 642710908 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 643671386 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 639731920 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5149328672 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.058203 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.061310 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.059936 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060376 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.058163 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.059553 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.058465 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062121 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.059769 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.855235 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851316 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.848485 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850819 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851852 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845855 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.859732 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.857828 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.852668 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.694097 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.692913 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.694590 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.690981 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.701838 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698122 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.698161 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.695576 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.695780 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.287000 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.287000 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49027.101208 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50060.902128 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49440.893805 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49444.918958 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49079.093514 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49589.264402 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50408.490937 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50010.496464 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49637.365473 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41847.602519 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41908.803709 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41926.437633 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41932.098335 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41934.007161 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41995.144461 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41868.713855 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41893.742755 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41912.990383 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42549.256693 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42592.260227 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42578.562357 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42657.417907 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42534.975169 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42605.869159 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42556.394055 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42455.650558 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42566.171534 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.demand_mshr_hits::cpu0 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 63 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 628 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 680 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 688 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 646 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 652 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 666 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 693 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5329 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2017 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2027 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2034 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2040 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2008 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1968 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2002 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16078 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4588 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4530 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4579 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4586 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4599 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4651 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4482 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4697 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 36712 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5216 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5210 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5267 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5232 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5251 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5317 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5390 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42041 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5216 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5210 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5267 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5232 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5251 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5317 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5390 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42041 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9956 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 10009 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9898 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9906 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9982 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9934 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9790 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9862 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 79337 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5436 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5494 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5519 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5358 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5458 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5448 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5462 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43589 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15370 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15445 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15392 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15425 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15340 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15392 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15238 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15324 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122926 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 30458949 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 33700940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 34051940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 31884439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 31746444 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 33289946 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 33296940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 33931439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 262361037 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 84760496 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 85183996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 85374489 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85565499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 84458998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83295996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82516991 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 84106992 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 675263457 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 195759954 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192669961 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 194828295 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 195239452 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 196619949 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 197755466 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 190831957 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 200614450 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1564319484 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 226218903 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 226370901 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 228880235 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 227123891 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 228366393 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 231045412 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 224128897 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 234545889 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1826680521 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 226218903 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 226370901 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 228880235 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 227123891 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 228366393 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 231045412 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 224128897 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 234545889 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1826680521 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420391962 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 422439462 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 417792957 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 418505281 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 421118468 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 419294453 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413123964 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416090788 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3348757335 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 237106474 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237782975 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 241705476 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 241076980 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 235943478 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 241042480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 238750464 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 240064477 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1913472804 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 657498436 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 660222437 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 659498433 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 659582261 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 657061946 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 660336933 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 651874428 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 656155265 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5262230139 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055477 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.059623 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.060499 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.057530 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.056918 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058876 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061338 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.058679 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877489 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.886275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885033 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.873803 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875055 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.875445 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878841 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.879829 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726985 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.721452 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730070 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.724830 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717361 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.725925 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.715746 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.726415 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.723603 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297002 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.294617 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.298515 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.298018 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.291627 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.303423 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297002 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48501.511146 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49560.205882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49494.098837 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49356.716718 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48690.865031 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49984.903904 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49255.828402 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 48963.115440 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49232.696003 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42023.052058 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42024.665022 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41973.691740 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.872059 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42061.253984 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42026.234107 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41929.365346 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42011.484515 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41999.219866 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42667.819093 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42532.000221 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42548.219043 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42572.928914 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42752.761252 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42518.913352 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42577.411200 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42711.187992 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42610.576487 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 43370.188459 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43449.309213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43455.522119 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43410.529625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43454.092910 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43452.674874 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43515.007236 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43449.977903 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42224.986139 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42205.960835 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42209.836027 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42247.656067 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42187.784813 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42208.018220 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42198.566292 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42191.319002 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42209.276063 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 43795.063539 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 43742.269132 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 43994.444121 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 43681.279217 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44035.736842 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44163.151337 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 43823.506608 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 43951.753387 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 43898.066118 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 42778.037476 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 42746.677695 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 42846.831666 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 42760.600389 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 42833.242894 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 42901.308017 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 42779.526710 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 42818.798290 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 42808.113328 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 123330 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 121282 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 252480 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 249408 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 84079 # Transaction distribution -system.membus.trans_dist::ReadResp 84076 # Transaction distribution -system.membus.trans_dist::WriteReq 43401 # Transaction distribution -system.membus.trans_dist::WriteResp 43399 # Transaction distribution -system.membus.trans_dist::Writeback 6042 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58662 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47800 # Transaction distribution -system.membus.trans_dist::ReadExReq 50251 # Transaction distribution -system.membus.trans_dist::ReadExResp 3038 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 420748 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1051128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1051128 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58073 # Total snoops (count) -system.membus.snoop_fanout::samples 123330 # Request fanout histogram +system.membus.trans_dist::ReadReq 84654 # Transaction distribution +system.membus.trans_dist::ReadResp 84652 # Transaction distribution +system.membus.trans_dist::WriteReq 43588 # Transaction distribution +system.membus.trans_dist::WriteResp 43585 # Transaction distribution +system.membus.trans_dist::Writeback 6143 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60492 # Transaction distribution +system.membus.trans_dist::UpgradeResp 49595 # Transaction distribution +system.membus.trans_dist::ReadExReq 50638 # Transaction distribution +system.membus.trans_dist::ReadExResp 3207 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 426554 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1061863 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1061863 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 58325 # Total snoops (count) +system.membus.snoop_fanout::samples 252480 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 252480 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123330 # Request fanout histogram -system.membus.reqLayer0.occupancy 349185814 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 47.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 311191349 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 42.6 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 561297 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 261699 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 297550 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 252480 # Request fanout histogram +system.membus.reqLayer0.occupancy 472884580 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 59.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 313892142 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 39.7 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 684630 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 383351 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 298207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 370588 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370576 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43402 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43399 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75955 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29152 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29150 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162499 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162497 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120652 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120226 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120519 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120569 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120393 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120447 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120346 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 963662 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766434 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1752931 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1758190 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1756878 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1755329 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1752897 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1753790 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14054393 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 323559 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 561297 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.683086 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.176196 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 371695 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371689 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43589 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43585 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 75954 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29169 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29167 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162397 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162391 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120614 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120783 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120664 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120646 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120853 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120726 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120516 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120736 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 965538 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1750933 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1748576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754368 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1762730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757509 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1755676 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14042920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 324098 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 684630 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.384232 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.250303 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 53942 9.61% 9.61% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 251180 44.75% 54.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141382 25.19% 79.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 68926 12.28% 91.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 30158 5.37% 97.20% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11557 2.06% 99.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3492 0.62% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 660 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 176832 25.83% 25.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 250927 36.65% 62.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141295 20.64% 83.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 69195 10.11% 93.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 30377 4.44% 97.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11672 1.70% 99.37% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3607 0.53% 99.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 725 0.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 561297 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 720580520 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100512947 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100775889 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 100644932 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100575951 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100528413 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100450921 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 100623449 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100655480 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 684630 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 782327755 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 99.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100591456 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 12.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100721944 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100768962 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100555978 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 12.7 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100847968 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100723976 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100740497 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 12.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100846524 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 12.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index e072d02ad..ff9b64e46 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1689 +1,1764 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000473 # Number of seconds simulated -sim_ticks 473250000 # Number of ticks simulated -final_tick 473250000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 473398500 # Number of ticks simulated +final_tick 473398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 101630905 # Simulator tick rate (ticks/s) -host_mem_usage 277340 # Number of bytes of host memory used -host_seconds 4.66 # Real time elapsed on the host +host_tick_rate 74773462 # Simulator tick rate (ticks/s) +host_mem_usage 221944 # Number of bytes of host memory used +host_seconds 6.33 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 80424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 83171 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 80813 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 86214 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 79490 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 82665 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 85333 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 80902 # Number of bytes read from this memory -system.physmem.bytes_read::total 659012 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 419392 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5448 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5355 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5405 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5451 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5481 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5462 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5450 # Number of bytes written to this memory -system.physmem.bytes_written::total 462904 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10946 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11055 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11056 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10909 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6553 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5448 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5355 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5405 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5481 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5462 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5450 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50065 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 169939778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 175744321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 170761754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 182174326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 167966191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 174675119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 180312731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 170949815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1392524036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 886195457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 11537242 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 11511886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 11315372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 11421025 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 11518225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 11581616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 11541469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 11516112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 978138405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 886195457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 181477021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 187256207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 182077126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 193595351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 179484416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 186256735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 191854200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 182465927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2370662441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 85610 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 86349 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 81279 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 82686 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 83314 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 81031 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 83113 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 86498 # Number of bytes read from this memory +system.physmem.bytes_read::total 669880 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 430080 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5517 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5460 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5549 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5366 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5497 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5427 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5336 # Number of bytes written to this memory +system.physmem.bytes_written::total 473601 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10845 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10927 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10898 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87697 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6720 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5517 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5460 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5549 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5366 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5497 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5427 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5336 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50241 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 180841300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 182402352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 171692559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 174664685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 175991263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 171168688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 175566674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 182717098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1415044619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 908494640 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 11654029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 11533623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 11721626 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11335059 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 11341396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 11611782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 11463915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 11271688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1000427758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 908494640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 192495329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 193935976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 183414185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 185999744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 187332659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 182780469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 187030588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 193988785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2415472377 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 98988 # number of read accesses completed -system.cpu0.num_writes 54550 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22171 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.248330 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13318 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22569 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.590101 # Average number of references to valid blocks. +system.cpu0.num_reads 99308 # number of read accesses completed +system.cpu0.num_writes 55247 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22271 # number of replacements +system.cpu0.l1c.tags.tagsinuse 390.476059 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13537 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22673 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.597054 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.248330 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.764157 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.764157 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 335805 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 335805 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8501 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8501 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9644 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9644 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9644 # number of overall hits -system.cpu0.l1c.overall_hits::total 9644 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36474 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36474 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23719 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23719 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60193 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60193 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60193 # number of overall misses -system.cpu0.l1c.overall_misses::total 60193 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 587864141 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 587864141 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 652231215 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 652231215 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1240095356 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1240095356 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1240095356 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1240095356 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44975 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44975 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24862 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24862 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 69837 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 69837 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 69837 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 69837 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810984 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.810984 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954026 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954026 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861907 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861907 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861907 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861907 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16117.347727 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16117.347727 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27498.259412 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 27498.259412 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20601.986211 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20601.986211 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20601.986211 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20601.986211 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 773904 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 390.476059 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.762649 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.762649 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337706 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337706 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8778 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8778 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1202 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1202 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9980 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9980 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9980 # number of overall hits +system.cpu0.l1c.overall_hits::total 9980 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36312 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36312 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23969 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23969 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60281 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60281 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60281 # number of overall misses +system.cpu0.l1c.overall_misses::total 60281 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 585914746 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 585914746 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 661973304 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 661973304 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1247888050 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1247888050 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1247888050 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1247888050 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45090 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45090 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25171 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25171 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70261 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70261 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70261 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70261 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805323 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805323 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952247 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952247 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.857958 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.857958 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.857958 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.857958 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16135.568022 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16135.568022 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27617.894113 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 27617.894113 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20701.183623 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20701.183623 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20701.183623 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20701.183623 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 772989 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66096 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66053 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.708787 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.702557 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9687 # number of writebacks -system.cpu0.l1c.writebacks::total 9687 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36474 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36474 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23719 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23719 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60193 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60193 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60193 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60193 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 531003039 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 531003039 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 615653301 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 615653301 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1146656340 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1146656340 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1146656340 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1146656340 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 646054384 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 646054384 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 971060215 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 971060215 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1617114599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1617114599 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810984 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810984 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954026 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954026 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861907 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861907 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14558.398832 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14558.398832 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25956.123825 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25956.123825 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9819 # number of writebacks +system.cpu0.l1c.writebacks::total 9819 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36312 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36312 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23969 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60281 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60281 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60281 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60281 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9835 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9835 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5519 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15354 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15354 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 529167946 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 529167946 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 625061532 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 625061532 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1154229478 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1154229478 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1154229478 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1154229478 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 639072193 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 639072193 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 970312557 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 970312557 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1609384750 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1609384750 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805323 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805323 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952247 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952247 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857958 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.857958 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857958 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.857958 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14572.811908 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14572.811908 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 26077.914473 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 26077.914473 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19147.483917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19147.483917 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 64979.379054 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64979.379054 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 175813.110527 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175813.110527 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 104818.597760 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 104818.597760 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99262 # number of read accesses completed -system.cpu1.num_writes 54743 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22415 # number of replacements -system.cpu1.l1c.tags.tagsinuse 391.761420 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13414 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.587972 # Average number of references to valid blocks. +system.cpu1.num_reads 98972 # number of read accesses completed +system.cpu1.num_writes 54740 # number of write accesses completed +system.cpu1.l1c.tags.replacements 21894 # number of replacements +system.cpu1.l1c.tags.tagsinuse 389.013692 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13227 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22299 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.593166 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 391.761420 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.765159 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.765159 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 336589 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 336589 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8598 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8598 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1162 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1162 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9760 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9760 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9760 # number of overall hits -system.cpu1.l1c.overall_hits::total 9760 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36477 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36477 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23776 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23776 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses -system.cpu1.l1c.overall_misses::total 60253 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 595460828 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 595460828 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 649149772 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 649149772 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1244610600 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1244610600 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1244610600 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1244610600 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45075 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45075 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24938 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24938 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70013 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70013 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70013 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70013 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809251 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.809251 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953404 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953404 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860597 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860597 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860597 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860597 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16324.281821 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16324.281821 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27302.732672 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 27302.732672 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20656.408810 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20656.408810 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20656.408810 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20656.408810 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 769857 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 389.013692 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.759792 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.759792 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 335323 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 335323 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8521 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8521 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9673 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9673 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9673 # number of overall hits +system.cpu1.l1c.overall_hits::total 9673 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36191 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36191 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23860 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23860 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60051 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60051 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60051 # number of overall misses +system.cpu1.l1c.overall_misses::total 60051 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 587357926 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 587357926 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 665550173 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 665550173 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1252908099 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1252908099 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1252908099 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1252908099 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44712 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44712 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25012 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69724 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69724 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69724 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69724 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809425 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.809425 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953942 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.861267 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.861267 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.861267 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.861267 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16229.392004 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16229.392004 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27893.972045 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 27893.972045 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20864.067193 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20864.067193 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20864.067193 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20864.067193 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 781068 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 65915 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.679542 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.805922 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9826 # number of writebacks -system.cpu1.l1c.writebacks::total 9826 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36477 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23776 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23776 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 538442174 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 538442174 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 612498892 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 612498892 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1150941066 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1150941066 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1150941066 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1150941066 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 637533564 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 637533564 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 980538192 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 980538192 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1618071756 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1618071756 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809251 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809251 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953404 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953404 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860597 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860597 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14761.141925 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14761.141925 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25761.225269 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25761.225269 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9676 # number of writebacks +system.cpu1.l1c.writebacks::total 9676 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36191 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36191 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23860 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60051 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60051 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60051 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60051 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9870 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9870 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5462 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5462 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15332 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15332 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 530766130 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 530766130 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 628779775 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 628779775 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1159545905 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1159545905 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1159545905 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1159545905 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 639204350 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 639204350 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 954877634 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 954877634 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1594081984 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1594081984 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809425 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809425 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953942 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861267 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.861267 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861267 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.861267 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14665.693957 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14665.693957 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 26352.882439 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 26352.882439 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19309.352134 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19309.352134 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19309.352134 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19309.352134 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 64762.345491 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64762.345491 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 174821.976199 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174821.976199 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103970.909470 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103970.909470 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99661 # number of read accesses completed -system.cpu2.num_writes 54617 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22463 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.489979 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13594 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22875 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.594273 # Average number of references to valid blocks. +system.cpu2.num_reads 99459 # number of read accesses completed +system.cpu2.num_writes 55455 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22538 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.681778 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22938 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.590810 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.489979 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.766582 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.766582 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 412 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.804688 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338191 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338191 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8852 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8852 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1132 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1132 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9984 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9984 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9984 # number of overall hits -system.cpu2.l1c.overall_hits::total 9984 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36597 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36597 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23791 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23791 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60388 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60388 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60388 # number of overall misses -system.cpu2.l1c.overall_misses::total 60388 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 596108462 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 596108462 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 646461820 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 646461820 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1242570282 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1242570282 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1242570282 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1242570282 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24923 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24923 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70372 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70372 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805232 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805232 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954580 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954580 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858125 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858125 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858125 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858125 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16288.451567 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16288.451567 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27172.536674 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 27172.536674 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 20576.443697 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 20576.443697 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 20576.443697 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 20576.443697 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 768951 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.681778 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766957 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337495 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337495 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8694 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8694 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1182 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9876 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9876 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9876 # number of overall hits +system.cpu2.l1c.overall_hits::total 9876 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36455 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36455 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23891 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23891 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60346 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60346 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60346 # number of overall misses +system.cpu2.l1c.overall_misses::total 60346 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 592802045 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 592802045 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 663383699 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 663383699 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1256185744 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1256185744 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1256185744 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1256185744 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45149 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45149 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25073 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70222 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70222 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70222 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70222 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807438 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.807438 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952858 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.952858 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859360 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859360 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859360 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859360 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16261.199973 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16261.199973 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27767.096354 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 27767.096354 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20816.387896 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20816.387896 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20816.387896 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20816.387896 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 773062 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 65985 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66064 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.653421 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.701713 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9852 # number of writebacks -system.cpu2.l1c.writebacks::total 9852 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36597 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36597 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23791 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23791 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60388 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60388 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60388 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60388 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 538960044 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 538960044 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 609774472 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 609774472 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1148734516 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1148734516 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1148734516 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1148734516 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638400628 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638400628 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 959722740 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 959722740 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1598123368 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1598123368 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805232 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805232 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954580 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954580 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858125 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858125 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14726.891385 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14726.891385 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 25630.468328 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 25630.468328 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9793 # number of writebacks +system.cpu2.l1c.writebacks::total 9793 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36455 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36455 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23891 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23891 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60346 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60346 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60346 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60346 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9727 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9727 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5550 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5550 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15277 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535820289 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535820289 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 626605165 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 626605165 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162425454 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1162425454 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162425454 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1162425454 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 629981617 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 629981617 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 971621622 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 971621622 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1601603239 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1601603239 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807438 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807438 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952858 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952858 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859360 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859360 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859360 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859360 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14698.128899 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14698.128899 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26227.665857 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26227.665857 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19262.676134 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19262.676134 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19262.676134 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19262.676134 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 64766.281176 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64766.281176 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 175066.958919 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175066.958919 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 104837.549192 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 104837.549192 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 55095 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22209 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.627346 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13529 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22601 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.598602 # Average number of references to valid blocks. +system.cpu3.num_reads 99575 # number of read accesses completed +system.cpu3.num_writes 55091 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22304 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.069306 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13533 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22710 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.595905 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.627346 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.764897 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.764897 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338542 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338542 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8783 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8783 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1149 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1149 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9932 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9932 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9932 # number of overall hits -system.cpu3.l1c.overall_hits::total 9932 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36678 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36678 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23815 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23815 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60493 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60493 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60493 # number of overall misses -system.cpu3.l1c.overall_misses::total 60493 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 595385248 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 595385248 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 651992109 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 651992109 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1247377357 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1247377357 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1247377357 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1247377357 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45461 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45461 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24964 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70425 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70425 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70425 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70425 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806801 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806801 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953974 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858971 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858971 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858971 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858971 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16232.762092 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16232.762092 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27377.371782 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 27377.371782 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20620.193361 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20620.193361 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20620.193361 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20620.193361 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 774947 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.069306 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.765760 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.765760 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336765 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336765 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8633 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8633 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1152 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1152 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9785 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9785 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9785 # number of overall hits +system.cpu3.l1c.overall_hits::total 9785 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36428 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36428 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23860 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23860 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60288 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60288 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60288 # number of overall misses +system.cpu3.l1c.overall_misses::total 60288 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 584499068 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 584499068 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 664565432 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 664565432 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1249064500 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1249064500 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1249064500 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1249064500 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45061 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45061 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25012 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70073 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70073 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70073 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70073 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808415 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808415 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953942 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860360 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860360 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860360 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860360 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16045.324146 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16045.324146 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27852.700419 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 27852.700419 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20718.293856 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20718.293856 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20718.293856 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20718.293856 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 775679 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66468 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66211 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.658949 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.715259 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9869 # number of writebacks -system.cpu3.l1c.writebacks::total 9869 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36678 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36678 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23815 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60493 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60493 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60493 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60493 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 538014612 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 538014612 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 615289695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 615289695 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1153304307 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1153304307 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1153304307 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1153304307 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 640462998 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 640462998 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962755753 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962755753 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1603218751 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1603218751 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806801 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806801 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953974 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858971 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858971 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14668.591853 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14668.591853 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25836.224858 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25836.224858 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9857 # number of writebacks +system.cpu3.l1c.writebacks::total 9857 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36428 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36428 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23860 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60288 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60288 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60288 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60288 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9854 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9854 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5367 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5367 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15221 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 527611348 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 527611348 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 627817964 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 627817964 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155429312 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1155429312 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155429312 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1155429312 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639378023 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639378023 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962583192 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962583192 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1601961215 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1601961215 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808415 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808415 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953942 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860360 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860360 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860360 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860360 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14483.675964 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14483.675964 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 26312.571836 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 26312.571836 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19165.162420 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19165.162420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19165.162420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19165.162420 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 64885.125127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64885.125127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 179352.187814 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179352.187814 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 105246.778464 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 105246.778464 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99958 # number of read accesses completed -system.cpu4.num_writes 55186 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22162 # number of replacements -system.cpu4.l1c.tags.tagsinuse 390.917230 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13739 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22564 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.608890 # Average number of references to valid blocks. +system.cpu4.num_reads 99348 # number of read accesses completed +system.cpu4.num_writes 54723 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22403 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.522543 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13385 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587448 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 390.917230 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.763510 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.763510 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338274 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338274 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8951 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8951 # number of ReadReq hits +system.cpu4.l1c.tags.occ_blocks::cpu4 391.522543 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.764692 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.764692 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 382 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.746094 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337332 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337332 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8635 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8635 # number of ReadReq hits system.cpu4.l1c.WriteReq_hits::cpu4 1108 # number of WriteReq hits system.cpu4.l1c.WriteReq_hits::total 1108 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits -system.cpu4.l1c.overall_hits::total 10059 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36463 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36463 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23892 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23892 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60355 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60355 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60355 # number of overall misses -system.cpu4.l1c.overall_misses::total 60355 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 590532010 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 590532010 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 657391664 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 657391664 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1247923674 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1247923674 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1247923674 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1247923674 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45414 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45414 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25000 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25000 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70414 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70414 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70414 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70414 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.802902 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.802902 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955680 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.955680 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857145 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857145 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857145 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857145 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16195.376409 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16195.376409 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27515.137452 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 27515.137452 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20676.392577 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20676.392577 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20676.392577 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20676.392577 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 772044 # number of cycles access was blocked +system.cpu4.l1c.demand_hits::cpu4 9743 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9743 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9743 # number of overall hits +system.cpu4.l1c.overall_hits::total 9743 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36706 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36706 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23706 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23706 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60412 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60412 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60412 # number of overall misses +system.cpu4.l1c.overall_misses::total 60412 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 597809741 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 597809741 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 658168265 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 658168265 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1255978006 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1255978006 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1255978006 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1255978006 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45341 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45341 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24814 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24814 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70155 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70155 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809554 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.809554 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955348 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955348 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.861122 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.861122 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.861122 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.861122 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16286.431128 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16286.431128 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27763.784063 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 27763.784063 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20790.207343 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20790.207343 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20790.207343 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20790.207343 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 777995 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66046 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66371 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.689489 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.721912 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks -system.cpu4.l1c.writebacks::total 9680 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36463 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36463 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23892 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23892 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60355 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60355 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60355 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60355 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533535272 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533535272 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 620520370 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 620520370 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1154055642 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1154055642 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1154055642 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1154055642 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 636776082 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636776082 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 976656146 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 976656146 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1613432228 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1613432228 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.802902 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802902 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955680 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955680 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857145 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857145 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14632.237391 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14632.237391 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25971.888917 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25971.888917 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9776 # number of writebacks +system.cpu4.l1c.writebacks::total 9776 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36706 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36706 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23706 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23706 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60412 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60412 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60412 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60412 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9778 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5370 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5370 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15148 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15148 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 540346315 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 540346315 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 621672271 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 621672271 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1162018586 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1162018586 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1162018586 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1162018586 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 636494546 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636494546 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 958781259 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 958781259 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1595275805 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1595275805 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809554 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809554 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955348 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955348 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861122 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.861122 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861122 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.861122 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14720.926143 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14720.926143 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 26224.258458 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 26224.258458 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65094.553692 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65094.553692 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 178543.996089 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 178543.996089 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 105312.635661 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 105312.635661 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98793 # number of read accesses completed -system.cpu5.num_writes 54966 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22337 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.447401 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13310 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22755 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.584926 # Average number of references to valid blocks. +system.cpu5.num_reads 99076 # number of read accesses completed +system.cpu5.num_writes 54802 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22210 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.101349 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13412 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22600 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.593451 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.447401 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.766499 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 335862 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 335862 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8554 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8554 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1127 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1127 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9681 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9681 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9681 # number of overall hits -system.cpu5.l1c.overall_hits::total 9681 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36144 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36144 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24019 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24019 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60163 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60163 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60163 # number of overall misses -system.cpu5.l1c.overall_misses::total 60163 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 586243376 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 586243376 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 664085386 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 664085386 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1250328762 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1250328762 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1250328762 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1250328762 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44698 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44698 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25146 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25146 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69844 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69844 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69844 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69844 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808627 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808627 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955182 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.955182 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.861391 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.861391 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.861391 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.861391 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16219.659584 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16219.659584 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27648.336151 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 27648.336151 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20782.353972 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20782.353972 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20782.353972 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20782.353972 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 771700 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.101349 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765823 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765823 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 335763 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 335763 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8687 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8687 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1188 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9875 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9875 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9875 # number of overall hits +system.cpu5.l1c.overall_hits::total 9875 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36386 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36386 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23589 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23589 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59975 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59975 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59975 # number of overall misses +system.cpu5.l1c.overall_misses::total 59975 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 587220514 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 587220514 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 653847941 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 653847941 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1241068455 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1241068455 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1241068455 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1241068455 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45073 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45073 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24777 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24777 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69850 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69850 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69850 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69850 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807268 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952052 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952052 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858626 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858626 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858626 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858626 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16138.638872 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16138.638872 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27718.340794 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 27718.340794 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20693.096373 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20693.096373 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20693.096373 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20693.096373 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 773798 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 65809 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 65921 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.726360 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.738262 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9916 # number of writebacks -system.cpu5.l1c.writebacks::total 9916 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36144 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24019 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24019 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60163 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60163 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60163 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60163 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 529678552 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 529678552 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 626959212 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 626959212 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156637764 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1156637764 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156637764 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1156637764 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632837521 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632837521 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 970316626 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 970316626 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1603154147 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1603154147 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808627 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808627 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955182 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955182 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.861391 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.861391 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14654.674413 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14654.674413 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26102.635913 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26102.635913 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9805 # number of writebacks +system.cpu5.l1c.writebacks::total 9805 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36386 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36386 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23589 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23589 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59975 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59975 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59975 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59975 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9927 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9927 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5497 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5497 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15424 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15424 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 530387712 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 530387712 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 617501507 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 617501507 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1147889219 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1147889219 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1147889219 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1147889219 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 644126924 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 644126924 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 971277615 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 971277615 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1615404539 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1615404539 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807268 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952052 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952052 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858626 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858626 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858626 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858626 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14576.697411 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14576.697411 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26177.519479 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26177.519479 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19139.461759 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19139.461759 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 64886.362849 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64886.362849 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 176692.307622 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176692.307622 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 104733.178099 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 104733.178099 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99383 # number of read accesses completed -system.cpu6.num_writes 54752 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22371 # number of replacements -system.cpu6.l1c.tags.tagsinuse 391.299314 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13429 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.589975 # Average number of references to valid blocks. +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 55196 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22166 # number of replacements +system.cpu6.l1c.tags.tagsinuse 390.500017 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13797 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22571 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.611271 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 391.299314 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.764256 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.764256 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 336995 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 336995 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1088 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1088 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9819 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9819 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9819 # number of overall hits -system.cpu6.l1c.overall_hits::total 9819 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36545 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36545 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23737 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23737 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60282 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60282 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60282 # number of overall misses -system.cpu6.l1c.overall_misses::total 60282 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 590611551 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 590611551 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 651380889 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 651380889 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1241992440 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1241992440 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1241992440 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1241992440 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45276 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45276 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24825 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24825 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70101 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70101 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70101 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70101 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807161 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807161 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956173 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956173 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859931 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859931 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859931 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859931 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16161.213600 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16161.213600 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27441.584404 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 27441.584404 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 20603.039713 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 20603.039713 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 20603.039713 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 20603.039713 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 771561 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 390.500017 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.762695 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.762695 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338189 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338189 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8999 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8999 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1089 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1089 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 10088 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 10088 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 10088 # number of overall hits +system.cpu6.l1c.overall_hits::total 10088 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36489 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36489 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23831 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23831 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60320 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60320 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60320 # number of overall misses +system.cpu6.l1c.overall_misses::total 60320 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 591265797 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 591265797 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 669884291 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 669884291 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1261150088 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1261150088 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1261150088 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1261150088 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45488 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45488 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24920 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24920 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70408 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70408 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70408 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70408 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.802168 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.802168 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956300 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.956300 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.856721 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.856721 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.856721 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.856721 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16203.946313 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16203.946313 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28109.785196 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28109.785196 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20907.660610 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20907.660610 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20907.660610 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20907.660610 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 779089 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66088 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66360 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.674752 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.740341 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9782 # number of writebacks -system.cpu6.l1c.writebacks::total 9782 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36545 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36545 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23737 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23737 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60282 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60282 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60282 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60282 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 533644023 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 533644023 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 614831387 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 614831387 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148475410 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1148475410 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148475410 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1148475410 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 641180935 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 641180935 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 971245186 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 971245186 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1612426121 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1612426121 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807161 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807161 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956173 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956173 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859931 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859931 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14602.381256 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14602.381256 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25901.815183 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25901.815183 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9642 # number of writebacks +system.cpu6.l1c.writebacks::total 9642 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36489 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36489 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23831 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60320 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60320 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60320 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60320 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9769 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9769 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5428 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15197 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15197 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 534211155 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 534211155 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 633170857 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 633170857 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1167382012 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1167382012 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1167382012 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1167382012 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 633249047 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 633249047 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 972097686 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 972097686 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1605346733 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1605346733 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.802168 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.802168 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956300 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956300 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.856721 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.856721 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.856721 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.856721 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14640.334210 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14640.334210 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 26569.210566 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 26569.210566 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19353.150066 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19353.150066 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 64822.299826 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64822.299826 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 179089.477892 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179089.477892 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 105635.765809 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 105635.765809 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99477 # number of read accesses completed -system.cpu7.num_writes 54915 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22352 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.525005 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13561 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22758 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.595878 # Average number of references to valid blocks. +system.cpu7.num_reads 99558 # number of read accesses completed +system.cpu7.num_writes 55171 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22301 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.314330 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13511 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22696 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.595303 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.525005 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.764697 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.764697 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337629 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337629 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8790 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8790 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1137 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1137 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9927 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9927 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9927 # number of overall hits -system.cpu7.l1c.overall_hits::total 9927 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36477 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36477 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23844 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23844 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60321 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60321 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60321 # number of overall misses -system.cpu7.l1c.overall_misses::total 60321 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 593716610 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 593716610 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 651325348 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 651325348 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1245041958 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1245041958 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1245041958 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1245041958 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45267 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45267 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24981 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24981 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70248 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70248 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70248 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70248 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805819 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805819 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954485 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954485 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858686 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858686 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858686 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858686 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16276.464896 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16276.464896 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27316.110887 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 27316.110887 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 20640.273835 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 20640.273835 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 20640.273835 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 20640.273835 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 768557 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 392.314330 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766239 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766239 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337937 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337937 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8724 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8724 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1105 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1105 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9829 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9829 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9829 # number of overall hits +system.cpu7.l1c.overall_hits::total 9829 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36568 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36568 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23906 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23906 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses +system.cpu7.l1c.overall_misses::total 60474 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 596090233 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 596090233 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 664580608 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 664580608 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1260670841 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1260670841 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1260670841 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1260670841 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45292 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45292 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25011 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25011 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70303 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70303 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70303 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70303 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807383 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807383 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955819 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955819 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860191 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860191 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860191 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860191 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16300.870515 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16300.870515 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27799.740986 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 27799.740986 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20846.493386 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20846.493386 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20846.493386 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20846.493386 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 776345 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 65923 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66228 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.658405 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.722308 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9939 # number of writebacks -system.cpu7.l1c.writebacks::total 9939 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36477 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23844 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23844 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60321 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60321 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 536729312 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 536729312 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 614614324 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 614614324 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1151343636 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1151343636 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1151343636 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1151343636 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 635643033 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 635643033 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 965131654 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 965131654 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1600774687 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1600774687 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805819 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805819 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954485 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954485 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858686 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858686 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14714.184609 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14714.184609 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25776.477269 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25776.477269 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9814 # number of writebacks +system.cpu7.l1c.writebacks::total 9814 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36568 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36568 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23906 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23906 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9700 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9700 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5336 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5336 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15036 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15036 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538984883 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538984883 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 627714786 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 627714786 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1166699669 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1166699669 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1166699669 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1166699669 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 629180127 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 629180127 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 945700289 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 945700289 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574880416 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574880416 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807383 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807383 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955819 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955819 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860191 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860191 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860191 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860191 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14739.249699 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14739.249699 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 26257.625115 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 26257.625115 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19292.583077 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19292.583077 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19292.583077 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19292.583077 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 64863.930619 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64863.930619 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 177230.189093 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 177230.189093 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 104740.650173 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 104740.650173 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13851 # number of replacements -system.l2c.tags.tagsinuse 783.697862 # Cycle average of tags in use -system.l2c.tags.total_refs 151322 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14625 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.346803 # Average number of references to valid blocks. +system.l2c.tags.replacements 14031 # number of replacements +system.l2c.tags.tagsinuse 784.967814 # Cycle average of tags in use +system.l2c.tags.total_refs 150152 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14812 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.137186 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 724.401984 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.094586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.546674 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.606935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.397120 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.288170 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.917650 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.470007 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.974735 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.707424 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006928 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007370 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007429 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007224 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007117 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007732 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007295 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006811 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765330 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 774 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 649 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1983958 # Number of tag accesses -system.l2c.tags.data_accesses 1983958 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10778 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10851 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10733 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10660 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10974 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86237 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76857 # number of Writeback hits -system.l2c.Writeback_hits::total 76857 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 346 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 384 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 373 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 367 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 376 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2885 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1990 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1993 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1893 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2001 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2049 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1965 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1890 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15680 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12610 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12768 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12844 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12641 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12783 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12864 # number of demand (read+write) hits -system.l2c.demand_hits::total 101917 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12610 # number of overall hits -system.l2c.overall_hits::cpu1 12768 # number of overall hits -system.l2c.overall_hits::cpu2 12844 # number of overall hits -system.l2c.overall_hits::cpu3 12641 # number of overall hits -system.l2c.overall_hits::cpu4 12783 # number of overall hits -system.l2c.overall_hits::cpu5 12782 # number of overall hits -system.l2c.overall_hits::cpu6 12625 # number of overall hits -system.l2c.overall_hits::cpu7 12864 # number of overall hits -system.l2c.overall_hits::total 101917 # number of overall hits -system.l2c.ReadReq_misses::cpu0 698 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 756 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 731 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 765 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 706 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 759 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 730 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 718 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5863 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1969 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1976 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1906 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1935 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2000 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15706 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4442 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4288 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4325 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4406 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4415 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4506 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4417 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4371 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35170 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5140 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5056 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5171 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5121 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5265 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5147 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5089 # number of demand (read+write) misses -system.l2c.demand_misses::total 41033 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5140 # number of overall misses -system.l2c.overall_misses::cpu1 5044 # number of overall misses -system.l2c.overall_misses::cpu2 5056 # number of overall misses -system.l2c.overall_misses::cpu3 5171 # number of overall misses -system.l2c.overall_misses::cpu4 5121 # number of overall misses -system.l2c.overall_misses::cpu5 5265 # number of overall misses -system.l2c.overall_misses::cpu6 5147 # number of overall misses -system.l2c.overall_misses::cpu7 5089 # number of overall misses -system.l2c.overall_misses::total 41033 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 43733919 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 46361427 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 45254929 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 46924929 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 44013419 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 46972420 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 45169428 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 45070420 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 363500891 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 59896998 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 56953495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 54104996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 56752496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 58374994 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 58176496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 54809998 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 58271994 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 457341467 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 244729947 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 236328444 # 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number of overall miss cycles -system.l2c.overall_miss_latency::total 2299716439 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11409 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11534 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11582 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11513 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11488 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11492 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11390 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 92100 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76857 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76857 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2315 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2360 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2279 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2302 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2376 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2355 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2322 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18591 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6341 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6278 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6318 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6299 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6416 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6555 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6382 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6261 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50850 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17812 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17900 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17812 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17904 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18047 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17772 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17953 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142950 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17812 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17900 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17812 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17904 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18047 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17772 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17953 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142950 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.061180 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.065545 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.063115 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.066447 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.061455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.066046 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.064091 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.061410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.063659 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.850540 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.837288 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.836332 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.840573 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.841751 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.854352 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.841805 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.855728 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.844817 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.700520 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.683020 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.684552 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.699476 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.688123 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.687414 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692103 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.698131 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.691642 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.289577 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.283180 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.282458 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.290310 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.286025 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291738 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.289613 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.283462 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.287044 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.289577 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.283180 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.282458 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.290310 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.286025 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291738 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.289613 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.283462 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.287044 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 62656.044413 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61324.638889 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 61908.247606 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61339.776471 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 62341.953258 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 61887.246377 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61875.928767 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 62772.172702 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61999.128603 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 30420.009142 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28822.618927 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28386.671563 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29329.455297 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29187.497000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28914.759443 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28532.013535 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29326.620030 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29118.901503 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 55094.540072 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 55113.909515 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 55006.230520 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 55044.244666 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 55035.773952 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 55082.876387 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 55162.311976 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54882.624800 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55053.043730 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 56121.374708 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 56044.780135 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 56004.128956 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55975.608393 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 56043.030853 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 56063.791263 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 56114.505537 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55995.750246 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 56045.535033 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 56121.374708 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 56044.780135 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 56004.128956 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55975.608393 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 56043.030853 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 56063.791263 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 56114.505537 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55995.750246 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 56045.535033 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 17878 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 723.923615 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.649200 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 8.016952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.636701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.493514 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.626072 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.131481 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.354188 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 8.136089 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.706957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007470 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007829 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007458 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007318 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007447 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006964 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007945 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.766570 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 781 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 686 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.762695 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1978435 # Number of tag accesses +system.l2c.tags.data_accesses 1978435 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10607 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10697 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10702 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 11123 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10597 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10776 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10709 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85924 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 76544 # number of Writeback hits +system.l2c.Writeback_hits::total 76544 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 268 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 299 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 302 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 259 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 274 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 287 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 307 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2268 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1803 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1734 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1772 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1671 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1762 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1808 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1767 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1864 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14181 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12516 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12341 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12469 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12373 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12885 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12405 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12543 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12573 # number of demand (read+write) hits +system.l2c.demand_hits::total 100105 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12516 # number of overall hits +system.l2c.overall_hits::cpu1 12341 # number of overall hits +system.l2c.overall_hits::cpu2 12469 # number of overall hits +system.l2c.overall_hits::cpu3 12373 # number of overall hits +system.l2c.overall_hits::cpu4 12885 # number of overall hits +system.l2c.overall_hits::cpu5 12405 # number of overall hits +system.l2c.overall_hits::cpu6 12543 # number of overall hits +system.l2c.overall_hits::cpu7 12573 # number of overall hits +system.l2c.overall_hits::total 100105 # number of overall hits +system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 785 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 742 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 727 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 760 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 712 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 735 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 780 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5986 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1959 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2034 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2073 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2095 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2075 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1984 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2104 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2050 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16374 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4569 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4626 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4511 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4582 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4471 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4493 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4628 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4552 # 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number of overall misses +system.l2c.overall_misses::cpu4 5231 # number of overall misses +system.l2c.overall_misses::cpu5 5205 # number of overall misses +system.l2c.overall_misses::cpu6 5363 # number of overall misses +system.l2c.overall_misses::cpu7 5332 # number of overall misses +system.l2c.overall_misses::total 42418 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 46187916 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 48036419 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 45900428 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 44726930 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 46758924 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 44218925 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 45379928 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 48529420 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 369738890 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 57866497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 60355991 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 61207994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 63805822 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 62183492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 61767496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 63498496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 63160496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 493846284 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 251689442 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 254959951 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 248273936 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 252714443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 246321934 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 247674443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 255400930 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 250363448 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2007398527 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 297877358 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 302996370 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 294174364 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 297441373 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 293080858 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 291893368 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 300780858 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 298892868 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2377137417 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 297877358 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 302996370 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 294174364 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 297441373 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 293080858 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 291893368 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 300780858 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 298892868 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2377137417 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11458 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11392 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11439 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11883 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11309 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11511 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91910 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 76544 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 76544 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2231 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2302 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2372 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2397 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2334 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2258 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2391 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2357 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18642 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6372 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6360 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6283 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6253 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6233 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6301 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6395 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6416 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50613 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17830 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17752 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17722 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17682 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18116 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17610 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17906 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17905 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 142523 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17830 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17752 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17722 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17682 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18116 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17610 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17906 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17905 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 142523 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.065020 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.068908 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064866 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.063610 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.063957 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.062959 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.063852 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.067891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.065129 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.878082 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.883579 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.873946 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.874009 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.889032 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.878654 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.879967 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.869750 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.878339 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.717043 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.727358 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.717969 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.732768 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717311 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.713061 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.723690 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.709476 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.719815 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.298037 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.304811 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.296411 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.300249 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.288750 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.295571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.299509 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.297794 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.297622 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.298037 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.304811 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.296411 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.300249 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.288750 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.295571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.299509 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.297794 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.297622 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 61997.202685 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61192.890446 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61860.415094 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61522.599725 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61524.900000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 62105.231742 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61741.398639 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 62217.205128 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61767.271968 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29538.793772 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29673.545231 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29526.287506 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30456.239618 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 29967.947952 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 31132.810484 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30179.893536 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 30809.998049 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 30160.393551 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55086.330050 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55114.559230 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55037.449789 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55153.741379 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55093.252964 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55124.514356 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55186.026361 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55000.757469 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55099.871734 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56055.204742 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55996.372205 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56001.211498 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 56025.875494 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56027.692219 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56079.417483 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56084.441171 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 56056.426857 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56040.770828 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56055.204742 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55996.372205 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56001.211498 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 56025.875494 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56027.692219 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56079.417483 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56084.441171 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 56056.426857 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56040.770828 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 18299 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3319 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3476 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.386562 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.264384 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6553 # number of writebacks -system.l2c.writebacks::total 6553 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 8 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6720 # number of writebacks +system.l2c.writebacks::total 6720 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 3 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 48 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 108 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 690 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 748 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 723 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 759 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 699 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 748 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 725 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 711 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5803 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1969 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1976 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1906 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1935 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1999 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2012 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1921 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1986 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15704 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4438 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4282 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4318 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4399 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4410 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4497 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4413 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4365 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35122 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5128 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5030 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5041 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5158 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5109 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5245 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5138 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5076 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40925 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5128 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5030 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5041 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5158 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5109 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5245 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5138 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5076 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40925 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 35173417 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 37031918 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 36254417 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 37641417 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 35371412 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 37570056 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 36289420 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 36247403 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 291579460 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 83090959 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 83391451 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80567464 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 81939961 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 84801962 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 85113946 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 81126982 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 83903452 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 663936177 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 190977391 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 184459864 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 185520379 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 189280870 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 189565364 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 193586876 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 190188358 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 187005383 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1510584485 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 226150808 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 221491782 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 221774796 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 226922287 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 224936776 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 231156932 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 226477778 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 223252786 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1802163945 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 226150808 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 221491782 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 221774796 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 226922287 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 224936776 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 231156932 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 226477778 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 223252786 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1802163945 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 423951568 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 418494765 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 418742272 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 420173606 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 417698791 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 416045242 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 420505761 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416931790 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3352543795 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 241936896 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 242321875 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237941390 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 239219888 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241365909 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 242888399 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 243671384 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 242767880 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1932113621 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 665888464 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 660816640 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 656683662 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 659393494 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 659064700 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 658933641 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 664177145 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 659699670 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5284657416 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060479 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064852 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062424 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.065925 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060846 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.065089 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063652 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060811 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.063008 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.850540 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.837288 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.836332 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.840573 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.841330 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.854352 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841805 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.855297 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.844710 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.699890 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682064 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.683444 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.698365 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687344 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.686041 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691476 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.697173 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.690698 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.286289 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.286289 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50975.966667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49507.911765 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50144.421853 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49593.434783 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50602.878398 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.347594 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50054.372414 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50980.876231 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 50246.331208 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42199.572880 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42202.151316 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42270.442812 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42346.233075 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42422.192096 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42303.154076 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42231.640812 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42247.458207 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42278.156966 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43032.309824 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43077.969173 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42964.423113 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43028.158672 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42985.343311 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43048.004447 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43097.293904 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42842.012142 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 43009.637407 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 35 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 738 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 776 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 734 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 724 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 745 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 706 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 731 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 774 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5928 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1959 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2034 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2073 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2095 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1984 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2101 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2050 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16370 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4565 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4622 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4503 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4580 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4467 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4488 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4624 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4548 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 36397 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5303 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5398 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5237 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5304 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5212 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5194 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5355 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5322 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42325 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5303 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5398 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5237 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5304 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5212 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5194 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5355 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5322 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42325 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9834 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 9869 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9727 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9854 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9778 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9927 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9769 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9700 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 78458 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5517 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5460 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5550 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5367 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5370 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5497 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5427 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5336 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43524 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15351 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15329 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15277 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15221 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15148 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15424 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15196 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15036 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 121982 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 37081908 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 38421892 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 36752422 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 35943926 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 37213921 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 35460411 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 36445418 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 38946899 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 296266797 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 82978964 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 86239947 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 87750966 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 88854787 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 87819107 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83999460 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 88854959 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 87064968 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 693563158 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 196462368 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 199050885 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193595340 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 197409379 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 192312836 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 193341369 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 199367330 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 195358866 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1566898373 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 233544276 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 237472777 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 230347762 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 233353305 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 229526757 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 228801780 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 235812748 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 234305765 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1863165170 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 233544276 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 237472777 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 230347762 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 233353305 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 229526757 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 228801780 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 235812748 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 234305765 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1863165170 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 419590422 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 420411799 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 414525738 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 420114597 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 417359247 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 423042782 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 416304244 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 412865244 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3344214073 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 244799897 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 243732417 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 247505386 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 237594430 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 238425396 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 244815873 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 242422406 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 237975886 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1937271691 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 664390319 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 664144216 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 662031124 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 657709027 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 655784643 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 667858655 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 658726650 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 650841130 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5281485764 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064409 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068118 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064166 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.063348 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.062695 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.062428 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063504 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067369 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.064498 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.878082 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883579 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.873946 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.874009 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.888603 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878654 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.878712 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.869750 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.878125 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.716416 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726730 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.716696 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.732448 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716669 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.712268 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723065 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.708853 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.719124 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.297420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.304078 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.295508 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.299966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.287701 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.294946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.299062 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.297235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.296970 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.297420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.304078 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.295508 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.299966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.287701 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.294946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.299062 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.297235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.296970 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50246.487805 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49512.747423 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50071.419619 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49646.306630 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49951.571812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.211048 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49856.932969 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50318.990956 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49977.529858 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42357.817254 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42399.187316 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42330.422576 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42412.786158 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42342.867406 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42338.437500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42291.746311 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42470.716098 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42367.938790 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43036.663308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43065.963868 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42992.524983 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43102.484498 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43051.899709 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43079.627674 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43115.772059 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42954.895778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43050.206693 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 44040.029417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43992.733790 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43984.678633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43995.721154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 44038.134497 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 44051.170581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 44035.994024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 44025.885945 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 44020.441110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 44040.029417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43992.733790 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43984.678633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43995.721154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 44038.134497 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 44051.170581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 44035.994024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 44025.885945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 44020.441110 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42667.319707 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42599.229811 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42615.990336 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42633.914857 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42683.498364 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42615.370404 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42614.826901 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42563.427216 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42624.258495 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 44371.922603 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 44639.636813 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 44595.565045 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 44269.504379 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44399.515084 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44536.269420 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 44669.689700 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 44598.179535 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 44510.423927 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 43279.937398 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 43325.997521 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 43335.152451 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 43210.631824 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 43291.830143 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 43299.964665 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 43348.687155 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 43285.523410 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 43297.255038 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 84510 # Transaction distribution -system.membus.trans_dist::ReadResp 84504 # Transaction distribution -system.membus.trans_dist::WriteReq 43512 # Transaction distribution -system.membus.trans_dist::WriteResp 43509 # Transaction distribution -system.membus.trans_dist::Writeback 6553 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58529 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47554 # Transaction distribution -system.membus.trans_dist::ReadExReq 49190 # Transaction distribution -system.membus.trans_dist::ReadExResp 3281 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 421142 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1121847 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1121847 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56880 # Total snoops (count) -system.membus.snoop_fanout::samples 123632 # Request fanout histogram +system.membus.trans_dist::ReadReq 84372 # Transaction distribution +system.membus.trans_dist::ReadResp 84365 # Transaction distribution +system.membus.trans_dist::WriteReq 43521 # Transaction distribution +system.membus.trans_dist::WriteResp 43519 # Transaction distribution +system.membus.trans_dist::Writeback 6720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60428 # Transaction distribution +system.membus.trans_dist::UpgradeResp 49463 # Transaction distribution +system.membus.trans_dist::ReadExReq 49409 # Transaction distribution +system.membus.trans_dist::ReadExResp 3325 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 425122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 425122 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1143411 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1143411 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57048 # Total snoops (count) +system.membus.snoop_fanout::samples 253034 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123632 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253034 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123632 # Request fanout histogram -system.membus.reqLayer0.occupancy 285799779 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 60.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 306149550 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 64.7 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 370575 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370557 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 7 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43514 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43509 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 76857 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29562 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29559 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161030 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161024 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120575 # Packet count per connected master and slave (bytes) +system.membus.snoop_fanout::total 253034 # Request fanout histogram +system.membus.reqLayer0.occupancy 288296633 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 60.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 308136269 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 65.1 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 369990 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 369967 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43524 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43518 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 76544 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29606 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29605 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161002 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 160999 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120638 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120231 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120586 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120766 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120839 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 965293 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1758906 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1769834 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1777815 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1771618 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1766732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1765164 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14189303 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 320901 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 563826 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120464 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120699 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120288 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120457 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120419 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 963786 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1770551 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1763883 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1765044 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785450 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756799 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1766043 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1776312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14141746 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 320975 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 687560 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1694,29 +1769,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 563826 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 687560 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 563826 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 445759226 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 94.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101149991 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 687560 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 445191055 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 94.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101323906 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101191512 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101359906 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 101013875 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101243878 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101648274 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 21.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101307289 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 101066643 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101367492 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101134998 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101213033 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 100955896 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101182766 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101242964 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 101290842 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 313b6d716..d571b5762 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011500 # Number of ticks simulated final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1111911 # Simulator instruction rate (inst/s) -host_op_rate 1421979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 767686935 # Simulator tick rate (ticks/s) -host_mem_usage 303468 # Number of bytes of host memory used -host_seconds 63.78 # Real time elapsed on the host +host_inst_rate 1547474 # Simulator instruction rate (inst/s) +host_op_rate 1979004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1068409192 # Simulator tick rate (ticks/s) +host_mem_usage 311136 # Number of bytes of host memory used +host_seconds 45.83 # Real time elapsed on the host sim_insts 70913182 # Number of instructions simulated sim_ops 90688137 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 120930619 # Request fanout histogram -system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram +system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::3 78145069 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::1 78145069 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 120930619 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 91d42cd77..90d753109 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -597,17 +597,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 307145 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 772df96ed..37a976075 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491500 # Number of ticks simulated final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1304038 # Simulator instruction rate (inst/s) -host_op_rate 1374666 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 753711187 # Simulator tick rate (ticks/s) -host_mem_usage 298984 # Number of bytes of host memory used -host_seconds 132.14 # Real time elapsed on the host +host_inst_rate 1968226 # Simulator instruction rate (inst/s) +host_op_rate 2074827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1137600357 # Simulator tick rate (ticks/s) +host_mem_usage 306644 # Number of bytes of host memory used +host_seconds 87.55 # Real time elapsed on the host sim_insts 172317410 # Number of instructions simulated sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 230024467 # Request fanout histogram -system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram +system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::3 189860052 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 230024467 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index e97c269ba..c495da061 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -585,17 +585,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 7b91ddd8b..b19da3109 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1264426 # Simulator instruction rate (inst/s) -host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1257935779 # Simulator tick rate (ticks/s) -host_mem_usage 324376 # Number of bytes of host memory used -host_seconds 104.45 # Real time elapsed on the host +host_inst_rate 851639 # Simulator instruction rate (inst/s) +host_op_rate 1427424 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 847267215 # Simulator tick rate (ticks/s) +host_mem_usage 272248 # Number of bytes of host memory used +host_seconds 155.08 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,33 +35,6 @@ system.physmem.bw_write::total 759720678 # Wr system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 230176372 # Transaction distribution -system.membus.trans_dist::ReadResp 230176372 # Transaction distribution -system.membus.trans_dist::WriteReq 20515731 # Transaction distribution -system.membus.trans_dist::WriteResp 20515731 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 250692103 # Request fanout histogram -system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram -system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 250692103 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls @@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.membus.trans_dist::ReadReq 230176372 # Transaction distribution +system.membus.trans_dist::ReadResp 230176372 # Transaction distribution +system.membus.trans_dist::WriteReq 20515731 # Transaction distribution +system.membus.trans_dist::WriteResp 20515731 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 250692103 # Request fanout histogram +system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram +system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 250692103 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 0e62e6e73..af03b59c5 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957500 # Number of ticks simulated final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 722726 # Simulator instruction rate (inst/s) -host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1373280924 # Simulator tick rate (ticks/s) -host_mem_usage 338728 # Number of bytes of host memory used -host_seconds 182.74 # Real time elapsed on the host +host_inst_rate 582427 # Simulator instruction rate (inst/s) +host_op_rate 976201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1106694320 # Simulator tick rate (ticks/s) +host_mem_usage 282016 # Number of bytes of host memory used +host_seconds 226.76 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -446,17 +446,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6606 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |