diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/quick/se | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/quick/se')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt | 42 | ||||
| -rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt | 2854 |
2 files changed, 1445 insertions, 1451 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 076c105ad..9e326e98d 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.019665 # Number of seconds simulated -sim_ticks 19665440 # Number of ticks simulated -final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.006104 # Number of seconds simulated +sim_ticks 6103915 # Number of ticks simulated +final_tick 6103915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 178903 # Simulator tick rate (ticks/s) -host_mem_usage 378856 # Number of bytes of host memory used -host_seconds 109.92 # Real time elapsed on the host +host_tick_rate 78453 # Simulator tick rate (ticks/s) +host_mem_usage 374396 # Number of bytes of host memory used +host_seconds 77.80 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99534 # number of read accesses completed -system.cpu0.num_writes 53920 # number of write accesses completed +system.cpu0.num_reads 99027 # number of read accesses completed +system.cpu0.num_writes 53493 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99604 # number of read accesses completed -system.cpu1.num_writes 53779 # number of write accesses completed +system.cpu1.num_reads 98254 # number of read accesses completed +system.cpu1.num_writes 52787 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99103 # number of read accesses completed -system.cpu2.num_writes 53314 # number of write accesses completed +system.cpu2.num_reads 99047 # number of read accesses completed +system.cpu2.num_writes 53306 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99223 # number of read accesses completed -system.cpu3.num_writes 53188 # number of write accesses completed +system.cpu3.num_reads 98414 # number of read accesses completed +system.cpu3.num_writes 53420 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53373 # number of write accesses completed +system.cpu4.num_writes 53741 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99316 # number of read accesses completed -system.cpu5.num_writes 53693 # number of write accesses completed +system.cpu5.num_reads 98111 # number of read accesses completed +system.cpu5.num_writes 53002 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99832 # number of read accesses completed -system.cpu6.num_writes 53341 # number of write accesses completed +system.cpu6.num_reads 99154 # number of read accesses completed +system.cpu6.num_writes 52587 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99257 # number of read accesses completed -system.cpu7.num_writes 53656 # number of write accesses completed +system.cpu7.num_reads 99215 # number of read accesses completed +system.cpu7.num_writes 53364 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 1fe48d0c8..0a33e618b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,640 +1,634 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000224 # Number of seconds simulated -sim_ticks 223713460 # Number of ticks simulated -final_tick 223713460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000247 # Number of seconds simulated +sim_ticks 246648467 # Number of ticks simulated +final_tick 246648467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1721618 # Simulator tick rate (ticks/s) -host_mem_usage 347508 # Number of bytes of host memory used -host_seconds 129.94 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 81065 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82807 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 84800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 80115 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83878 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 83050 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 84723 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 83101 # Number of bytes read from this memory -system.physmem.bytes_read::total 663539 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 423360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5290 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5393 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5404 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5324 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5344 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5398 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5445 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5412 # Number of bytes written to this memory -system.physmem.bytes_written::total 466370 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11135 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11041 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11139 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11029 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88727 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6615 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5290 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5393 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5404 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5324 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5344 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5398 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5445 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5412 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49625 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 362360852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 370147599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 379056316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 358114349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 374934973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 371233810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 378712126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 371461780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2966021803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1892420778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 23646320 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 24106730 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 24155900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 23798300 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 23887700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 24129080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 24339170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 24191660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2084675638 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1892420778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 386007172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 394254329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 403212216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 381912648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 398822673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 395362890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 403051296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 395653440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5050697441 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 13635 # number of replacements -system.l2c.tagsinuse 790.382632 # Cycle average of tags in use -system.l2c.total_refs 148986 # Total number of references to valid blocks. -system.l2c.sampled_refs 14447 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.312591 # Average number of references to valid blocks. +host_tick_rate 1526116 # Simulator tick rate (ticks/s) +host_mem_usage 347672 # Number of bytes of host memory used +host_seconds 161.62 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 85584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 85024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 83876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80921 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79699 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 87892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 84658 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 85643 # Number of bytes read from this memory +system.physmem.bytes_read::total 673297 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 432320 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5346 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5458 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5415 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5191 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5426 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5272 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5284 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5390 # Number of bytes written to this memory +system.physmem.bytes_written::total 475102 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11251 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10988 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88405 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6755 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5346 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5415 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5191 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5272 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5284 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5390 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 346987764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 344717326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 340062929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 328082315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 323127895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 356345211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 343233433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 347226971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2729783843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1752777973 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 21674572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 22128660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 21954323 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 21046147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 21998920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 21374550 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 21423202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 21852964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1926231311 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1752777973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 368662336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 366845986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 362017251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 349128462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 345126816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 377719761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 364656635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 369079934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4656015154 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 13761 # number of replacements +system.l2c.tagsinuse 783.393170 # Cycle average of tags in use +system.l2c.total_refs 148641 # Total number of references to valid blocks. +system.l2c.sampled_refs 14595 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.184378 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 735.582494 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 6.455373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 6.652747 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 6.865494 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 6.639169 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.152690 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.266868 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.044725 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 6.723074 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.718342 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.006304 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.006497 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.006705 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.006484 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.006985 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007097 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.006880 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.006566 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.771858 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10736 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10598 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10639 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10768 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85297 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 74602 # number of Writeback hits -system.l2c.Writeback_hits::total 74602 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 364 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 337 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 366 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 372 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 359 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 320 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2793 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1921 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1802 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1826 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1884 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1935 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1883 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1847 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15016 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12437 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12615 # number of demand (read+write) hits -system.l2c.demand_hits::total 100313 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12657 # number of overall hits -system.l2c.overall_hits::cpu1 12416 # number of overall hits -system.l2c.overall_hits::cpu2 12424 # number of overall hits -system.l2c.overall_hits::cpu3 12574 # number of overall hits -system.l2c.overall_hits::cpu4 12523 # number of overall hits -system.l2c.overall_hits::cpu5 12437 # number of overall hits -system.l2c.overall_hits::cpu6 12667 # number of overall hits -system.l2c.overall_hits::cpu7 12615 # number of overall hits -system.l2c.overall_hits::total 100313 # number of overall hits -system.l2c.ReadReq_misses::cpu0 732 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 746 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 787 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 736 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 779 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 768 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 802 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 756 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6106 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1954 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1934 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2007 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1961 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1921 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2008 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1917 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15600 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4348 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4389 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4257 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4350 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4337 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4234 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4290 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34525 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5080 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5135 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5044 # 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number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1902 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15079 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4399 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4186 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4344 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4286 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4382 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4394 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4423 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34643 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5175 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 4974 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5108 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 4963 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 54472253 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 52324574 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 51552168 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 422857100 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 245296624 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 234887322 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 237706545 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 232669020 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 238760287 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 246249803 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 240187312 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 245760610 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1921517523 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 312211900 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 301982332 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 309669898 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 300471660 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 301263060 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 316044007 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 312159402 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 317112939 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2470915198 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 312211900 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11599 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11449 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91345 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 74327 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 74327 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2165 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2222 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2184 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2268 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2229 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2221 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2217 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17792 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6318 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6062 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6256 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6098 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6213 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6254 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6254 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6215 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49670 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17644 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17486 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17622 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17663 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17400 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17853 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu6 17703 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17661 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 140944 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17737 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17551 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17468 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17652 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17542 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu7 17644 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141015 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17644 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17486 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17622 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17663 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17400 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17853 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu6 17703 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17661 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 140944 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.063830 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.065669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.069126 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.064607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068226 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.068146 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.069221 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.065602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.842968 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.853486 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.856229 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851128 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.839965 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.843697 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.842267 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.855726 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.848149 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.693572 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.708932 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.699819 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.692530 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.697786 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.691486 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692169 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.699039 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.696898 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.286407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.292576 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.288757 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.286784 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.290562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291016 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.284472 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.285714 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.288278 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.286407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.292576 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.288757 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.286784 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.290562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291016 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.284472 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.285714 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.288278 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 49429.372951 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 49725.445040 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 49351.857687 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 49348.440217 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 49620.612323 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 49455.048177 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 49767.672070 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 49497.575397 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 49526.305437 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 26392.335722 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 27313.714581 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 27448.613852 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27559.738909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 26774.917231 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 27613.063745 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 26643.425143 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 26896.813488 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 27085.680128 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 49986.975621 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 49971.519481 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 49975.390886 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 49962.522685 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 49952.484828 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 49965.982707 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 49953.924894 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 49933.975524 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 49962.900941 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 49906.628150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 49935.770399 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 49878.102895 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 49873.130934 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 49902.079548 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 49889.117336 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 49924.263503 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 49868.593341 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 49897.289656 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 49906.628150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 49935.770399 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 49878.102895 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 49873.130934 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 49902.079548 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 49889.117336 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 49924.263503 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 49868.593341 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 49897.289656 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 96627 # number of cycles access was blocked +system.l2c.overall_accesses::cpu7 17644 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141015 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.068515 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.068978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.067218 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.063467 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.061947 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.069834 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.068827 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.068510 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.067174 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.835566 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.842034 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.847985 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.843034 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.844707 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.856886 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.851869 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.857916 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.847516 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.696265 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.690531 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.694373 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.693506 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.689844 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.700672 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.702590 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.711665 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.697463 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.293301 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.284456 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.289865 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.280983 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.286149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.290819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.292719 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.295058 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.289182 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.293301 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.284456 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.289865 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.280983 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.286149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.290819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.292719 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.295058 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.289182 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 86231.025773 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 85145.951777 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 94192.870419 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 92374.168937 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 90191.591631 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 86165.683951 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 91335.139594 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 91126.856960 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 89536.778846 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28982.305141 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27889.094602 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27838.458963 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27944.695607 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28436.838426 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28519.504188 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 27655.694503 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 27104.189274 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28042.781352 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55761.905888 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 56112.594840 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54720.659530 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55017.502956 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55707.019832 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 56195.756047 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54662.565316 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55564.234682 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55466.256473 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 60330.801932 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 60712.169682 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 60624.490603 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 60542.345356 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 60506.740309 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 60871.341872 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 60239.174450 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 60912.973300 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 60592.834498 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 60330.801932 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 60712.169682 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 60624.490603 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 60542.345356 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 60506.740309 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 60871.341872 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 60239.174450 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 60912.973300 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 60592.834498 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 751039 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 19 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 217 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5085.631579 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 3461.009217 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6616 # number of writebacks -system.l2c.writebacks::total 6616 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 19 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6755 # number of writebacks +system.l2c.writebacks::total 6755 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 14 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 16 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 143 # 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number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 11 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 10 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 15 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 85 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 24 # number of demand (read+write) MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 14 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 17 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 12 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 14 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 11 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 5 # 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number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 34 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 31 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 234 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 27 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 33 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 32 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 34 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 30 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 27 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 242 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 714 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 736 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 763 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 713 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 757 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 749 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 785 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 732 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5949 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1952 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1933 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2006 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1960 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1920 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2007 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1916 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1894 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15588 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4342 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4376 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4248 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4311 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4338 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4326 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4224 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4275 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34440 # 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number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 173685720 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 175005460 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 169924253 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 172445652 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 173444745 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 173045540 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 168925276 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 170965174 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1377441820 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 202250474 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 204450395 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 200450676 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 200970482 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 203729262 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 203009268 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 200330127 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 200249838 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1615440522 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 202250474 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 204450395 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 200450676 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 200970482 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 203729262 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 203009268 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 200330127 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 200249838 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1615440522 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 400927744 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 396406972 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396807484 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 398767759 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 400808423 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 395927220 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 398767355 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 395367613 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3183780570 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 211603917 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215684252 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 216163665 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 212923402 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213723846 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 215924115 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217803639 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216444289 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1720271125 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 612531661 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 612091224 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 612971149 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 611691161 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 614532269 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 611851335 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 616570994 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 611811902 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4904051695 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.062260 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064789 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.067018 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.062588 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.066299 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066460 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.067754 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.065085 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842105 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.853045 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.855802 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850694 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.839528 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.843277 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841828 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853922 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.847496 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.692614 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.706832 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.698340 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691087 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695861 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689732 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.690535 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696594 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.695182 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.286561 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.286561 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40006.658263 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40006.705163 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40008.418087 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40006.774194 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40005.966975 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40004.977303 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40006.179618 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 40006.371585 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.505631 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.579918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39979.845835 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.600199 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.580612 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40000.623958 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39980.647733 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40000.517745 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.543823 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39995.438542 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40001.317365 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39992.106947 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 40001.001177 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40001.311065 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 39982.652144 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40001.280629 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 39991.779356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.853567 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39995.407085 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu2 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 29 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 34 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 31 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 234 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 763 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 774 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 751 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 717 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 677 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 785 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 768 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 758 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5993 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1807 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1871 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1852 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1911 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1931 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1910 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1892 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1902 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15076 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4385 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4177 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4327 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4217 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4272 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4373 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4383 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4418 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34552 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5148 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 4951 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5078 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 4934 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 4949 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5151 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5176 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40545 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5148 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 4951 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5078 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 4934 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 4949 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5151 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5176 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40545 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 58870730 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 58585309 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 63480686 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 59975234 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 54977009 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 60150971 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 63201488 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 61933736 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 481175163 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 75210107 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78015248 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77004240 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 79811462 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 80566647 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 79563303 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78963808 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 79283534 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 628418349 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 200402415 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192724360 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193590833 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189833874 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 195179728 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 201870094 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 195807052 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 201165400 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1570573756 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 259273145 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 251309669 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 257071519 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 249809108 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 250156737 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 262021065 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 259008540 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 263099136 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2051748919 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 259273145 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 251309669 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 257071519 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 249809108 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 250156737 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 262021065 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 259008540 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 263099136 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2051748919 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 422219130 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 432042675 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 419593939 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 421722054 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 422767760 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 422714984 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 423711086 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 417921325 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3382692953 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 236377012 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 240741589 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 239322336 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229099860 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 239042372 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232239121 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 232671200 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 242872940 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1892366430 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 658596142 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 672784264 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 658916275 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 650821914 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 661810132 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 654954105 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 656382286 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 660794265 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5275059383 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.067367 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.067752 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.066074 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061997 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060517 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.067678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.067080 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.066323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.065608 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.834642 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.842034 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.847985 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.842593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.844707 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.856886 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851869 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.857916 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847347 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.694049 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689047 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.691656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691538 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687591 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.699232 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.700831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.710861 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.695631 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.291771 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.283141 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.288163 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.279341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284425 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.288915 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.290968 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.293358 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.287523 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.291771 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.283141 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.288163 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.279341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284425 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.288915 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.290968 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.293358 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.287523 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 77156.920052 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 75691.613695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 84528.210386 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 83647.467225 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 81206.807976 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 76625.440764 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 82293.604167 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 81706.775726 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 80289.531620 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41621.531267 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41697.086050 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41578.963283 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41764.239665 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41722.758674 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41656.179581 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41735.627907 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41684.297581 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41683.360905 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45701.805017 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46139.420637 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44740.197134 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45016.332464 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45688.138577 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46162.838783 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44674.207620 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45533.137166 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 45455.364552 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 50363.858780 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 50759.375682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 50624.560654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 50630.139441 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 50546.926046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 50798.965684 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 50283.156669 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 50830.590417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 50604.240202 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 50363.858780 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 50759.375682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 50624.560654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 50630.139441 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 50546.926046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 50798.965684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 50283.156669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 50830.590417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 50604.240202 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -663,114 +657,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 99016 # number of read accesses completed -system.cpu0.num_writes 53340 # number of write accesses completed +system.cpu0.num_reads 98266 # number of read accesses completed +system.cpu0.num_writes 53265 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 21906 # number of replacements -system.cpu0.l1c.tagsinuse 396.590239 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13140 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22312 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.588921 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 21972 # number of replacements +system.cpu0.l1c.tagsinuse 389.500163 # Cycle average of tags in use +system.cpu0.l1c.total_refs 12866 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22378 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.574940 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 396.590239 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.774590 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.774590 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8561 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8561 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1051 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1051 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9612 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9612 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9612 # number of overall hits -system.cpu0.l1c.overall_hits::total 9612 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35875 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35875 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23186 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23186 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59061 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59061 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59061 # number of overall misses -system.cpu0.l1c.overall_misses::total 59061 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 894906998 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 894906998 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 820039819 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 820039819 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1714946817 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1714946817 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1714946817 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1714946817 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44436 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44436 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24237 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24237 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68673 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68673 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68673 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68673 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807341 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956637 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956637 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860032 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860032 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860032 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860032 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 24945.142801 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 24945.142801 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 35367.886613 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 35367.886613 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 29036.874029 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 29036.874029 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 29036.874029 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 29036.874029 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 154642800 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 389.500163 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.760743 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.760743 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8421 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8421 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1069 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1069 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9490 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9490 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9490 # number of overall hits +system.cpu0.l1c.overall_hits::total 9490 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35688 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35688 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23099 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23099 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58787 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58787 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58787 # number of overall misses +system.cpu0.l1c.overall_misses::total 58787 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1012085750 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1012085750 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 897172564 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 897172564 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1909258314 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1909258314 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1909258314 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1909258314 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44109 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44109 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24168 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24168 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68277 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68277 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68277 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68277 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809087 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809087 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955768 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955768 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861007 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861007 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861007 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861007 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 28359.273425 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 28359.273425 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38840.320533 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38840.320533 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 32477.559903 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 32477.559903 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 32477.559903 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 32477.559903 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 171686674 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 52409 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 2910.978089 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3275.900590 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks -system.cpu0.l1c.writebacks::total 9551 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35875 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35875 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23186 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59061 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59061 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59061 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59061 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 858892486 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 858892486 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 796764078 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 796764078 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1655656564 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1655656564 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1655656564 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1655656564 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 681029068 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 681029068 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 670499371 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 670499371 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1351528439 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1351528439 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807341 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956637 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956637 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860032 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860032 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 23941.253965 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 23941.253965 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34364.016130 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34364.016130 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9624 # number of writebacks +system.cpu0.l1c.writebacks::total 9624 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35688 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35688 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23099 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58787 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58787 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58787 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58787 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 976260004 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 976260004 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 873984178 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 873984178 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1850244182 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1850244182 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1850244182 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1850244182 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 721713598 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 721713598 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 736436829 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 736436829 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1458150427 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1458150427 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809087 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809087 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955768 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955768 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861007 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861007 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861007 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861007 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 27355.413696 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 27355.413696 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37836.450842 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37836.450842 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 31473.696259 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -778,114 +772,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99689 # number of read accesses completed -system.cpu1.num_writes 53832 # number of write accesses completed +system.cpu1.num_reads 99239 # number of read accesses completed +system.cpu1.num_writes 53491 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21971 # number of replacements -system.cpu1.l1c.tagsinuse 397.434568 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13255 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22377 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.592349 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21775 # number of replacements +system.cpu1.l1c.tagsinuse 388.085808 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13330 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22170 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.601263 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 397.434568 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.776239 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.776239 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8630 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8630 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1103 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1103 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9733 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9733 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9733 # number of overall hits -system.cpu1.l1c.overall_hits::total 9733 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36139 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36139 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23155 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23155 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 59294 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 59294 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 59294 # number of overall misses -system.cpu1.l1c.overall_misses::total 59294 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 902705787 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 902705787 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 819450505 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 819450505 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1722156292 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1722156292 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1722156292 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1722156292 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44769 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44769 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24258 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24258 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 69027 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 69027 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 69027 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 69027 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807233 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807233 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954530 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954530 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858997 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858997 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858997 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858997 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 24978.715155 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 24978.715155 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 35389.786439 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 35389.786439 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 29044.360171 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 29044.360171 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 29044.360171 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 29044.360171 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 155390130 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 388.085808 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.757980 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.757980 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8854 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8854 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1044 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1044 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9898 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9898 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9898 # number of overall hits +system.cpu1.l1c.overall_hits::total 9898 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35763 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35763 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22917 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22917 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58680 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58680 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58680 # number of overall misses +system.cpu1.l1c.overall_misses::total 58680 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1015131417 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1015131417 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 886463982 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 886463982 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1901595399 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1901595399 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1901595399 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1901595399 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44617 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44617 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23961 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23961 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68578 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68578 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68578 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68578 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.801555 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.801555 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956429 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.956429 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.855668 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.855668 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.855668 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.855668 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 28384.962587 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 28384.962587 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38681.502029 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38681.502029 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 32406.192894 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 32406.192894 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 32406.192894 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 32406.192894 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 173063141 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 53247 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 53052 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 2918.288918 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3262.141691 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks -system.cpu1.l1c.writebacks::total 9603 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36139 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36139 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23155 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23155 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 59294 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 59294 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 59294 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 59294 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 866427236 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 866427236 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 796207895 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 796207895 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1662635131 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1662635131 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1662635131 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1662635131 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 674093801 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 674093801 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 675943433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 675943433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1350037234 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1350037234 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807233 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807233 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954530 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954530 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858997 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858997 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23974.853648 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23974.853648 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34386.002807 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34386.002807 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9480 # number of writebacks +system.cpu1.l1c.writebacks::total 9480 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22917 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22917 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58680 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58680 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58680 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58680 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 979228369 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 979228369 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 863458324 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 863458324 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1842686693 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1842686693 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1842686693 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1842686693 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740677115 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740677115 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 739780589 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 739780589 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480457704 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480457704 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.801555 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.801555 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956429 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956429 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.855668 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.855668 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.855668 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.855668 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 27381.046584 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 27381.046584 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37677.633373 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37677.633373 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 31402.295382 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -893,114 +887,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99864 # number of read accesses completed -system.cpu2.num_writes 53679 # number of write accesses completed +system.cpu2.num_reads 98639 # number of read accesses completed +system.cpu2.num_writes 53360 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22117 # number of replacements -system.cpu2.l1c.tagsinuse 397.846327 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13470 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22518 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.598188 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 21788 # number of replacements +system.cpu2.l1c.tagsinuse 389.777022 # Cycle average of tags in use +system.cpu2.l1c.total_refs 12892 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22192 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.580930 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 397.846327 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.777044 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.777044 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8720 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1090 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1090 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9810 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9810 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9810 # number of overall hits -system.cpu2.l1c.overall_hits::total 9810 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36026 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36026 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23186 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23186 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59212 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59212 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59212 # number of overall misses -system.cpu2.l1c.overall_misses::total 59212 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 899117648 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 899117648 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 813653609 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 813653609 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1712771257 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1712771257 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1712771257 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1712771257 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44746 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44746 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24276 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24276 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 69022 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 69022 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 69022 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 69022 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805122 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805122 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955100 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955100 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857871 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857871 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857871 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857871 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 24957.465386 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 24957.465386 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 35092.452730 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 35092.452730 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 28926.083513 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 28926.083513 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 28926.083513 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 28926.083513 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 153072251 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 389.777022 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.761283 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.761283 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8419 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8419 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1037 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1037 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9456 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9456 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9456 # number of overall hits +system.cpu2.l1c.overall_hits::total 9456 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22886 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22886 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58678 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58678 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58678 # number of overall misses +system.cpu2.l1c.overall_misses::total 58678 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1023256428 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1023256428 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 895299843 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 895299843 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1918556271 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1918556271 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1918556271 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1918556271 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44211 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44211 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23923 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23923 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68134 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68134 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68134 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68134 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.809572 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.809572 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.956653 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.956653 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.861215 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.861215 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.861215 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.861215 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 28588.970384 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 28588.970384 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 39119.979158 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 39119.979158 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 32696.347370 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 32696.347370 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 32696.347370 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 32696.347370 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 172516137 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 52648 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 52707 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 2907.465640 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3273.116227 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9600 # number of writebacks -system.cpu2.l1c.writebacks::total 9600 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36026 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36026 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23186 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59212 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59212 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59212 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59212 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 862954550 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 862954550 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 790376865 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 790376865 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1653331415 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1653331415 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1653331415 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1653331415 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 676110998 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 676110998 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 681557695 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 681557695 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1357668693 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1357668693 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805122 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805122 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955100 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955100 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857871 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857871 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 23953.659857 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 23953.659857 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34088.538989 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34088.538989 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9481 # number of writebacks +system.cpu2.l1c.writebacks::total 9481 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22886 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22886 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58678 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58678 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58678 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58678 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 987321254 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 987321254 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 872322294 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 872322294 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1859643548 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1859643548 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1859643548 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1859643548 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 722326579 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 722326579 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 745926521 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 745926521 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1468253100 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1468253100 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.809572 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.809572 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.956653 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.956653 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861215 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.861215 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861215 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.861215 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 27584.970217 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 27584.970217 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 38115.978939 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 38115.978939 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 31692.347183 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1008,114 +1002,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98954 # number of read accesses completed -system.cpu3.num_writes 53519 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53214 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21866 # number of replacements -system.cpu3.l1c.tagsinuse 395.683419 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13218 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22277 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.593347 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22201 # number of replacements +system.cpu3.l1c.tagsinuse 390.202631 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13426 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22601 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.594045 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.683419 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.772819 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.772819 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1098 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9660 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9660 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9660 # number of overall hits -system.cpu3.l1c.overall_hits::total 9660 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35996 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35996 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23029 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23029 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59025 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59025 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59025 # number of overall misses -system.cpu3.l1c.overall_misses::total 59025 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 899058428 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 899058428 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 817455350 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 817455350 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1716513778 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1716513778 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1716513778 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1716513778 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44558 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44558 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24127 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68685 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68685 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68685 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68685 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807846 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807846 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954491 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954491 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859358 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859358 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859358 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859358 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 24976.620402 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 24976.620402 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 35496.780147 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 35496.780147 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 29081.131351 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 29081.131351 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 29081.131351 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 29081.131351 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 155038956 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 390.202631 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.762115 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.762115 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8779 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8779 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1080 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1080 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9859 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9859 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9859 # number of overall hits +system.cpu3.l1c.overall_hits::total 9859 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36255 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36255 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22971 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22971 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59226 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59226 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59226 # number of overall misses +system.cpu3.l1c.overall_misses::total 59226 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1029467396 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1029467396 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 892890764 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 892890764 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1922358160 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1922358160 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1922358160 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1922358160 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45034 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45034 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24051 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24051 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 69085 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 69085 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 69085 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 69085 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805058 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805058 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955095 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955095 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.857292 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.857292 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.857292 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.857292 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 28395.184002 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 28395.184002 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38870.348004 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38870.348004 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 32458.011009 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 32458.011009 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 32458.011009 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 32458.011009 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 173404945 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 53526 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 2918.435283 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3239.639521 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9442 # number of writebacks -system.cpu3.l1c.writebacks::total 9442 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35996 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35996 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23029 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23029 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59025 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59025 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59025 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59025 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 862924447 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 862924447 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794336234 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794336234 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1657260681 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1657260681 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1657260681 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1657260681 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 680106792 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 680106792 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 674669668 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 674669668 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1354776460 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1354776460 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807846 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807846 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954491 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954491 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859358 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859358 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23972.787171 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23972.787171 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34492.866994 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34492.866994 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9609 # number of writebacks +system.cpu3.l1c.writebacks::total 9609 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36255 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36255 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22971 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22971 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59226 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59226 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59226 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59226 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 993072387 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 993072387 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869829882 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869829882 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1862902269 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1862902269 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1862902269 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1862902269 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 723358193 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 723358193 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 722023340 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 722023340 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1445381533 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1445381533 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805058 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805058 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955095 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955095 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857292 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.857292 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857292 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.857292 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 27391.322218 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 27391.322218 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37866.435157 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37866.435157 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 31454.129420 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1123,114 +1117,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99591 # number of read accesses completed -system.cpu4.num_writes 53646 # number of write accesses completed +system.cpu4.num_reads 98672 # number of read accesses completed +system.cpu4.num_writes 53449 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22293 # number of replacements -system.cpu4.l1c.tagsinuse 397.816545 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13327 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22684 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.587507 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 21899 # number of replacements +system.cpu4.l1c.tagsinuse 389.567143 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13162 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22307 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.590039 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 397.816545 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.776985 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.776985 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8743 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8743 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1036 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1036 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9779 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9779 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9779 # number of overall hits -system.cpu4.l1c.overall_hits::total 9779 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35998 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35998 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23232 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23232 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59230 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59230 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59230 # number of overall misses -system.cpu4.l1c.overall_misses::total 59230 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 899681935 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 899681935 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 816003996 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 816003996 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1715685931 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1715685931 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1715685931 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1715685931 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44741 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24268 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24268 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69009 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69009 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69009 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69009 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804586 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804586 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.957310 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.957310 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858294 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858294 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858294 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858294 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 24992.553336 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 24992.553336 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 35124.138946 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 35124.138946 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 28966.502296 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 28966.502296 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 28966.502296 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 28966.502296 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 154355931 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 389.567143 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.760873 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.760873 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8516 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8516 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1086 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1086 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9602 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9602 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9602 # number of overall hits +system.cpu4.l1c.overall_hits::total 9602 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35797 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35797 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23063 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23063 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 58860 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 58860 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 58860 # number of overall misses +system.cpu4.l1c.overall_misses::total 58860 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1014475710 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1014475710 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 905483061 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 905483061 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1919958771 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1919958771 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1919958771 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1919958771 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44313 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44313 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24149 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24149 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68462 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68462 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68462 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68462 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807822 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807822 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955029 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859747 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859747 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859747 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859747 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 28339.685169 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 28339.685169 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 39261.286953 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 39261.286953 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 32619.075280 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 32619.075280 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 32619.075280 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 32619.075280 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 173090211 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 53171 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 52926 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 2903.009742 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3270.419284 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9702 # number of writebacks -system.cpu4.l1c.writebacks::total 9702 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35998 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35998 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23232 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23232 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59230 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59230 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59230 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59230 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 863541936 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 863541936 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 792684079 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 792684079 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1656226015 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1656226015 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1656226015 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1656226015 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 681350371 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 681350371 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 669996228 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 669996228 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1351346599 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1351346599 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804586 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804586 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.957310 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.957310 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858294 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858294 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 23988.608700 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 23988.608700 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34120.354640 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34120.354640 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9537 # number of writebacks +system.cpu4.l1c.writebacks::total 9537 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35797 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35797 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23063 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23063 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 58860 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 58860 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 58860 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 58860 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 978543547 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 978543547 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 882330817 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 882330817 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1860874364 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1860874364 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1860874364 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1860874364 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 726225983 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 726225983 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 739406150 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 739406150 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1465632133 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1465632133 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807822 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807822 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955029 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859747 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859747 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859747 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859747 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 27335.909350 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 27335.909350 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 38257.417378 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 38257.417378 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 31615.262725 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1238,114 +1232,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99523 # number of read accesses completed -system.cpu5.num_writes 53948 # number of write accesses completed +system.cpu5.num_reads 98938 # number of read accesses completed +system.cpu5.num_writes 52979 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22088 # number of replacements -system.cpu5.l1c.tagsinuse 397.555659 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13442 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22486 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.597794 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22003 # number of replacements +system.cpu5.l1c.tagsinuse 389.145531 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13186 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22409 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.588424 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 397.555659 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.776476 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.776476 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8700 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8700 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1066 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1066 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9766 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9766 # number of overall hits -system.cpu5.l1c.overall_hits::total 9766 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36016 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36016 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23333 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23333 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59349 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59349 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59349 # number of overall misses -system.cpu5.l1c.overall_misses::total 59349 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 899040098 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 899040098 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 826704780 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 826704780 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1725744878 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1725744878 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1725744878 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1725744878 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44716 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24399 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24399 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69115 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69115 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69115 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69115 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805439 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.805439 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956310 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.956310 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858699 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858699 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858699 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858699 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 24962.241726 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 24962.241726 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 35430.711010 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 35430.711010 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 29077.909956 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 29077.909956 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 29077.909956 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 29077.909956 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 155795508 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 389.145531 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.760050 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.760050 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1030 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1030 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9667 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9667 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9667 # number of overall hits +system.cpu5.l1c.overall_hits::total 9667 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36114 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36114 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22950 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22950 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59064 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59064 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59064 # number of overall misses +system.cpu5.l1c.overall_misses::total 59064 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1023713867 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1023713867 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 899864913 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 899864913 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1923578780 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1923578780 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1923578780 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1923578780 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44751 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44751 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 23980 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 23980 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68731 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68731 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68731 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68731 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806999 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806999 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.957048 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.957048 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859350 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859350 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859350 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859350 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 28346.731655 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 28346.731655 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 39209.800131 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 39209.800131 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 32567.702492 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 32567.702492 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 32567.702492 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 32567.702492 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 172870705 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 53352 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 53593 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 2920.143725 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3225.620977 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9610 # number of writebacks -system.cpu5.l1c.writebacks::total 9610 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36016 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36016 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23333 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23333 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59349 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59349 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59349 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59349 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 862885041 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 862885041 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 803284460 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 803284460 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1666169501 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1666169501 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1666169501 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1666169501 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 674425818 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 674425818 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 675374924 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 675374924 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1349800742 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1349800742 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805439 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805439 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956310 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956310 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858699 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858699 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 23958.380747 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 23958.380747 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 34426.968671 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 34426.968671 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9578 # number of writebacks +system.cpu5.l1c.writebacks::total 9578 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36114 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36114 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22950 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22950 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59064 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59064 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59064 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59064 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 987460421 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 987460421 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 876826122 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 876826122 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1864286543 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1864286543 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1864286543 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1864286543 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 726267830 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 726267830 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 727074165 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 727074165 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1453341995 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1453341995 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806999 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.957048 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.957048 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859350 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859350 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859350 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859350 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 27342.870383 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 27342.870383 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 38205.931242 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 38205.931242 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 31563.838260 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1353,114 +1347,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53510 # number of write accesses completed +system.cpu6.num_reads 98714 # number of read accesses completed +system.cpu6.num_writes 53264 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 22177 # number of replacements -system.cpu6.l1c.tagsinuse 397.660479 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13364 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22573 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.592035 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21950 # number of replacements +system.cpu6.l1c.tagsinuse 389.196991 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13256 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22357 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.592924 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 397.660479 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.776681 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.776681 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8760 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8760 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1035 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1035 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9795 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9795 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9795 # number of overall hits -system.cpu6.l1c.overall_hits::total 9795 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36279 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36279 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 59312 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 59312 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 59312 # number of overall misses -system.cpu6.l1c.overall_misses::total 59312 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 908517794 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 908517794 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 809582336 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 809582336 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1718100130 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1718100130 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1718100130 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1718100130 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45039 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45039 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24068 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24068 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 69107 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 69107 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 69107 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 69107 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805502 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805502 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956997 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956997 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858263 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858263 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858263 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858263 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 25042.525814 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 25042.525814 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 35148.801111 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 35148.801111 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 28967.158922 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 28967.158922 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 28967.158922 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 28967.158922 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 154185284 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 389.196991 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.760150 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.760150 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8708 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8708 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1082 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1082 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9790 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9790 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9790 # number of overall hits +system.cpu6.l1c.overall_hits::total 9790 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35839 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35839 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23075 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23075 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58914 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58914 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58914 # number of overall misses +system.cpu6.l1c.overall_misses::total 58914 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1020128042 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1020128042 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 903798683 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 903798683 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1923926725 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1923926725 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1923926725 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1923926725 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44547 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44547 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24157 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24157 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68704 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68704 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68704 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68704 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804521 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.804521 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955210 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.955210 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.857505 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.857505 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.857505 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.857505 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 28464.188231 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 28464.188231 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 39167.873586 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 39167.873586 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 32656.528584 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 32656.528584 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 32656.528584 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 32656.528584 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 174295545 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 52977 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 53485 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 2910.419314 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3258.774329 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9564 # number of writebacks -system.cpu6.l1c.writebacks::total 9564 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36279 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36279 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 59312 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 59312 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 59312 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 59312 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 872097671 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 872097671 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 786461211 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 786461211 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1658558882 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1658558882 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1658558882 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1658558882 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 680107967 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 680107967 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 681972539 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 681972539 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1362080506 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1362080506 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805502 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805502 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956997 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956997 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858263 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858263 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24038.635878 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24038.635878 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34144.975079 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34144.975079 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9548 # number of writebacks +system.cpu6.l1c.writebacks::total 9548 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35839 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35839 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23075 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23075 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58914 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58914 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 984150696 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 984150696 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 880635396 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 880635396 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1864786092 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1864786092 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1864786092 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1864786092 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 725723754 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 725723754 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 729548625 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 729548625 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1455272379 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1455272379 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804521 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804521 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955210 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955210 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857505 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.857505 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857505 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.857505 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 27460.328023 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 27460.328023 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 38164.047497 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 38164.047497 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 31652.681739 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1468,114 +1462,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99201 # number of read accesses completed -system.cpu7.num_writes 53497 # number of write accesses completed +system.cpu7.num_reads 98633 # number of read accesses completed +system.cpu7.num_writes 53420 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22218 # number of replacements -system.cpu7.l1c.tagsinuse 396.828031 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13271 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22622 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.586641 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 21845 # number of replacements +system.cpu7.l1c.tagsinuse 390.265182 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13266 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22252 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.596171 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 396.828031 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.775055 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.775055 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8703 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8703 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1096 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9799 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9799 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9799 # number of overall hits -system.cpu7.l1c.overall_hits::total 9799 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36453 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36453 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22910 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22910 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59363 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59363 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59363 # number of overall misses -system.cpu7.l1c.overall_misses::total 59363 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 908883238 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 908883238 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 808946616 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 808946616 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1717829854 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1717829854 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1717829854 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1717829854 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69162 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69162 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69162 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69162 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807268 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954345 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954345 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858318 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858318 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858318 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858318 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 24933.016158 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 24933.016158 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 35309.760629 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 35309.760629 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 28937.719691 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 28937.719691 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 28937.719691 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 28937.719691 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 153732048 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 390.265182 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.762237 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.762237 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8641 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8641 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1118 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1118 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9759 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9759 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9759 # number of overall hits +system.cpu7.l1c.overall_hits::total 9759 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35823 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35823 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22965 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22965 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 58788 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 58788 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 58788 # number of overall misses +system.cpu7.l1c.overall_misses::total 58788 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1021778024 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1021778024 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 908326044 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 908326044 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1930104068 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1930104068 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1930104068 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1930104068 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44464 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44464 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68547 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68547 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68547 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68547 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805663 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805663 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953577 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953577 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857631 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857631 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857631 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857631 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 28522.960779 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 28522.960779 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 39552.625474 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 39552.625474 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 32831.599442 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 32831.599442 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 32831.599442 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 32831.599442 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 173409503 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 53029 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 52851 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 2899.018424 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3281.101644 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9581 # number of writebacks -system.cpu7.l1c.writebacks::total 9581 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36453 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36453 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22910 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22910 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59363 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59363 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59363 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59363 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 872289420 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 872289420 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 785947981 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 785947981 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1658237401 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1658237401 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1658237401 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1658237401 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 674384984 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 674384984 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 681937361 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 681937361 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1356322345 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1356322345 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807268 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954345 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954345 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858318 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858318 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23929.153156 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23929.153156 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34305.891794 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34305.891794 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9467 # number of writebacks +system.cpu7.l1c.writebacks::total 9467 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35823 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35823 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22965 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 58788 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 58788 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 58788 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 58788 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 985813733 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 985813733 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 885270188 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 885270188 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1871083921 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1871083921 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1871083921 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1871083921 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 719750432 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 719750432 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 746183664 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 746183664 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1465934096 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1465934096 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805663 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805663 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953577 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953577 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857631 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857631 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857631 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857631 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 27519.016637 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 27519.016637 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 38548.669192 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 38548.669192 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 31827.650558 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |